drt: Adjust tests

Signed-off-by: Krzysztof Bieganski <[email protected]>
antmicro · Jan 10, 2025 · bf4cb1e · bf4cb1e
1 parent 84e0d57
commit bf4cb1e
Show file tree

Hide file tree

Showing 11 changed files with 850 additions and 511 deletions.
diff --git a/src/drt/test/ispd18_sample.defok b/src/drt/test/ispd18_sample.defok
@@ -55,12 +55,15 @@ COMPONENTS 22 ;
 END COMPONENTS
 NETS 11 ;
     - net1230 ( inst7234 Y ) ( inst5195 C0 ) + USE SIGNAL
-      + ROUTED Metal2 ( 92200 73530 ) ( * 78850 )
-      NEW Metal3 ( 92200 78850 ) ( 95800 * )
+      + ROUTED Metal2 ( 92200 73530 ) ( * 75810 )
+      NEW Metal1 ( 92200 75810 ) ( 94200 * )
+      NEW Metal1 ( 94200 75810 ) ( 94600 * )
+      NEW Metal2 ( 94600 75810 ) ( * 78850 )
+      NEW Metal2 ( 94600 78850 ) ( 95800 * )
       NEW Metal2 ( 95800 78850 ) ( * 83790 )
       NEW Metal1 ( 92200 73530 ) VIA12_1C_V
-      NEW Metal2 ( 92200 78850 ) VIA23_1C
-      NEW Metal2 ( 95800 78850 ) VIA23_1C
+      NEW Metal1 ( 92200 75810 ) VIA12_1C
+      NEW Metal1 ( 94600 75810 ) VIA12_1C
       NEW Metal1 ( 95800 83790 ) VIA12_1C_V ;
     - net1231 ( inst5821 B ) ( inst5275 Y ) + USE SIGNAL
       + ROUTED Metal3 ( 85800 77710 ) ( 91000 * )
@@ -97,7 +100,8 @@ NETS 11 ;
       NEW Metal2 ( 95400 73530 ) RECT ( -70 -442 70 0 )  ;
     - net1235 ( inst4183 A ) ( inst4132 Y ) + USE SIGNAL
       + ROUTED Metal2 ( 103000 84930 ) ( * 87590 )
-      NEW Metal1 ( 98600 84930 ) ( 103000 * )
+      NEW Metal1 ( 100600 84930 ) ( 103000 * )
+      NEW Metal1 ( 98600 84930 ) ( 100600 * )
       NEW Metal2 ( 98600 76950 ) ( * 84930 )
       NEW Metal1 ( 103000 87590 ) VIA12_1C
       NEW Metal1 ( 103000 84930 ) VIA12_1C
@@ -136,12 +140,16 @@ NETS 11 ;
       NEW Metal1 ( 91800 86830 ) VIA12_1C_V
       NEW Metal2 ( 102600 80370 ) RECT ( -70 -442 70 0 )  ;
     - net1240 ( inst3502 A ) ( inst2015 Y ) + USE SIGNAL
-      + ROUTED Metal2 ( 91000 78470 ) ( * 80750 )
-      NEW Metal3 ( 91000 78470 ) ( 96200 * )
-      NEW Metal2 ( 96200 76950 ) ( * 78470 )
+      + ROUTED Metal2 ( 91000 80750 ) ( 91400 * )
+      NEW Metal2 ( 91400 78090 ) ( * 80750 )
+      NEW Metal1 ( 91400 78090 ) ( 93400 * )
+      NEW Metal1 ( 93400 78090 ) ( 95400 * )
+      NEW Metal2 ( 95400 78090 ) ( 95800 * )
+      NEW Metal2 ( 95800 76950 ) ( * 78090 )
+      NEW Metal2 ( 95800 76950 ) ( 96200 * )
       NEW Metal1 ( 91000 80750 ) VIA12_1C
-      NEW Metal2 ( 91000 78470 ) VIA23_1C
-      NEW Metal2 ( 96200 78470 ) VIA23_1C
+      NEW Metal1 ( 91400 78090 ) VIA12_1C
+      NEW Metal1 ( 95400 78090 ) VIA12_1C
       NEW Metal1 ( 96200 76950 ) VIA12_1C_V ;
 END NETS
 END DESIGN
diff --git a/src/drt/test/ndr_vias1.defok b/src/drt/test/ndr_vias1.defok
diff --git a/src/drt/test/ndr_vias2.defok b/src/drt/test/ndr_vias2.defok
diff --git a/src/drt/test/obstruction.defok b/src/drt/test/obstruction.defok
@@ -35,14 +35,19 @@ BLOCKAGES 1 ;
 END BLOCKAGES
 NETS 1 ;
     - clk ( PIN clk ) ( clkbuf_0_clk A ) ( clkbuf_2_3__f_clk A ) ( clkbuf_2_2__f_clk A ) ( clkbuf_2_1__f_clk A ) + USE SIGNAL
-      + ROUTED met5 ( 2400 155030 0 ) ( 21600 * )
+      + ROUTED met2 ( 145200 144855 ) ( * 147630 )
+      NEW met5 ( 2400 155030 0 ) ( 21600 * )
+      NEW met3 ( 21600 155030 ) ( 25680 * )
       NEW met2 ( 112080 154845 ) ( * 155030 )
+      NEW met3 ( 108960 155030 ) ( 112080 * )
       NEW met1 ( 112080 158175 ) ( 135600 * )
       NEW met2 ( 112080 155030 ) ( * 158175 )
-      NEW met1 ( 135600 158175 ) ( 144240 * )
+      NEW met1 ( 138720 158175 ) ( 144240 * )
+      NEW met1 ( 135600 158175 ) ( 138720 * )
       NEW met1 ( 144240 158175 ) ( 145200 * )
-      NEW met2 ( 145200 144855 ) ( * 158175 )
-      NEW met3 ( 21600 155030 ) ( 112080 * )
+      NEW met2 ( 145200 147630 ) ( * 158175 )
+      NEW met3 ( 25680 155030 ) ( 75360 * )
+      NEW met3 ( 75360 155030 ) ( 108960 * )
       NEW li1 ( 145200 144855 ) L1M1_PR_MR
       NEW met1 ( 145200 144855 ) M1M2_PR
       NEW met3 ( 21600 155030 ) M3M4_PR

diff --git a/src/drt/test/single_step.defok b/src/drt/test/single_step.defok
@@ -0,0 +1,156 @@
+VERSION 5.8 ;
+DIVIDERCHAR "/" ;
+BUSBITCHARS "[]" ;
+DESIGN ispd18_sample ;
+UNITS DISTANCE MICRONS 2000 ;
+DIEAREA ( 83600 71820 ) ( 104400 91200 ) ;
+ROW CORE_ROW_0 CoreSite 83600 71820 N DO 52 BY 1 STEP 400 0 ;
+ROW CORE_ROW_1 CoreSite 83600 75240 FS DO 52 BY 1 STEP 400 0 ;
+ROW CORE_ROW_2 CoreSite 83600 78660 N DO 52 BY 1 STEP 400 0 ;
+ROW CORE_ROW_3 CoreSite 83600 82080 FS DO 52 BY 1 STEP 400 0 ;
+ROW CORE_ROW_4 CoreSite 83600 85500 N DO 52 BY 1 STEP 400 0 ;
+TRACKS X 83800 DO 52 STEP 400 LAYER Metal9 ;
+TRACKS Y 72770 DO 25 STEP 760 LAYER Metal9 ;
+TRACKS X 83800 DO 52 STEP 400 LAYER Metal8 ;
+TRACKS Y 72580 DO 33 STEP 570 LAYER Metal8 ;
+TRACKS X 83800 DO 52 STEP 400 LAYER Metal7 ;
+TRACKS Y 72580 DO 33 STEP 570 LAYER Metal7 ;
+TRACKS X 83800 DO 52 STEP 400 LAYER Metal6 ;
+TRACKS Y 72010 DO 51 STEP 380 LAYER Metal6 ;
+TRACKS X 83800 DO 52 STEP 400 LAYER Metal5 ;
+TRACKS Y 72010 DO 51 STEP 380 LAYER Metal5 ;
+TRACKS X 83800 DO 52 STEP 400 LAYER Metal4 ;
+TRACKS Y 72010 DO 51 STEP 380 LAYER Metal4 ;
+TRACKS X 83800 DO 52 STEP 400 LAYER Metal3 ;
+TRACKS Y 72010 DO 51 STEP 380 LAYER Metal3 ;
+TRACKS X 83800 DO 52 STEP 400 LAYER Metal2 ;
+TRACKS Y 72010 DO 51 STEP 380 LAYER Metal2 ;
+TRACKS X 83800 DO 52 STEP 400 LAYER Metal1 ;
+TRACKS Y 72010 DO 51 STEP 380 LAYER Metal1 ;
+GCELLGRID X 83600 DO 3 STEP 6000 ;
+GCELLGRID Y 71820 DO 3 STEP 5700 ;
+COMPONENTS 22 ;
+    - inst2015 NAND3X2 + PLACED ( 88000 78660 ) N ;
+    - inst2591 NAND4X2 + PLACED ( 100000 71820 ) N ;
+    - inst2908 OR4X1 + PLACED ( 85600 75240 ) FS ;
+    - inst3428 BUFX3 + PLACED ( 86000 82080 ) FS ;
+    - inst3444 BUFX3 + PLACED ( 96800 82080 ) FS ;
+    - inst3502 NOR4X2 + PLACED ( 92800 75240 ) FS ;
+    - inst4062 AOI222X1 + PLACED ( 96000 85500 ) N ;
+    - inst4132 NAND4X1 + PLACED ( 102000 85500 ) N ;
+    - inst4183 NOR4X4 + PLACED ( 96800 75240 ) FS ;
+    - inst4189 AOI22X2 + PLACED ( 85200 71820 ) N ;
+    - inst4382 NAND4X1 + PLACED ( 84000 78660 ) N ;
+    - inst4597 NAND4X1 + PLACED ( 94400 71820 ) N ;
+    - inst4678 NOR2X1 + PLACED ( 90800 82080 ) FS ;
+    - inst5195 AOI221X1 + PLACED ( 89600 71820 ) N ;
+    - inst5275 AOI22X1 + PLACED ( 89600 75240 ) FS ;
+    - inst5333 AOI221X1 + PLACED ( 89200 85500 ) N ;
+    - inst5638 BUFX6 + PLACED ( 96000 78660 ) N ;
+    - inst5821 NAND3X1 + PLACED ( 84400 85500 ) N ;
+    - inst6050 NAND4X1 + PLACED ( 97200 71820 ) N ;
+    - inst6286 AO22XL + PLACED ( 100000 78660 ) N ;
+    - inst6458 AOI221X2 + PLACED ( 99200 82080 ) FS ;
+    - inst7234 AO22XL + PLACED ( 93200 82080 ) FS ;
+END COMPONENTS
+NETS 11 ;
+    - net1230 ( inst7234 Y ) ( inst5195 C0 ) + USE SIGNAL
+      + ROUTED Metal2 ( 92200 73530 ) ( * 75810 )
+      NEW Metal1 ( 92200 75810 ) ( 94200 * )
+      NEW Metal1 ( 94200 75810 ) ( 94600 * )
+      NEW Metal2 ( 94600 75810 ) ( * 78850 )
+      NEW Metal2 ( 94600 78850 ) ( 95800 * )
+      NEW Metal2 ( 95800 78850 ) ( * 83790 )
+      NEW Metal1 ( 92200 73530 ) VIA12_1C_V
+      NEW Metal1 ( 92200 75810 ) VIA12_1C
+      NEW Metal1 ( 94600 75810 ) VIA12_1C
+      NEW Metal1 ( 95800 83790 ) VIA12_1C_V ;
+    - net1231 ( inst5821 B ) ( inst5275 Y ) + USE SIGNAL
+      + ROUTED Metal3 ( 85800 77710 ) ( 91000 * )
+      NEW Metal2 ( 85800 77710 ) ( * 86450 )
+      NEW Metal2 ( 85400 86450 ) ( 85800 * )
+      NEW Metal1 ( 91000 77710 ) VIA12_1C_V
+      NEW Metal2 ( 91000 77710 ) VIA23_1C
+      NEW Metal2 ( 85800 77710 ) VIA23_1C
+      NEW Metal1 ( 85400 86450 ) VIA12_1C_V
+      NEW Metal2 ( 91000 77710 ) RECT ( -70 -442 70 0 )  ;
+    - net1232 ( inst4382 C ) ( inst4062 Y ) + USE SIGNAL
+      + ROUTED Metal3 ( 85400 79990 ) ( 98200 * )
+      NEW Metal2 ( 98200 79990 ) ( * 86450 )
+      NEW Metal1 ( 85400 79990 ) VIA12_1C_V
+      NEW Metal2 ( 85400 79990 ) VIA23_1C
+      NEW Metal2 ( 98200 79990 ) VIA23_1C
+      NEW Metal1 ( 98200 86450 ) VIA12_1C
+      NEW Metal2 ( 85400 79990 ) RECT ( -70 -442 70 0 )  ;
+    - net1233 ( inst6050 A ) ( inst4189 Y ) + USE SIGNAL
+      + ROUTED Metal2 ( 88200 72770 ) ( * 73150 )
+      NEW Metal3 ( 88200 73150 ) ( 97800 * )
+      NEW Metal1 ( 88200 72770 ) VIA12_1C
+      NEW Metal2 ( 88200 73150 ) VIA23_1C
+      NEW Metal1 ( 97800 73150 ) VIA12_1C
+      NEW Metal2 ( 97800 73150 ) VIA23_1C
+      NEW Metal2 ( 97800 73150 ) RECT ( -70 -442 70 0 )  ;
+    - net1234 ( inst6458 Y ) ( inst4597 B ) + USE SIGNAL
+      + ROUTED Metal3 ( 95400 73530 ) ( 101400 * )
+      NEW Metal2 ( 101400 73530 ) ( * 83410 )
+      NEW Metal1 ( 95400 73530 ) VIA12_1C_V
+      NEW Metal2 ( 95400 73530 ) VIA23_1C
+      NEW Metal2 ( 101400 73530 ) VIA23_1C
+      NEW Metal1 ( 101400 83410 ) VIA12_1C
+      NEW Metal2 ( 95400 73530 ) RECT ( -70 -442 70 0 )  ;
+    - net1235 ( inst4183 A ) ( inst4132 Y ) + USE SIGNAL
+      + ROUTED Metal2 ( 103000 84930 ) ( * 87590 )
+      NEW Metal1 ( 100600 84930 ) ( 103000 * )
+      NEW Metal1 ( 98600 84930 ) ( 100600 * )
+      NEW Metal2 ( 98600 76950 ) ( * 84930 )
+      NEW Metal1 ( 103000 87590 ) VIA12_1C
+      NEW Metal1 ( 103000 84930 ) VIA12_1C
+      NEW Metal1 ( 98600 84930 ) VIA12_1C
+      NEW Metal1 ( 98600 76950 ) VIA12_1C_V ;
+    - net1236 ( inst2908 D ) ( inst2591 Y ) + USE SIGNAL
+      + ROUTED Metal3 ( 85800 76950 ) ( 102600 * )
+      NEW Metal2 ( 102600 72770 ) ( * 76950 )
+      NEW Metal1 ( 85800 76950 ) VIA12_1C_V
+      NEW Metal2 ( 85800 76950 ) VIA23_1C
+      NEW Metal2 ( 102600 76950 ) VIA23_1C
+      NEW Metal1 ( 102600 72770 ) VIA12_1C
+      NEW Metal2 ( 85800 76950 ) RECT ( -70 -442 70 0 )  ;
+    - net1237 ( inst5638 A ) ( inst4678 Y ) + USE SIGNAL
+      + ROUTED Metal3 ( 92200 80750 ) ( 99000 * )
+      NEW Metal2 ( 92200 80750 ) ( * 83030 )
+      NEW Metal1 ( 99000 80750 ) VIA12_1C
+      NEW Metal2 ( 99000 80750 ) VIA23_1C
+      NEW Metal2 ( 92200 80750 ) VIA23_1C
+      NEW Metal1 ( 92200 83030 ) VIA12_1C_V
+      NEW Metal2 ( 99000 80750 ) RECT ( -70 -442 70 0 )  ;
+    - net1238 ( inst3444 Y ) ( inst3428 A ) + USE SIGNAL
+      + ROUTED Metal3 ( 87800 83410 ) ( 88600 * )
+      NEW Metal3 ( 88600 83410 ) ( 97400 * )
+      NEW Metal1 ( 87800 83410 ) VIA12_1C_V
+      NEW Metal2 ( 87800 83410 ) VIA23_1C
+      NEW Metal1 ( 97400 83410 ) VIA12_1C_V
+      NEW Metal2 ( 97400 83410 ) VIA23_1C
+      NEW Metal2 ( 87800 83410 ) RECT ( -70 -442 70 0 ) 
+      NEW Metal2 ( 97400 83410 ) RECT ( -70 -442 70 0 )  ;
+    - net1239 ( inst6286 Y ) ( inst5333 C0 ) + USE SIGNAL
+      + ROUTED Metal3 ( 91800 80370 ) ( 102600 * )
+      NEW Metal2 ( 91800 80370 ) ( * 86830 )
+      NEW Metal1 ( 102600 80370 ) VIA12_1C_V
+      NEW Metal2 ( 102600 80370 ) VIA23_1C
+      NEW Metal2 ( 91800 80370 ) VIA23_1C
+      NEW Metal1 ( 91800 86830 ) VIA12_1C_V
+      NEW Metal2 ( 102600 80370 ) RECT ( -70 -442 70 0 )  ;
+    - net1240 ( inst3502 A ) ( inst2015 Y ) + USE SIGNAL
+      + ROUTED Metal2 ( 91000 80750 ) ( 91400 * )
+      NEW Metal2 ( 91400 78090 ) ( * 80750 )
+      NEW Metal1 ( 91400 78090 ) ( 93400 * )
+      NEW Metal1 ( 93400 78090 ) ( 95400 * )
+      NEW Metal2 ( 95400 78090 ) ( 95800 * )
+      NEW Metal2 ( 95800 76950 ) ( * 78090 )
+      NEW Metal2 ( 95800 76950 ) ( 96200 * )
+      NEW Metal1 ( 91000 80750 ) VIA12_1C
+      NEW Metal1 ( 91400 78090 ) VIA12_1C
+      NEW Metal1 ( 95400 78090 ) VIA12_1C
+      NEW Metal1 ( 96200 76950 ) VIA12_1C_V ;
+END NETS
+END DESIGN
diff --git a/src/drt/test/single_step.py b/src/drt/test/single_step.py
@@ -25,4 +25,4 @@
 
 def_file = helpers.make_result_file("single_step.def")
 design.writeDef(def_file)
-helpers.diff_files("ispd18_sample.defok", def_file)
+helpers.diff_files("single_step.defok", def_file)
diff --git a/src/drt/test/single_step.tcl b/src/drt/test/single_step.tcl
@@ -17,4 +17,4 @@ drt::step_end
 set def_file [make_result_file single_step.def]
 write_def $def_file
 # Single stepping should produce the same result as a regular run
-diff_files ispd18_sample.defok $def_file
+diff_files single_step.defok $def_file
diff --git a/src/drt/test/ta_ap_aligned.defok b/src/drt/test/ta_ap_aligned.defok
@@ -105,11 +105,25 @@ COMPONENTS 4 ;
 END COMPONENTS
 NETS 2 ;
     - net_M2 ( inv_M2_2 A ) ( inv_M2_1 A ) + USE SIGNAL
-      + ROUTED metal2 ( 100130 21140 ) ( * 180460 )
+      + ROUTED metal2 ( 100130 21140 ) ( * 25060 )
+      NEW metal2 ( 100130 178780 ) ( * 180460 )
+      NEW metal2 ( 100130 25060 ) ( * 44100 )
+      NEW metal2 ( 100130 44100 ) ( * 73740 )
+      NEW metal2 ( 100130 73740 ) ( * 103180 )
+      NEW metal2 ( 100130 103180 ) ( * 132300 )
+      NEW metal2 ( 100130 132300 ) ( * 161740 )
+      NEW metal2 ( 100130 161740 ) ( * 178780 )
       NEW metal1 ( 100130 21140 ) via1_4
       NEW metal1 ( 100130 180460 ) via1_4 ;
     - net_M3 ( inv_M3_2 A ) ( inv_M3_1 A ) + USE SIGNAL
-      + ROUTED metal3 ( 20330 102060 ) ( 180310 * )
+      + ROUTED metal3 ( 20330 102060 ) ( 24830 * )
+      NEW metal3 ( 178410 102060 ) ( 180310 * )
+      NEW metal3 ( 24830 102060 ) ( 43890 * )
+      NEW metal3 ( 43890 102060 ) ( 73530 * )
+      NEW metal3 ( 73530 102060 ) ( 103170 * )
+      NEW metal3 ( 103170 102060 ) ( 132050 * )
+      NEW metal3 ( 132050 102060 ) ( 162030 * )
+      NEW metal3 ( 162030 102060 ) ( 178410 * )
       NEW metal1 ( 20330 102060 ) via1_4
       NEW metal2 ( 20330 102060 ) via2_5
       NEW metal1 ( 180310 102060 ) via1_4

diff --git a/src/drt/test/ta_pin_aligned.defok b/src/drt/test/ta_pin_aligned.defok
@@ -119,11 +119,24 @@ PINS 4 ;
 END PINS
 NETS 2 ;
     - Metal2_in ( PIN Metal2_out ) ( PIN Metal2_in ) + USE SIGNAL
-      + ROUTED metal2 ( 97850 19740 0 ) ( * 180180 0 ) ;
+      + ROUTED metal2 ( 97850 19740 0 ) ( * 25060 )
+      NEW metal2 ( 97850 178220 ) ( * 180180 0 )
+      NEW metal2 ( 97850 25060 ) ( * 44100 )
+      NEW metal2 ( 97850 44100 ) ( * 73740 )
+      NEW metal2 ( 97850 73740 ) ( * 103180 )
+      NEW metal2 ( 97850 103180 ) ( * 132300 )
+      NEW metal2 ( 97850 132300 ) ( * 161740 )
+      NEW metal2 ( 97850 161740 ) ( * 178220 ) ;
     - Metal3_in ( PIN Metal3_out ) ( PIN Metal3_in ) + USE SIGNAL
-      + ROUTED metal3 ( 176400 97580 ) ( * 97860 )
+      + ROUTED metal3 ( 19790 97860 0 ) ( 24830 * )
+      NEW metal3 ( 176400 97580 ) ( * 97860 )
       NEW metal3 ( 180510 97580 ) ( * 97860 0 )
+      NEW metal3 ( 24830 97860 ) ( 43890 * )
+      NEW metal3 ( 43890 97860 ) ( 73530 * )
+      NEW metal3 ( 73530 97860 ) ( 103170 * )
+      NEW metal3 ( 103170 97860 ) ( 132050 * )
       NEW metal3 ( 176400 97580 ) ( 180510 * )
-      NEW metal3 ( 19790 97860 0 ) ( 176400 * ) ;
+      NEW metal3 ( 162030 97860 ) ( 176400 * )
+      NEW metal3 ( 132050 97860 ) ( 162030 * ) ;
 END NETS
 END DESIGN
diff --git a/src/drt/test/top_level_term.defok b/src/drt/test/top_level_term.defok
@@ -32,17 +32,24 @@ PINS 1 ;
 END PINS
 NETS 1 ;
     - clk ( PIN clk ) ( clkbuf_0_clk A ) ( clkbuf_2_3__f_clk A ) ( clkbuf_2_2__f_clk A ) ( clkbuf_2_1__f_clk A ) + USE SIGNAL
-      + ROUTED met3 ( 1440 155030 0 ) ( 6960 * )
+      + ROUTED met2 ( 145200 144855 ) ( * 147630 )
+      NEW met3 ( 1440 155030 0 ) ( 6960 * )
       NEW met2 ( 6960 155030 ) ( * 155215 )
-      NEW met1 ( 112080 154845 ) ( * 155215 )
-      NEW met1 ( 127440 158175 ) ( 135600 * )
-      NEW met1 ( 127440 155955 ) ( * 158175 )
-      NEW met1 ( 112080 155955 ) ( 127440 * )
-      NEW met1 ( 112080 155215 ) ( * 155955 )
-      NEW met1 ( 135600 158175 ) ( 144240 * )
+      NEW met1 ( 6960 155215 ) ( 23280 * )
+      NEW met1 ( 100800 154845 ) ( * 155215 )
+      NEW met1 ( 135600 157065 ) ( * 158175 )
+      NEW met1 ( 114480 157065 ) ( 135600 * )
+      NEW met1 ( 114480 156325 ) ( * 157065 )
+      NEW met1 ( 114480 155955 ) ( * 156325 )
+      NEW met1 ( 112080 155955 ) ( 114480 * )
+      NEW met1 ( 112080 154845 ) ( * 155955 )
+      NEW met1 ( 138720 158175 ) ( 144240 * )
+      NEW met1 ( 135600 158175 ) ( 138720 * )
       NEW met1 ( 144240 158175 ) ( 145200 * )
-      NEW met2 ( 145200 144855 ) ( * 158175 )
-      NEW met1 ( 6960 155215 ) ( 112080 * )
+      NEW met2 ( 145200 147630 ) ( * 158175 )
+      NEW met1 ( 100800 154845 ) ( 112080 * )
+      NEW met1 ( 75360 155215 ) ( 100800 * )
+      NEW met1 ( 23280 155215 ) ( 75360 * )
       NEW li1 ( 145200 144855 ) L1M1_PR_MR
       NEW met1 ( 145200 144855 ) M1M2_PR
       NEW met2 ( 6960 155030 ) M2M3_PR

diff --git a/src/drt/test/top_level_term2.defok b/src/drt/test/top_level_term2.defok
@@ -40,29 +40,41 @@ PINS 3 ;
 END PINS
 NETS 1 ;
     - clk ( PIN reg ) ( PIN pin ) ( PIN clk ) ( clkbuf_0_clk A ) ( clkbuf_2_3__f_clk A ) ( clkbuf_2_2__f_clk A ) ( clkbuf_2_1__f_clk A ) + USE SIGNAL
-      + ROUTED met3 ( 1440 155030 0 ) ( 2160 * )
-      NEW met2 ( 2160 155030 ) ( * 155215 )
-      NEW met3 ( 480 148370 ) ( 1440 * 0 )
-      NEW met3 ( 480 148370 ) ( * 149110 )
-      NEW met3 ( 480 149110 ) ( 1440 * )
-      NEW met3 ( 1440 149110 ) ( * 154290 )
+      + ROUTED met3 ( 1440 155030 0 ) ( 6960 * )
+      NEW met2 ( 6960 155030 ) ( * 155215 )
+      NEW met1 ( 6960 155215 ) ( 16560 * )
+      NEW met3 ( 1440 148370 0 ) ( 2400 * )
+      NEW met3 ( 2400 148370 ) ( * 149110 )
+      NEW met3 ( 1440 149110 ) ( 2400 * )
+      NEW met3 ( 1440 149110 ) ( * 151885 )
+      NEW met3 ( 1440 151885 ) ( * 154290 )
       NEW met3 ( 1440 154290 ) ( 2400 * )
       NEW met3 ( 2400 154290 ) ( * 155030 )
-      NEW met3 ( 2160 155030 ) ( 2400 * )
-      NEW met1 ( 112080 154845 ) ( * 155215 )
-      NEW met1 ( 117360 158175 ) ( 135600 * )
-      NEW met1 ( 117360 155955 ) ( * 158175 )
-      NEW met1 ( 112080 155955 ) ( 117360 * )
-      NEW met1 ( 112080 155215 ) ( * 155955 )
+      NEW met1 ( 135600 157065 ) ( * 158175 )
+      NEW met1 ( 116880 157065 ) ( 135600 * )
+      NEW met1 ( 116880 156325 ) ( * 157065 )
+      NEW met1 ( 116640 156325 ) ( 116880 * )
+      NEW met1 ( 116400 156325 ) ( 116640 * )
+      NEW met1 ( 116400 155955 ) ( * 156325 )
+      NEW met1 ( 112080 155955 ) ( 116400 * )
+      NEW met1 ( 112080 154845 ) ( * 155955 )
+      NEW met1 ( 135600 158175 ) ( 136080 * )
       NEW met3 ( 149280 370 0 ) ( 149520 * )
-      NEW met1 ( 2160 155215 ) ( 112080 * )
-      NEW met1 ( 145680 144855 ) ( 149520 * )
+      NEW met2 ( 149520 370 ) ( * 17945 )
+      NEW met1 ( 16560 155215 ) ( 36000 * )
+      NEW met1 ( 36000 154845 ) ( * 155215 )
+      NEW met1 ( 36000 154845 ) ( 112080 * )
+      NEW met2 ( 149520 17945 ) ( * 61050 )
+      NEW met2 ( 149520 61050 ) ( * 111555 )
+      NEW met1 ( 145680 144855 ) ( 147360 * )
+      NEW met1 ( 147360 144855 ) ( 149520 * )
       NEW met2 ( 144720 144855 ) ( * 158175 )
       NEW met1 ( 144720 144855 ) ( 145680 * )
-      NEW met1 ( 135600 158175 ) ( 144720 * )
-      NEW met2 ( 149520 370 ) ( * 144855 )
-      NEW met2 ( 2160 155030 ) M2M3_PR
-      NEW met1 ( 2160 155215 ) M1M2_PR
+      NEW met1 ( 140640 158175 ) ( 144720 * )
+      NEW met1 ( 136080 158175 ) ( 140640 * )
+      NEW met2 ( 149520 111555 ) ( * 144855 )
+      NEW met2 ( 6960 155030 ) M2M3_PR
+      NEW met1 ( 6960 155215 ) M1M2_PR
       NEW li1 ( 112080 154845 ) L1M1_PR_MR
       NEW li1 ( 135600 158175 ) L1M1_PR_MR
       NEW met2 ( 149520 370 ) M2M3_PR