Update HDL core version for Xilinx

Signed-off-by: Travis F. Collins <[email protected]>
analogdevicesinc · Sep 25, 2024 · 72a525a · 72a525a
1 parent 264daef
commit 72a525a
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/adijif/fpgas/xilinx.py b/adijif/fpgas/xilinx.py
@@ -26,7 +26,7 @@ class xilinx(xilinx_bf):
 
     max_serdes_lanes = 24
 
-    hdl_core_version = 1.0
+    hdl_core_version = 2.1
 
     available_speed_grades = [-1, -2, -3]
     speed_grade = -2