Fix remaining lint issues

Signed-off-by: Travis F. Collins <[email protected]>

adijif/cli.py

@@ -13,7 +13,9 @@ def main(args: List[str] = None) -> None:
     Args:
         args (List[str]): List of input argument
     """
-    click.echo("Replace this message by putting your code into " "adijif.cli.main")
+    click.echo(
+        "Replace this message by putting your code into " "adijif.cli.main"
+    )
     click.echo("See click documentation at https://click.palletsprojects.com/")
 
 

adijif/clocks/ad9523.py

@@ -166,7 +166,9 @@ def get_config(self, solution: CpoSolveResult = None) -> Dict:
             Exception: If solver is not called first
         """
         if not self._clk_names:
-            raise Exception("set_requested_clocks must be called before get_config")
+            raise Exception(
+                "set_requested_clocks must be called before get_config"
+            )
         for k in ["out_dividers", "m1", "n2", "r2"]:
             if k not in self.config.keys():
                 raise Exception("Missing key: " + str(k))
@@ -177,11 +179,15 @@ def get_config(self, solution: CpoSolveResult = None) -> Dict:
             "m1": self._get_val(self.config["m1"]),
             "n2": self._get_val(self.config["n2"]),
             "r2": self._get_val(self.config["r2"]),
-            "out_dividers": [self._get_val(x) for x in self.config["out_dividers"]],
+            "out_dividers": [
+                self._get_val(x) for x in self.config["out_dividers"]
+            ],
             "output_clocks": [],
         }
 
-        config["vcxo"] = self._get_val(self.vcxo)  # pytype: disable=attribute-error
+        config["vcxo"] = self._get_val(
+            self.vcxo
+        )  # pytype: disable=attribute-error
         vcxo = config["vcxo"]
 
         clk = vcxo / config["r2"] * config["n2"] / config["m1"]
@@ -196,7 +202,9 @@ def get_config(self, solution: CpoSolveResult = None) -> Dict:
 
         return config
 
-    def _setup_solver_constraints(self, vcxo: Union[float, int, CpoIntVar]) -> None:
+    def _setup_solver_constraints(
+        self, vcxo: Union[float, int, CpoIntVar]
+    ) -> None:
         """Apply constraints to solver model.
 
         Args:
@@ -273,7 +281,11 @@ def _get_clock_constraint(
         od = self._convert_input(self._d, "d_" + str(clk_name))
         self.config["out_dividers"].append(od)
         return (
-            self.vcxo / self.config["r2"] * self.config["n2"] / self.config["m1"] / od
+            self.vcxo
+            / self.config["r2"]
+            * self.config["n2"]
+            / self.config["m1"]
+            / od
         )
 
     def set_requested_clocks(

adijif/clocks/ad9523_1_bf.py

@@ -30,7 +30,8 @@ def list_available_references(self, divider_set):
                     "Input must be of type dict with fields: " + str(ref.keys())
                 )
         return [
-            divider_set["vco"] / divider_set["m1"] / div for div in self.d_available
+            divider_set["vco"] / divider_set["m1"] / div
+            for div in self.d_available
         ]
 
     def find_dividers(self, vcxo, required_output_rates, find=3):

adijif/clocks/ad9528.py

@@ -278,7 +278,9 @@ def get_config(self, solution: CpoSolveResult = None) -> Dict:
             Exception: If solver is not called first
         """
         if not self._clk_names:
-            raise Exception("set_requested_clocks must be called before get_config")
+            raise Exception(
+                "set_requested_clocks must be called before get_config"
+            )
 
         if solution:
             self.solution = solution
@@ -346,9 +348,15 @@ def _setup_solver_constraints(self, vcxo: int) -> None:
         self._add_equation(
             [
                 self.vcxo / self.config["r1"] <= self.pfd_max,
-                self.vcxo / self.config["r1"] * self.config["m1"] * self.config["n2"]
+                self.vcxo
+                / self.config["r1"]
+                * self.config["m1"]
+                * self.config["n2"]
                 <= self.vco_max,
-                self.vcxo / self.config["r1"] * self.config["m1"] * self.config["n2"]
+                self.vcxo
+                / self.config["r1"]
+                * self.config["m1"]
+                * self.config["n2"]
                 >= self.vco_min,
                 4 * self.config["b"] + self.config["a"] >= 16,
                 4 * self.config["b"] + self.config["a"]
@@ -424,14 +432,19 @@ def set_requested_clocks(
             else:
                 sysref_src = self.vcxo / self.config["r1"]
 
-            self._add_equation([sysref_src / (2 * self.config["k"]) == self._sysref])
+            self._add_equation(
+                [sysref_src / (2 * self.config["k"]) == self._sysref]
+            )
 
         # Add requested clocks to output constraints
         for out_freq, name in zip(out_freqs, clk_names):  # noqa: B905
             # od = self.model.Var(integer=True, lb=1, ub=256, value=1)
             od = self._convert_input(self._d, f"d_{name}_{out_freq}")
             # od = self.model.sos1([n*n for n in range(1,9)])
             self._add_equation(
-                [self.vcxo / self.config["r1"] * self.config["n2"] / od == out_freq]
+                [
+                    self.vcxo / self.config["r1"] * self.config["n2"] / od
+                    == out_freq
+                ]
             )
             self.config["out_dividers"].append(od)

adijif/clocks/ad9528_bf.py

@@ -31,7 +31,8 @@ def list_available_references(self, divider_set):
                     "Input must be of type dict with fields: " + str(ref.keys())
                 )
         return [
-            divider_set["vco"] / divider_set["m1"] / div for div in self.d_available
+            divider_set["vco"] / divider_set["m1"] / div
+            for div in self.d_available
         ]
 
     def find_dividers(self, vcxo, required_output_rates, find=3):
@@ -55,8 +56,12 @@ def find_dividers(self, vcxo, required_output_rates, find=3):
                         and vco < self.vco_max
                         and (vco / m1) % mod == 0
                     ):
-                        required_output_divs = (vco / m1) / required_output_rates
-                        if np.all(np.in1d(required_output_divs, self.d_available)):
+                        required_output_divs = (
+                            vco / m1
+                        ) / required_output_rates
+                        if np.all(
+                            np.in1d(required_output_divs, self.d_available)
+                        ):
                             configs.append(
                                 {
                                     "m1": m1,

adijif/clocks/ad9545.py

@@ -171,7 +171,9 @@ def get_config(self, solution: CpoSolveResult = None) -> Dict:
                         self.config[n_dpll_name]
                     )
 
-                    config["PLL" + str(i)][n_name] = self._get_val(self.config[n_name])
+                    config["PLL" + str(i)][n_name] = self._get_val(
+                        self.config[n_name]
+                    )
 
                     config["PLL" + str(i)]["rate_hz"] = self._get_val(
                         self.config["PLL" + str(i) + "_rate"]
@@ -183,7 +185,9 @@ def get_config(self, solution: CpoSolveResult = None) -> Dict:
 
                 if self.PLL_used[i] and dpll_profile_name in self.profiles:
                     if self.profiles[dpll_profile_name]["hitless"]:
-                        source_nr = int(self.profiles[dpll_profile_name]["fb_source"])
+                        source_nr = int(
+                            self.profiles[dpll_profile_name]["fb_source"]
+                        )
 
                         config["PLL" + str(i)]["hitless"] = {
                             "fb_source": source_nr,
@@ -259,11 +263,18 @@ def _setup_solver_constraints(
                     for j in range(0, 4):
                         if input_refs[j] != 0:
                             n_name = "n" + str(i) + "_profile_" + str(j)
-                            n_dpll_name = "n_dpll" + str(i) + "_profile_" + str(j)
-                            m_apll_name = "m_apll" + str(i) + "_profile_" + str(j)
+                            n_dpll_name = (
+                                "n_dpll" + str(i) + "_profile_" + str(j)
+                            )
+                            m_apll_name = (
+                                "m_apll" + str(i) + "_profile_" + str(j)
+                            )
 
                             self.config[n_name] = self.model.Var(
-                                integer=True, lb=self.N_min, ub=self.N_max, name=n_name
+                                integer=True,
+                                lb=self.N_min,
+                                ub=self.N_max,
+                                name=n_name,
                             )
 
                             """ Internally the PLL block is composed of a
@@ -317,8 +328,12 @@ def _setup_solver_constraints(
                     for j in range(0, 4):
                         if input_refs[j] != 0:
                             n_name = "n" + str(i) + "_profile_" + str(j)
-                            n_dpll_name = "n_dpll" + str(i) + "_profile_" + str(j)
-                            m_apll_name = "m_apll" + str(i) + "_profile_" + str(j)
+                            n_dpll_name = (
+                                "n_dpll" + str(i) + "_profile_" + str(j)
+                            )
+                            m_apll_name = (
+                                "m_apll" + str(i) + "_profile_" + str(j)
+                            )
 
                             self.config[n_name] = exp.integer_var(
                                 int(self.N_min), int(self.N_max), n_name
@@ -328,9 +343,13 @@ def _setup_solver_constraints(
                             PLL and an Analog PLL with different constraints on
                             dividers
                             """
-                            DPLL_N = exp.integer_var(int(1), int(350e6), n_dpll_name)
+                            DPLL_N = exp.integer_var(
+                                int(1), int(350e6), n_dpll_name
+                            )
                             self.config[n_dpll_name] = DPLL_N
-                            APLL_M = exp.integer_var(int(7), int(255), m_apll_name)
+                            APLL_M = exp.integer_var(
+                                int(7), int(255), m_apll_name
+                            )
                             self.config[m_apll_name] = APLL_M
 
                             equations = equations + [
@@ -358,7 +377,8 @@ def _setup_solver_constraints(
                     raise Exception("Unknown solver {}".format(self.solver))
 
                 equations = equations + [
-                    self.config["PLL_in_rate_" + str(i)] * self.config["r" + str(i)]
+                    self.config["PLL_in_rate_" + str(i)]
+                    * self.config["r" + str(i)]
                     == self.config["input_ref_" + str(i)]
                 ]
 
@@ -400,18 +420,22 @@ def _setup_solver_constraints(
         if self.avoid_min_max_PLL_rates:
             for i in range(0, 2):
                 if self.PLL_used[i]:
-                    average_PLL_rate = self.PLL_out_min[i] / 2 + self.PLL_out_max[i] / 2
+                    average_PLL_rate = (
+                        self.PLL_out_min[i] / 2 + self.PLL_out_max[i] / 2
+                    )
 
                     if self.solver == "CPLEX":
                         cplex_objectives = cplex_objectives + [
                             mod.abs(
-                                self.config["PLL" + str(i) + "_rate"] - average_PLL_rate
+                                self.config["PLL" + str(i) + "_rate"]
+                                - average_PLL_rate
                             )
                         ]
                     elif self.solver == "gekko":
                         self.model.Minimize(
                             self.model.abs3(
-                                self.config["PLL" + str(i) + "_rate"] - average_PLL_rate
+                                self.config["PLL" + str(i) + "_rate"]
+                                - average_PLL_rate
                             )
                         )
                     else:
@@ -426,7 +450,9 @@ def _setup_solver_constraints(
                             self.config["r" + str(i)]
                         ]
                     elif self.solver == "gekko":
-                        self.model.Maximize(self.config["PLL_in_rate_" + str(i)])
+                        self.model.Maximize(
+                            self.config["PLL_in_rate_" + str(i)]
+                        )
                     else:
                         raise Exception("Unknown solver {}".format(self.solver))
 
@@ -489,8 +515,13 @@ def set_requested_clocks(self, ins: List[int], outs: List[int]) -> None:
             for j in range(0, 4):
                 dpll_profile_name = "dpll_" + str(i) + "_profile_" + str(j)
 
-                if self.PLL_used[i] and self.profiles[dpll_profile_name]["hitless"]:
-                    source_nr = int(self.profiles[dpll_profile_name]["fb_source"])
+                if (
+                    self.PLL_used[i]
+                    and self.profiles[dpll_profile_name]["hitless"]
+                ):
+                    source_nr = int(
+                        self.profiles[dpll_profile_name]["fb_source"]
+                    )
                     n_dpll_name = "n_dpll" + str(i) + "_profile_" + str(j)
 
                     if out_freqs[source_nr] == 0:
@@ -508,7 +539,9 @@ def set_requested_clocks(self, ins: List[int], outs: List[int]) -> None:
                     """ Frequency translation factor:
                     N * input_ref_j == out_rate_x * r_div_j
                     """
-                    self._add_equation([input_ref * pll_n_div == out_rate * r_div])
+                    self._add_equation(
+                        [input_ref * pll_n_div == out_rate * r_div]
+                    )
 
                     """ Hitless mode places a strict constraint on Q dividers """
                     self.config["q" + str(i)]
@@ -524,7 +557,8 @@ def set_requested_clocks(self, ins: List[int], outs: List[int]) -> None:
                 self._add_equation(
                     [
                         self.config["PLL" + str(pll_number) + "_rate"]
-                        == self.config["out_rate_" + str(i)] * self.config["q" + str(i)]
+                        == self.config["out_rate_" + str(i)]
+                        * self.config["q" + str(i)]
                     ]
                 )
 

adijif/clocks/hmc7044.py

@@ -208,7 +208,9 @@ def _init_diagram(self) -> None:
 
         # Connections inside the IC
         # lo.add_connection({"from": ref_in, "to": r2_div, 'rate': 125000000})
-        self.ic_diagram_node.add_connection({"from": vcxo_doubler, "to": r2_div})
+        self.ic_diagram_node.add_connection(
+            {"from": vcxo_doubler, "to": r2_div}
+        )
         self.ic_diagram_node.add_connection(
             {"from": r2_div, "to": pfd, "rate": 125000000 / 2}
         )
@@ -266,7 +268,11 @@ def draw(self) -> str:
         lo.add_node(ref_in)
         vcxo_double = self.ic_diagram_node.get_child("VCXO Doubler")
         lo.add_connection(
-            {"from": ref_in, "to": vcxo_double, "rate": self._saved_solution["vcxo"]}
+            {
+                "from": ref_in,
+                "to": vcxo_double,
+                "rate": self._saved_solution["vcxo"],
+            }
         )
 
         # Update Node values
@@ -279,7 +285,9 @@ def draw(self) -> str:
 
         # Update VCXO Doubler to R2
         # con = self.ic_diagram_node.get_connection("VCXO Doubler", "R2")
-        rate = self._saved_solution["vcxo_doubler"] * self._saved_solution["vcxo"]
+        rate = (
+            self._saved_solution["vcxo_doubler"] * self._saved_solution["vcxo"]
+        )
         self.ic_diagram_node.update_connection("VCXO Doubler", "R2", rate)
 
         # Update R2 to PFD
@@ -308,7 +316,9 @@ def draw(self) -> str:
             div.value = str(div_value)
             d += 1
             lo.add_node(clk_node)
-            lo.add_connection({"from": div, "to": clk_node, "rate": val["rate"]})
+            lo.add_connection(
+                {"from": div, "to": clk_node, "rate": val["rate"]}
+            )
 
         return lo.draw()
 
@@ -328,7 +338,9 @@ def get_config(self, solution: CpoSolveResult = None) -> Dict:
             Exception: If solver is not called first
         """
         if not self._clk_names:
-            raise Exception("set_requested_clocks must be called before get_config")
+            raise Exception(
+                "set_requested_clocks must be called before get_config"
+            )
 
         if solution:
             self.solution = solution
@@ -375,7 +387,9 @@ def _setup_solver_constraints(self, vcxo: int) -> None:
         self.vcxo = vcxo
 
         if self.solver == "gekko":
-            self.config = {"r2": self.model.Var(integer=True, lb=1, ub=4095, value=1)}
+            self.config = {
+                "r2": self.model.Var(integer=True, lb=1, ub=4095, value=1)
+            }
             self.config["n2"] = self.model.Var(integer=True, lb=8, ub=4095)
             if isinstance(vcxo, (int, float)):
                 vcxo_var = self.model.Const(int(vcxo))
@@ -456,7 +470,9 @@ def _get_clock_constraint(
             __d = self._d if isinstance(self._d, list) else [self._d]
 
             if __d.sort() != self.d_available.sort():
-                raise Exception("For solver gekko d is not configurable for HMC7044")
+                raise Exception(
+                    "For solver gekko d is not configurable for HMC7044"
+                )
 
             even = self.model.Var(integer=True, lb=3, ub=2047)
             odd = self.model.Intermediate(even * 2)