core: fix compatability with Pokemon Pinball

- Add support for 0x1E cart type (MBC5)
- Fix MBC5 out of range ram access, now ignore / return 0xFF instead of crashing
- Fix PPU mode when the PPU is disabled (was the last mode, now its HBLANK)

core/src/machine/mbc_initializer.rs

@@ -28,7 +28,8 @@ pub fn initialize_mbc(program:&[u8], save_data:Option<&[u8]>)->&'static mut dyn
         0x12 => static_alloc(Mbc3::new(program_clone,false,None)),
         0x19 | 
         0x1A => static_alloc(Mbc5::new(program_clone, false, save_data_clone)),
-        0x1B => static_alloc(Mbc5::new(program_clone, true, save_data_clone)),
+        0x1B |
+        0x1E => static_alloc(Mbc5::new(program_clone, true, save_data_clone)),
         _=> core::panic!("not supported cartridge: {:#X}",mbc_type)
     };
 

core/src/mmu/carts/mbc5.rs

@@ -46,7 +46,7 @@ impl<'a> Mbc for Mbc5<'a> {
     fn read_external_ram(&self, address:u16)->u8 {
         if self.ram_enable_register == ENABLE_RAM_VALUE{
             let bank = (self.ram_bank_number & 0xF) as usize * RAM_BANK_SIZE;
-            return self.ram[address as usize + bank];
+            return *self.ram.get(address as usize + bank).unwrap_or(&0xFF);
         }
 
         // ram is disabled
@@ -56,7 +56,9 @@ impl<'a> Mbc for Mbc5<'a> {
     fn write_external_ram(&mut self, address:u16, value:u8) {
         if self.ram_enable_register == ENABLE_RAM_VALUE{
             let bank = (self.ram_bank_number & 0xF) as usize * RAM_BANK_SIZE;
-            self.ram[address as usize + bank] = value;
+            if let Some(memory_cell) = self.ram.get_mut(address as usize + bank){
+                *memory_cell = value;
+            }
         }
         else{
             log::warn!("MBC5 write while ram is not enabled. ram_address: {}, value: {}", address, value);

core/src/ppu/gb_ppu.rs

@@ -117,6 +117,7 @@ impl<GFX:GfxDevice> GbPpu<GFX>{
         unsafe{core::ptr::write_bytes(self.screen_buffers[self.current_screen_buffer_index].as_mut_ptr(), 0xFF, SCREEN_HEIGHT * SCREEN_WIDTH)};
         self.swap_buffer();
         self.state = PpuState::Hblank;
+        self.update_stat_ppu_mode();
         self.ly_register = 0;
         self.stat_triggered = false;
         self.trigger_stat_interrupt = false;
@@ -158,8 +159,7 @@ impl<GFX:GfxDevice> GbPpu<GFX>{
     }
 
     fn update_stat_register(&mut self, if_register: &mut u8) -> u32{
-        self.stat_register &= 0b1111_1100;
-        self.stat_register |= self.state as u8;
+        self.update_stat_ppu_mode();
         if self.ly_register == self.lyc_register{
             if self.coincidence_interrupt_request {
                 self.trigger_stat_interrupt = true;
@@ -193,6 +193,11 @@ impl<GFX:GfxDevice> GbPpu<GFX>{
         return t_cycles_to_next_stat_change;
     }
 
+    fn update_stat_ppu_mode(&mut self) {
+        self.stat_register &= 0b1111_1100;
+        self.stat_register |= self.state as u8;
+    }
+
     fn cycle_fetcher(&mut self, m_cycles:u32, if_register:&mut u8)->u16{
         let mut m_cycles_counter = 0;