0.13

What's Changed

• Add PLL pads. by @yrabbit in #241
• Doc. Brief notes on DSP operation by @yrabbit in #246
• Fix CI by @yrabbit in #248
• BUGFIX. Fix BSRAM unpacking. by @yrabbit in #247
• Add description of BSRAM harness by @yrabbit in #249
• Fix IO unpack by @yrabbit in #250
• Describe the BSRAM regs in GW1NR-9C and GW2AR-18C by @yrabbit in #251
• BSRAM. Corrective action. by @yrabbit in #252
• BSRAM BLKSEL fix by @yrabbit in #254
• Clarification in the doc about BSRAM BLKSEL by @yrabbit in #255
• Relax BSRAM initialization data requirements by @yrabbit in #253
• Fix regex by @max-kudinov in #259
• Fix pROM(X9). by @yrabbit in #256
• Implement power saving primitive BANDGAP by @yrabbit in #257
• Fix bits to bytes conversion. by @yrabbit in #265
• Add wire class info by @yrabbit in #266
• Add dynamic clock control by @yrabbit in #260
• HCLK Support by @Seyviour in #258
• HCLK. Primary clock pins by @yrabbit in #263
• Add delays for primary clocks. by @yrabbit in #270

New Contributors

• @max-kudinov made their first contribution in #259

Full Changelog: 0.12...0.13