[RN50] Update configs for ResNet to implement last MVAU as rtl component

Xilinx · Jul 22, 2024 · fcb25ce · fcb25ce
1 parent b4854da
commit fcb25ce
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Showing 3 changed files with 11 additions and 12 deletions.
diff --git a/build/get-finn.sh b/build/get-finn.sh
@@ -31,7 +31,7 @@
 # URL for git repo to be cloned
 REPO_URL=https://github.com/Xilinx/finn
 # commit hash for repo
-REPO_COMMIT=9cd8bab4d5ebd6895716fad41753256542cc314f
+REPO_COMMIT=274785308d563cf2c8d899023b3b098cf430f4bf
 # directory (under the same folder as this script) to clone to
 REPO_DIR=finn
 

diff --git a/build/resnet50/folding_config/U250_folding_config.json b/build/resnet50/folding_config/U250_folding_config.json
@@ -56,7 +56,7 @@
   "MVAU_hls_0": {
     "PE": 64,
     "SIMD": 3,
-    "ram_style": "auto",
+    "ram_style": "distributed",
     "resType": "lut",
     "mem_mode": "internal_decoupled",
     "runtime_writeable_weights": 0,
@@ -68,7 +68,7 @@
     ]
   },
   "StreamingFIFO_rtl_3": {
-    "ram_style": "auto",
+    "ram_style": "distributed",
     "depth": 2,
     "impl_style": "rtl",
     "inFIFODepths": [
@@ -251,7 +251,7 @@
   "MVAU_hls_1": {
     "PE": 1,
     "SIMD": 16,
-    "ram_style": "auto",
+    "ram_style": "distributed",
     "resType": "lut",
     "mem_mode": "internal_decoupled",
     "runtime_writeable_weights": 0,
@@ -265,7 +265,7 @@
   "MVAU_hls_2": {
     "PE": 2,
     "SIMD": 32,
-    "ram_style": "auto",
+    "ram_style": "distributed",
     "resType": "lut",
     "mem_mode": "internal_decoupled",
     "runtime_writeable_weights": 0,
@@ -349,7 +349,7 @@
     ]
   },
   "StreamingFIFO_rtl_17": {
-    "ram_style": "auto",
+    "ram_style": "distributed",
     "depth": 2,
     "impl_style": "rtl",
     "inFIFODepths": [
@@ -381,7 +381,7 @@
   "MVAU_hls_3": {
     "PE": 2,
     "SIMD": 64,
-    "ram_style": "auto",
+    "ram_style": "distributed",
     "resType": "lut",
     "mem_mode": "internal_decoupled",
     "runtime_writeable_weights": 0,
@@ -5499,12 +5499,11 @@
       0
     ]
   },
-  "MVAU_hls_53": {
+  "MVAU_rtl_0": {
     "PE": 1,
     "SIMD": 4,
-    "ram_style": "auto",
-    "resType": "lut",
-    "mem_mode": "external",
+    "ram_style": "block",
+    "resType": "dsp",
     "runtime_writeable_weights": 0,
     "inFIFODepths": [
       2

diff --git a/build/resnet50/specialize_layers_config/U250_specialize_layers.json b/build/resnet50/specialize_layers_config/U250_specialize_layers.json
@@ -517,7 +517,7 @@
     "preferred_impl_style": "hls"
   },
   "MVAU_53": {
-    "preferred_impl_style": "hls"
+    "preferred_impl_style": "rtl"
   },
   "ChannelwiseOp_2": {
     "preferred_impl_style": "hls"