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feat: bump MAX_AXI_BRAM_ADDR_WIDTH
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Blaok committed Feb 18, 2024
1 parent e49a22f commit 93646a9
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Showing 2 changed files with 2 additions and 2 deletions.
2 changes: 1 addition & 1 deletion tapa_fast_cosim/common.py
Original file line number Diff line number Diff line change
Expand Up @@ -4,4 +4,4 @@ def __init__(self, name, data_width, addr_width):
self.data_width = data_width
self.addr_width = addr_width

MAX_AXI_BRAM_ADDR_WIDTH = 20
MAX_AXI_BRAM_ADDR_WIDTH = 24
2 changes: 1 addition & 1 deletion tapa_fast_cosim/templates.py
Original file line number Diff line number Diff line change
Expand Up @@ -364,7 +364,7 @@ def get_end():

def get_axi_ram_module(axi: AXI, input_data_path: str, c_array_size: int):
if axi.data_width / 8 * c_array_size > 2**MAX_AXI_BRAM_ADDR_WIDTH:
_logger.error('The current cosim data size is larger than the recommended threashold (1 MB per DDR/HBM). '
_logger.error('The current cosim data size is larger than the recommended threashold (16 MB per DDR/HBM). '
'Option 1: reduce cosim data size. '
'Option 2: increase the MAX_AXI_BRAM_ADDR_WIDTH constant in tapa_fast_cosim/common.py. '
'To do that, clone the https://github.com/UCLA-VAST/tapa-fast-cosim.git repo and '
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