This project involves the design of a central processing unit (CPU) capable of moving, loading, and manipulating data. The CPU features 8 registers and an instruction code format represented as OOXXXYYY. The first two bits denote operations, while the remaining bits specify operands. For the move immediate operation, the entire code is considered a value in the second clock cycle.
- First Clock Cycle: Instruction Register (IR) is loaded with DIN when the IRin signal is high.
- Second Clock Cycle: Ryout flag selects the source register, and Rxin flag enables the destination register to move the data.
- First Clock Cycle: IR is loaded with DIN when IRin is high.
- Second Clock Cycle: MUX selects DIN, and Rxin enables the desired register to receive the immediate value.
- First Clock Cycle: IR is loaded with DIN when IRin is high.
- Second Clock Cycle: Rx data is loaded into temporary register A.
- Third Clock Cycle: Ry register's data is loaded onto the bus.
- Fourth Clock Cycle: ALU performs addition or subtraction based on the Asen flag, storing the result in register B.
- Fifth Clock Cycle: Rxin enables the destination register to store the result from register B.
The 1-bit ALU designed in previous labs is utilized to create an 8-bit ALU. This ALU is capable of performing addition and subtraction, with complementary operations represented in a truth table.
Figure 2: illustrating 1-bit ALU.
- The control circuit uses Boolean expressions derived from the truth table.
- The clock starts in the IR state, and clear signals are added for the first two instructions.
- A 2-bit counter resets at the 4th clock cycle.
- MUX Selection: Rxout as a select signal in the 2x1 MUX determines which register's data appears on the bus.
- Enable Signals: Rxin enables the decoder to decide which register receives data.
- An 8x1 MUX determines the selected register.
- Two 2x1 MUXes select between B and DIN inputs.
A custom "decimal" circuit with three ROMs is built to read register contents easily. This circuit decodes 8-bit numbers (from -128 to 127) into corresponding most significant, middle, and least significant bits, with a sign output indicating the number's sign.
- Components: 2-bit counter, A and B temporary registers, 8 memory registers, and an IR register for storing instructions.
- ROM for Instructions: An OR gate manages inputs to facilitate faster instruction loading, synchronized with clock cycles.
The CPU design demonstrates the functionality through a series of instructions to show the 1's complement of the value in register Rb in register Ra.
Figure 2: illustrating sub operation the architecture of the CPU.
- Load immediate values into registers.
- Move values between registers.
- Perform subtraction operations.
The functionality is implemented with 6 instructions:
- 2 move immediate instructions (4 clock cycles)
- 1 move instruction (2 clock cycles)
- 3 subtraction instructions (12 clock cycles)
A total of 18 clock cycles are used to achieve the desired functionality.
To use this CPU design, follow these steps:
- Load the provided instructions into the ROM.
- Set the appropriate clock signals to initiate the operations.
- Monitor the registers and ALU operations as described in the data path.
The CPU supports a set of instructions as listed below:
| OP code | Operation and Operands | Executed Function |
|---|---|---|
| 00 | mv Rx, Ry | Rx ← [Ry] |
| 01 | mvi Rx, D | Rx ← D |
| 10 | add Rx, Ry | Rx ← [Rx] + [Ry] |
| 11 | sub Rx, Ry | Rx ← [Rx] - [Ry] |
Contributions to this project are welcome. Please fork the repository, make your changes, and submit a pull request. Ensure that your code adheres to the project's coding standards and includes appropriate documentation.