tja

BG/doc/build.log

@@ -1,3 +0,0 @@
-
-Sphinx error:
-Builder name docs not registered or available through entry point

BG/doc/build/html/.buildinfo

@@ -1,4 +1,4 @@
 # Sphinx build info version 1
 # This file records the configuration used when building these files. When it is not found, a full rebuild will be done.
-config: de256c898c0cfb6c782320ef8a3a4c31
+config: f8f37a3807f279bfd416ee3cd6bbff8c
 tags: 645f666f9bcd5a90fca523b33c5a78b7

BG/doc/build/html/_sources/designdata.rst.txt

@@ -17,7 +17,7 @@ open-source runs:
 https://www.ihp-microelectronics.com/services/research-and-prototyping-service/fast-design-enablement/open-source-pdk
 
 Xschem schematics:
-#######
+###############################
 
 .. list-table:: 
    :header-rows: 1
@@ -35,7 +35,7 @@ Xschem schematics:
      - symbols for Xschem schematics
 
 KLayout .GDS:
-#######
+###############################
 
 .. list-table:: 
    :header-rows: 1

BG/doc/build/html/_sources/detectors.rst.txt

@@ -12,4 +12,5 @@ layout
 .. image:: _static/detectors.png
     :align: center
 
+\
 

BG/doc/build/html/_sources/index.rst.txt

@@ -3,10 +3,17 @@
 CMOS only BiCMOS chip ;)
 ************************
 
+.. warning::
+    this chip is mostly done using an unfinished PDK. LVS was done only for parts.
+
+.. image:: _static/CMOS_chip.png
+    :align: center
+
+\
 
 .. toctree::
-    :hidden:
-    
+    :hidden: 
+
     specification
     ota
     reference
@@ -17,14 +24,10 @@ CMOS only BiCMOS chip ;)
     designdata
     validation
 
-.. warning::
-    this chip is mostly done using an unfinished PDK. LVS was done only for parts.
-
-.. image:: _static/CMOS_chip.png
-    :align: center
-
-\
+.. only:: latex
 
+    .. contents:: Table of Contents
+
 background
 **********
 

BG/doc/build/html/_sources/ota.rst.txt

@@ -14,14 +14,28 @@ in the space the circuit uses are 3 MiM-capacitors placed. they are intended to
 OTA 
 ###
 
-.. image:: _static/OTA3C.svg
-    :align: center
+.. only:: html
+
+    .. image:: _static/OTA3C.svg
+        :align: center
+
+.. only:: latex
+
+    .. image:: _static/OTA3C.eps
+        :align: center
 
 bias generator
-############
+########################
 
-.. image:: _static/OTA33_BiAS.svg
-    :align: center
+.. only:: html
+
+    .. image:: _static/OTA33_BiAS.svg
+        :align: center
+
+.. only:: latex
+
+    .. image:: _static/OTA33_BiAS.eps
+        :align: center
 
 layout
 ######

BG/doc/build/html/_sources/reference.rst.txt

@@ -8,8 +8,15 @@ the shunt-regulator has to limit the supply-voltage to 3.3V. it should be usable
 schematic
 #########
 
-.. image:: _static/bg.svg
-    :align: center
+.. only:: html
+
+    .. image:: _static/bg.svg
+        :align: center
+
+.. only:: latex
+
+    .. image:: _static/bg.eps
+        :align: center
 
 layout
 ######

BG/doc/build/html/_sources/regulators.rst.txt

@@ -17,8 +17,15 @@ the serial regulator should produce 1.8V for low-voltage MOSFETs. the OTA respon
 schematic
 #########
 
-.. image:: _static/regs.svg
-    :align: center
+.. only:: html
+
+    .. image:: _static/regs.svg
+        :align: center
+
+.. only:: latex
+
+    .. image:: _static/regs.eps
+        :align: center
 
 layout
 ######

BG/doc/build/html/_sources/specification.rst.txt

@@ -32,8 +32,15 @@ this is a chip to test the following circuits:
 pinout
 ########################
 
-.. image:: _static/pinout.svg
-    :align: center
+.. only:: html
+
+    .. image:: _static/pinout.svg
+        :align: center
+
+.. only:: latex
+
+    .. image:: _static/pinout.eps
+        :align: center
 
 signals
 ########################

BG/doc/build/html/_sources/validation.rst.txt

@@ -1,5 +1,5 @@
 validation sometime in the farfar future
-#################################
+#############################################
 
 
 i cant wait...

BG/doc/build/html/detectors.html

@@ -87,6 +87,7 @@ <h1>mmW diode detectors<a class="headerlink" href="#mmw-diode-detectors" title="
 <section id="layout">
 <h2>layout<a class="headerlink" href="#layout" title="Link to this heading"></a></h2>
 <img alt="_images/detectors.png" class="align-center" src="_images/detectors.png" />
+<p></p>
 </section>
 </section>
 

BG/doc/build/html/index.html

@@ -78,22 +78,22 @@
            <div itemprop="articleBody">
 
   <section id="cmos-only-bicmos-chip">
-<h1>CMOS only BiCMOS chip ;)<a class="headerlink" href="#cmos-only-bicmos-chip" title="Link to this heading"></a></h1>
-<div class="toctree-wrapper compound">
-</div>
+<h1><a class="toc-backref" href="#id1" role="doc-backlink">CMOS only BiCMOS chip ;)</a><a class="headerlink" href="#cmos-only-bicmos-chip" title="Link to this heading"></a></h1>
 <div class="admonition warning">
 <p class="admonition-title">Warning</p>
 <p>this chip is mostly done using an unfinished PDK. LVS was done only for parts.</p>
 </div>
 <img alt="_images/CMOS_chip.png" class="align-center" src="_images/CMOS_chip.png" />
 <p></p>
+<div class="toctree-wrapper compound">
+</div>
 <section id="background">
-<h2>background<a class="headerlink" href="#background" title="Link to this heading"></a></h2>
+<h2><a class="toc-backref" href="#id2" role="doc-backlink">background</a><a class="headerlink" href="#background" title="Link to this heading"></a></h2>
 <p>to make first steps using iHPs openPDK, Xschem and KLayout designing a OTA was obvious. this part is DRC and LVS clean, verified also using commercial tools.</p>
 <p>but that’s also the only clean part on this chip from my perspective. its highly likely that the IO cells are perfect, but i couldn’t verify this my self. the opensource LVS didn’t was ready, and i hadn’t the time to verify any other part then the OTA via LVS.</p>
 </section>
 <section id="the-sg13g2-process">
-<h2>the sg13g2 process<a class="headerlink" href="#the-sg13g2-process" title="Link to this heading"></a></h2>
+<h2><a class="toc-backref" href="#id3" role="doc-backlink">the sg13g2 process</a><a class="headerlink" href="#the-sg13g2-process" title="Link to this heading"></a></h2>
 <p>there are two kinds of GateOxyde: thick for high-voltage like 3.3V circuits and standard for 1.2..1.8V circuits. there are three different SiGe BjTs, but all are NPNs. while the Si-parasitic transistors are only PNP.</p>
 </section>
 </section>

BG/doc/build/latex/LICRcyr2utf8.xdy

@@ -0,0 +1,101 @@
+;; -*- coding: utf-8; mode: Lisp; -*-
+;; style file for xindy
+;; filename: LICRcyr2utf8.xdy
+;; description: style file for xindy which maps back LaTeX Internal
+;;   Character Representation of Cyrillic to utf-8
+;; usage: for use with pdflatex produced .idx files.
+;; Contributed by the Sphinx team, July 2018.
+(merge-rule "\IeC {\'\CYRG }" "Ѓ" :string)
+(merge-rule "\IeC {\'\CYRK }" "Ќ" :string)
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+(merge-rule "\IeC {\CYRC }" "Ц" :string)
+(merge-rule "\IeC {\CYRCH }" "Ч" :string)
+(merge-rule "\IeC {\CYRD }" "Д" :string)
+(merge-rule "\IeC {\CYRDJE }" "Ђ" :string)
+(merge-rule "\IeC {\CYRDZE }" "Ѕ" :string)
+(merge-rule "\IeC {\CYRDZHE }" "Џ" :string)
+(merge-rule "\IeC {\CYRE }" "Е" :string)
+(merge-rule "\IeC {\CYREREV }" "Э" :string)
+(merge-rule "\IeC {\CYRERY }" "Ы" :string)
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+(merge-rule "\IeC {\CYRHRDSN }" "Ъ" :string)
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