Change circuit translation to tuple the state instead of adding it to a record type#2022

Merged

mergify[bot] merged 9 commits intomasterfrom yosys/tuple-trans-types

Feb 1, 2024

+1,969-92

Commits on Jan 26, 2024

changed the yosys compositional translation to use a pair type to combine the state type with the inputand output types of a circuit model, rather than a record type with a field named __state__
Eddy Westbrook
committed

Commits on Jan 31, 2024

whoops, forgot to project out the submodule state when calling the translation of a submodule
Eddy Westbrook
committed

Commits on Feb 1, 2024

added explicit SAW core type-checking at the end of translateModule to double-check that things are honky-dory whenever we translate a module (because it turns out things were not!)
Eddy Westbrook
committed
fixed a subtle bug in how the record fields are ordered by the compositional yosys translation
Eddy Westbrook
committed
added a test case for using prove_bisim on a compositional circuit
Eddy Westbrook
committed
Merge branch 'master' into yosys/tuple-trans-types
Eddy Westbrook
committed
Update intTests/test_comp_bisim/test.sh

Eddy Westbrook
and
RyanGlScott
authored
Update intTests/test_comp_bisim/feedback.saw

Eddy Westbrook
and
RyanGlScott
authored
removed unnecessary import
Eddy Westbrook
committed