i#3037: Add support for inclusive caches in DRCacheSim. (#3036)

Add support for inclusive caches and cache line invalidation in DRCacheSim. No support for setting the "inclusive" field and the "children" vector are included in this commit because a new configuration file-based interface to the simulator is being added in a subsequent commit. Tests for inclusive caches will be added in the subsequent commit. Fixes #3037
DynamoRIO · Jun 1, 2018 · 5312f66 · 5312f66
1 parent 90ef0b9
commit 5312f66
Show file tree

Hide file tree

Showing 33 changed files with 154 additions and 12 deletions.
diff --git a/clients/drcachesim/simulator/cache.cpp b/clients/drcachesim/simulator/cache.cpp
@@ -37,13 +37,15 @@
 bool
 cache_t::init(int associativity_, int line_size_, int total_size,
               caching_device_t *parent_, caching_device_stats_t *stats_,
-              prefetcher_t *prefetcher_)
+              prefetcher_t *prefetcher_, bool inclusive_,
+              const std::vector<caching_device_t*>& children_)
 {
     // convert total_size to num_blocks to fit for caching_device_t::init
     int num_lines = total_size / line_size_;
 
     return caching_device_t::init(associativity_, line_size_, num_lines,
-                                  parent_, stats_, prefetcher_);
+                                  parent_, stats_, prefetcher_, inclusive_,
+                                  children_);
 }
 
 void

diff --git a/clients/drcachesim/simulator/cache.h b/clients/drcachesim/simulator/cache.h
@@ -47,7 +47,9 @@ class cache_t : public caching_device_t
     // to describe a CPU cache.
     virtual bool init(int associativity, int line_size, int total_size,
                       caching_device_t *parent, caching_device_stats_t *stats,
-                      prefetcher_t *prefetcher = nullptr);
+                      prefetcher_t *prefetcher = nullptr,
+                      bool inclusive = false,
+                      const std::vector<caching_device_t*>& children = {});
     virtual void request(const memref_t &memref);
     virtual void flush(const memref_t &memref);
  protected:

diff --git a/clients/drcachesim/simulator/cache_fifo.cpp b/clients/drcachesim/simulator/cache_fifo.cpp
@@ -41,13 +41,15 @@
 bool
 cache_fifo_t::init(int associativity_, int block_size_, int total_size,
                    caching_device_t *parent_, caching_device_stats_t *stats_,
-                   prefetcher_t *prefetcher_)
+                   prefetcher_t *prefetcher_, bool inclusive_,
+                   const std::vector<caching_device_t*>& children_)
 {
     // Works in the same way as the base class,
     // except that the counters are initialized in a different way.
 
     bool ret_val = cache_t::init(associativity_, block_size_, total_size,
-                                 parent_, stats_, prefetcher_);
+                                 parent_, stats_, prefetcher_, inclusive_,
+                                 children_);
     if (ret_val == false)
         return false;
 

diff --git a/clients/drcachesim/simulator/cache_fifo.h b/clients/drcachesim/simulator/cache_fifo.h
@@ -43,7 +43,8 @@ class cache_fifo_t : public cache_t
  public:
     virtual bool init(int associativity, int line_size, int total_size,
                       caching_device_t *parent, caching_device_stats_t *stats,
-                      prefetcher_t *prefetcher);
+                      prefetcher_t *prefetcher, bool inclusive = false,
+                      const std::vector<caching_device_t*>& children = {});
 
  protected:
     virtual void access_update(int line_idx, int way);

diff --git a/clients/drcachesim/simulator/caching_device.cpp b/clients/drcachesim/simulator/caching_device.cpp
@@ -55,7 +55,8 @@ caching_device_t::~caching_device_t()
 bool
 caching_device_t::init(int associativity_, int block_size_, int num_blocks_,
                        caching_device_t *parent_, caching_device_stats_t *stats_,
-                       prefetcher_t *prefetcher_)
+                       prefetcher_t *prefetcher_, bool inclusive_,
+                       const std::vector<caching_device_t*>& children_)
 {
     if (!IS_POWER_OF_2(associativity_) ||
         !IS_POWER_OF_2(block_size_) ||
@@ -85,6 +86,10 @@ caching_device_t::init(int associativity_, int block_size_, int num_blocks_,
     init_blocks();
 
     last_tag = TAG_INVALID; // sentinel
+
+    inclusive = inclusive_;
+    children = children_;
+
     return true;
 }
 
@@ -147,6 +152,11 @@ caching_device_t::request(const memref_t &memref_in)
             // the block loaded count.
             if (get_caching_device_block(block_idx, way).tag == TAG_INVALID) {
                 loaded_blocks++;
+            } else if (inclusive && !children.empty()) {
+                for (auto &child : children) {
+                    child->invalidate(
+                        get_caching_device_block(block_idx, way).tag);
+                }
             }
             get_caching_device_block(block_idx, way).tag = tag;
         }
@@ -200,3 +210,25 @@ caching_device_t::replace_which_way(int block_idx)
     get_caching_device_block(block_idx, min_way).counter = 0;
     return min_way;
 }
+
+void
+caching_device_t::invalidate(const addr_t tag)
+{
+    int block_idx = compute_block_idx(tag);
+
+    for (int way = 0; way < associativity; ++way) {
+        auto &cache_block = get_caching_device_block(block_idx, way);
+        if (cache_block.tag == tag) {
+            cache_block.tag = TAG_INVALID;
+            cache_block.counter = 0;
+            stats->invalidate();
+            // Invalidate the block in the children's caches.
+            if (inclusive && !children.empty()) {
+                for (auto &child : children) {
+                    child->invalidate(tag);
+                }
+            }
+            break;
+        }
+    }
+}
diff --git a/clients/drcachesim/simulator/caching_device.h b/clients/drcachesim/simulator/caching_device.h
@@ -36,6 +36,8 @@
 #ifndef _CACHING_DEVICE_H_
 #define _CACHING_DEVICE_H_ 1
 
+#include <vector>
+
 #include "caching_device_block.h"
 #include "caching_device_stats.h"
 #include "memref.h"
@@ -55,9 +57,12 @@ class caching_device_t
     caching_device_t();
     virtual bool init(int associativity, int block_size, int num_blocks,
                       caching_device_t *parent, caching_device_stats_t *stats,
-                      prefetcher_t *prefetcher = nullptr);
+                      prefetcher_t *prefetcher = nullptr,
+                      bool inclusive = false,
+                      const std::vector<caching_device_t*>& children = {});
     virtual ~caching_device_t();
     virtual void request(const memref_t &memref);
+    virtual void invalidate(const addr_t tag);
 
     caching_device_stats_t *get_stats() const { return stats; }
     void set_stats(caching_device_stats_t *stats_) { stats = stats_; }
@@ -86,7 +91,14 @@ class caching_device_t
     int num_blocks;
     // Current valid blocks in the cache
     int loaded_blocks;
+
+    // Pointers to the caching device's parent and children devices.
     caching_device_t *parent;
+    std::vector<caching_device_t*> children;
+
+    // If true, this device is inclusive of its children.
+    bool inclusive;
+
     // This should be an array of caching_device_block_t pointers, otherwise
     // an extended block class which has its own member variables cannot be indexed
     // correctly by base class pointers.

diff --git a/clients/drcachesim/simulator/caching_device_stats.cpp b/clients/drcachesim/simulator/caching_device_stats.cpp
@@ -38,8 +38,8 @@
 caching_device_stats_t::caching_device_stats_t(const std::string &miss_file,
                                                bool warmup_enabled) :
     success(true), num_hits(0), num_misses(0), num_child_hits(0),
-    num_hits_at_reset(0), num_misses_at_reset(0), num_child_hits_at_reset(0),
-    warmup_enabled(warmup_enabled), file(nullptr)
+    num_inclusive_invalidates(0), num_hits_at_reset(0), num_misses_at_reset(0),
+    num_child_hits_at_reset(0), warmup_enabled(warmup_enabled), file(nullptr)
 {
     if (miss_file.empty()) {
         dump_misses = false;
@@ -126,6 +126,8 @@ caching_device_stats_t::print_counts(std::string prefix)
         std::setw(20) << std::right << num_hits << std::endl;
     std::cerr << prefix << std::setw(18) << std::left << "Misses:" <<
         std::setw(20) << std::right << num_misses << std::endl;
+    std::cerr << prefix << std::setw(18) << std::left << "Invalidations:" <<
+        std::setw(20) << std::right << num_inclusive_invalidates << std::endl;
 }
 
 void
@@ -176,4 +178,11 @@ caching_device_stats_t::reset()
     num_hits = 0;
     num_misses = 0;
     num_child_hits = 0;
+    num_inclusive_invalidates = 0;
+}
+
+void
+caching_device_stats_t::invalidate()
+{
+    num_inclusive_invalidates++;
 }
diff --git a/clients/drcachesim/simulator/caching_device_stats.h b/clients/drcachesim/simulator/caching_device_stats.h
@@ -64,6 +64,9 @@ class caching_device_stats_t
 
     virtual bool operator!() { return !success; }
 
+    // Process invalidations due to cache inclusions.
+    virtual void invalidate();
+
  protected:
     bool success;
 
@@ -79,6 +82,8 @@ class caching_device_stats_t
     int_least64_t num_misses;
     int_least64_t num_child_hits;
 
+    int_least64_t num_inclusive_invalidates;
+
     // Stats saved when the last reset was called. This helps us get insight
     // into what the stats were when the cache was warmed up.
     int_least64_t num_hits_at_reset;

diff --git a/clients/drcachesim/tests/TLB-simple.templatex b/clients/drcachesim/tests/TLB-simple.templatex
@@ -5,14 +5,17 @@ Core #0 \(1 thread\(s\)\)
   L1I stats:
     Hits:                      *[0-9,\.]*
     Misses:                    *[0-9,\.]*
+    Invalidations:             *0
     Miss rate:                        0[,\.]..%
   L1D stats:
     Hits:                      *[0-9,\.]*
     Misses:                    *[0-9,\.]*
+    Invalidations:             *0
     Miss rate:                 *[0-9]*[,\.]..%
   LL stats:
     Hits:                      *[0-9,\.]*
     Misses:                           *[0-9]..?
+    Invalidations:             *0
     Local miss rate:           *[0-9]*[,\.]..%
     Child hits:                *[0-9,\.]*
     Total miss rate:                  0[,\.]..%

diff --git a/clients/drcachesim/tests/TLB-threads.templatex b/clients/drcachesim/tests/TLB-threads.templatex
@@ -69,14 +69,17 @@ Core #0 \([0-9] traced CPU\(s\): [#0-9, ]+\)
   L1I stats:
     Hits:                    *[0-9]*[,\.]?...[,\.]?...
     Misses:                  *[0-9,\.]*
+    Invalidations:           *0
     Miss rate:                        [0-4][\.,]..%
   L1D stats:
     Hits:                      *[0-9,\.]*
     Misses:                    *[0-9,\.]*
+    Invalidations:             *0
     Miss rate:                 *[0-9]*[\.,]..%
   LL stats:
     Hits:                      *[0-9,\.]*
     Misses:                    *[0-9,\.]*
+    Invalidations:             *0
     Local miss rate:           *[0-9]*[\.,]..%
     Child hits:                *[0-9,\.]*
     Total miss rate:                  [0-4][\.,]..%

diff --git a/clients/drcachesim/tests/allasm-aarch64-cache.templatex b/clients/drcachesim/tests/allasm-aarch64-cache.templatex
@@ -5,17 +5,20 @@ Core #0 \(1 thread\(s\)\)
   L1I stats:
     Hits:                 *          8[,.]?246
     Misses:                              2
+    Invalidations:        *              0
     Miss rate:                        0[.,]02%
   L1D stats:
     Hits:                 *          2[,.]?030
     Misses:                             16
+    Invalidations:        *              0
     Miss rate:                        0[.,]78%
 Core #1 \(0 thread\(s\)\)
 Core #2 \(0 thread\(s\)\)
 Core #3 \(0 thread\(s\)\)
 LL stats:
     Hits:                                0
     Misses:                             18
+    Invalidations:        *              0
     Local miss rate:                100[.,]00%
     Child hits:           *         10[,.]?276
     Total miss rate:                  0[.,]17%
diff --git a/clients/drcachesim/tests/allasm-arm.templatex b/clients/drcachesim/tests/allasm-arm.templatex
@@ -11,13 +11,15 @@ Core #0 \(1 thread\(s\)\)
   L1I stats:
     Hits:                              [45][90][0-9]
     Misses:                              [5-9]
+    Invalidations:                       0
     Flushes:                             1
     Prefetch hits:                       1
     Prefetch misses:                     1
     Miss rate:                        [01][,\.]..%
   L1D stats:
     Hits:                               1[0-9]
     Misses:                              [1-9]
+    Invalidations:                       0
     Prefetch hits:                       1
     Prefetch misses:                     3
     Miss rate:                       [ 1][0-3][,\.]..%
@@ -27,6 +29,7 @@ Core #3 \(0 thread\(s\)\)
 LL stats:
     Hits:                                1
     Misses:                             [ 1][0-9]
+    Invalidations:                       0
     Flushes:                             1
     Prefetch hits:                       1
     Prefetch misses:                     3

diff --git a/clients/drcachesim/tests/allasm-thumb.templatex b/clients/drcachesim/tests/allasm-thumb.templatex
@@ -11,10 +11,12 @@ Core #0 \(1 thread\(s\)\)
   L1I stats:
     Hits:                              6[34].
     Misses:                             11
+    Invalidations:                       0
     Miss rate:                        1[,\.]69%
   L1D stats:
     Hits:                               3[0-9]
     Misses:                             *[0-9]*
+    Invalidations:                       0
     Prefetch hits:                       1
     Prefetch misses:                     6
     Miss rate:                       [ 1][0-5][,\.]..%
@@ -24,6 +26,7 @@ Core #3 \(0 thread\(s\)\)
 LL stats:
     Hits:                                3
     Misses:                             1[0-9]
+    Invalidations:                       0
     Prefetch hits:                       1
     Prefetch misses:                     [56]
     Local miss rate:                 [89].[,\.]..%

diff --git a/clients/drcachesim/tests/delay-simple.templatex b/clients/drcachesim/tests/delay-simple.templatex
@@ -6,17 +6,20 @@ Core #0 \(1 thread\(s\)\)
   L1I stats:
     Hits:                         *[0-9,\.]*
     Misses:                       *[0-9,\.]*.
+    Invalidations:                *0
 .*   Miss rate:                   *[0-9,\.]*%
   L1D stats:
     Hits:                         *[0-9,\.]*
     Misses:                       *[0-9,\.]*.
+    Invalidations:                *0
 .*   Miss rate:                   *[0-9,\.]*%
 Core #1 \(0 thread\(s\)\)
 Core #2 \(0 thread\(s\)\)
 Core #3 \(0 thread\(s\)\)
 LL stats:
     Hits:                         *[0-9,\.]*.
     Misses:                       *[0-9,\.]*..
+    Invalidations:                *0
 .*   Local miss rate:             *[0-9,\.]*%
     Child hits:                   *[0-9,\.]*.
     Total miss rate:              *[0-9,\.]*%
diff --git a/clients/drcachesim/tests/filter-no-d.templatex b/clients/drcachesim/tests/filter-no-d.templatex
@@ -5,16 +5,19 @@ Core #0 \(1 thread\(s\)\)
   L1I stats:
     Hits:                         *[0-9,\.]*
     Misses:                       *[0-9,\.]*.
+    Invalidations:                *0
 .*   Miss rate:                   *[1-9][0-9][,\.]..%
   L1D stats:
     Hits:                                0
     Misses:                              0
+    Invalidations:                       0
 Core #1 \(0 thread\(s\)\)
 Core #2 \(0 thread\(s\)\)
 Core #3 \(0 thread\(s\)\)
 LL stats:
     Hits:                         *[0-9,\.]*.
     Misses:                       *[0-9,\.]*..
+    Invalidations:                *0
 .*   Local miss rate:             *[1-9][0-9][,\.]..%
     Child hits:                   *[0-9,\.]*.
     Total miss rate:              *[1-9][0-9][,\.]..%
diff --git a/clients/drcachesim/tests/filter-no-i.templatex b/clients/drcachesim/tests/filter-no-i.templatex
@@ -5,16 +5,19 @@ Core #0 \(1 thread\(s\)\)
   L1I stats:
     Hits:                                0
     Misses:                              0
+    Invalidations:                       0
   L1D stats:
     Hits:                         *[0-9,\.]*
     Misses:                       *[0-9,\.]*.
+    Invalidations:                *0
 .*   Miss rate:                   *[1-9][0-9][,\.]..%
 Core #1 \(0 thread\(s\)\)
 Core #2 \(0 thread\(s\)\)
 Core #3 \(0 thread\(s\)\)
 LL stats:
     Hits:                         *[0-9,\.]*.
     Misses:                       *[0-9,\.]*..
+    Invalidations:                *0
 .*   Local miss rate:             *[1-9][0-9][,\.]..%
     Child hits:                   *[0-9,\.]*.
     Total miss rate:              *[1-9][0-9][,\.]..%
diff --git a/clients/drcachesim/tests/filter-simple.templatex b/clients/drcachesim/tests/filter-simple.templatex
@@ -5,17 +5,20 @@ Core #0 \(1 thread\(s\)\)
   L1I stats:
     Hits:                         *[0-9,\.]*
     Misses:                       *[0-9,\.]*.
+    Invalidations:                *0
 .*   Miss rate:                   *[1-9][0-9][,\.]..%
   L1D stats:
     Hits:                         *[0-9,\.]*
     Misses:                       *[0-9,\.]*.
+    Invalidations:                *0
 .*   Miss rate:                   *[1-9][0-9][,\.]..%
 Core #1 \(0 thread\(s\)\)
 Core #2 \(0 thread\(s\)\)
 Core #3 \(0 thread\(s\)\)
 LL stats:
     Hits:                         *[0-9,\.]*.
     Misses:                       *[0-9,\.]*..
+    Invalidations:                *0
 .*   Local miss rate:             *[1-9][0-9][,\.]..%
     Child hits:                   *[0-9,\.]*.
     Total miss rate:              *[1-9][0-9][,\.]..%