MOD: timing relaxed for D-PHY data rate in use: 420Mbps/lane

Digilent · Jun 22, 2018 · f18cbb2 · f18cbb2
1 parent f983b6b
commit f18cbb2
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Showing 6 changed files with 8 additions and 7 deletions.
diff --git a/hw_handoff/system_wrapper.hdf b/hw_handoff/system_wrapper.hdf
diff --git a/sdk/pcam_vdma_hdmi/src/main.cc b/sdk/pcam_vdma_hdmi/src/main.cc
@@ -84,7 +84,7 @@ int main()
 			VDMA_S2MM_IRPT_ID);
 	VideoOutput vid(XPAR_VTC_0_DEVICE_ID, XPAR_VIDEO_DYNCLK_DEVICE_ID);
 
-	pipeline_mode_change(vdma_driver, cam, vid, Resolution::R1920_1080_60_PP, OV5640_cfg::mode_t::MODE_1080P_1920_1080_30fps_336M_MIPI);
+	pipeline_mode_change(vdma_driver, cam, vid, Resolution::R1920_1080_60_PP, OV5640_cfg::mode_t::MODE_1080P_1920_1080_30fps);
 
 
 	xil_printf("Video init done.\r\n");

diff --git a/sdk/system_wrapper_hw_platform_0/.project b/sdk/system_wrapper_hw_platform_0/.project
@@ -1,7 +1,7 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <projectDescription>
 	<name>system_wrapper_hw_platform_0</name>
-	<comment>Created by SDK v2016.4</comment>
+	<comment>Created by SDK v2017.4</comment>
 	<projects>
 	</projects>
 	<buildSpec>
@@ -11,7 +11,7 @@
 	</natures>
 	<filteredResources>
 		<filter>
-			<id>1519295346739</id>
+			<id>1529682269382</id>
 			<name></name>
 			<type>6</type>
 			<matcher>
@@ -20,7 +20,7 @@
 			</matcher>
 		</filter>
 		<filter>
-			<id>1519295346739</id>
+			<id>1529682269387</id>
 			<name></name>
 			<type>6</type>
 			<matcher>
@@ -29,7 +29,7 @@
 			</matcher>
 		</filter>
 		<filter>
-			<id>1519295346749</id>
+			<id>1529682269393</id>
 			<name></name>
 			<type>6</type>
 			<matcher>

diff --git a/sdk/system_wrapper_hw_platform_0/system.hdf b/sdk/system_wrapper_hw_platform_0/system.hdf
diff --git a/src/constraints/ZyboZ7_A.xdc b/src/constraints/ZyboZ7_A.xdc
@@ -170,8 +170,6 @@ set_property -dict {PACKAGE_PIN J20 IOSTANDARD HSUL_12} [get_ports {dphy_data_lp
 
 set_property -dict {PACKAGE_PIN H18 IOSTANDARD LVDS_25} [get_ports dphy_hs_clock_clk_n]
 set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVDS_25} [get_ports dphy_hs_clock_clk_p]
-# 672Mbps/lane = 336 MHz HS_Clk
-create_clock -period 2.976 -name dphy_hs_clock_p -waveform {0.000 1.488} [get_ports dphy_hs_clock_clk_p]
 
 set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVDS_25} [get_ports {dphy_data_hs_n[0]}]
 set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVDS_25} [get_ports {dphy_data_hs_p[0]}]

diff --git a/src/constraints/timing.xdc b/src/constraints/timing.xdc
@@ -16,6 +16,9 @@ create_clock -period 1.667 -name video_dynclk [get_pins -regexp .*video_dynclk/.
 # Comment below to disable underconstraining and live with the Pulse Width errors
 create_clock -period 6.734 -name pixel_dynclk [get_pins -regexp .*DVIClocking_0/U0/PixelClkBuffer/O -hierarchical]
 
+# MIPI D-PHY data rate 420Mbps/lane = 210 MHz HS_Clk
+create_clock -period 4.761 -name dphy_hs_clock_p -waveform {0.000 2.380} [get_ports dphy_hs_clock_clk_p]
+
 # Workaround for FIFO XDC not getting applied (it seems there is no need for this anymore in 2017.4)
 #set_false_path -through [get_pins system_i/MIPI_CSI_2_RX_0/U0/MIPI_CSI2_Rx_inst/LLP_inst/DataFIFO/s_aresetn] -to [get_pins -hierarchical -filter {NAME =~ system_i/MIPI_CSI_2_RX_0/U0/MIPI_CSI2_Rx_inst/LLP_inst/DataFIFO/*rstblk*/*PRE}]
 #set_false_path -from [get_cells -hierarchical -filter {NAME =~ system_i/MIPI_CSI_2_RX_0/U0/MIPI_CSI2_Rx_inst/LLP_inst/DataFIFO/*rstblk*/*rst_reg_reg[*]}]