Added the 'cleanup_dma' helper fn

examples/spi.rs

@@ -136,7 +136,10 @@ fn DMA1_CH2() {
     free(|cs| {
         defmt::println!("SPI DMA read complete");
         access_global!(SPI, spi, cs);
-        spi.stop_dma(DmaChannel::C2, Some(DmaPeriph::Dma2), DmaPeriph::Dma2);
+        spi.stop_dma(DmaChannel::C1, Some(DmaChannel::C2), DmaPeriph::Dma2);
+
+        // See also this convenience function, which clears the interrupt and stops othe Txfer.:
+        spi.cleanup_dma(DmaPeriph::Dma2, DmaChannel::C1, Some(DmaChannel::C2));
 
         unsafe {
             // Ignore byte 0, which is the reg we passed during the write.

src/spi.rs

@@ -1091,7 +1091,6 @@ where
         &mut self,
         channel: DmaChannel,
         channel2: Option<DmaChannel>,
-        // dma: &mut Dma<D>,
         dma_periph: dma::DmaPeriph,
     ) {
         // where
@@ -1123,6 +1122,32 @@ where
         });
     }
 
+    /// Convenience function that clears the interrupt, and stops the transfer. For use with the TC
+    /// interrupt only.
+    pub fn cleanup_dma(
+        &mut self,
+        dma_periph: dma::DmaPeriph,
+        channel_tx: DmaChannel,
+        channel_rx: Option<DmaChannel>,
+    ) {
+        // The hardware seems to automatically enable Tx too; and we use it when transmitting.
+        dma::clear_interrupt(
+            dma_periph,
+            channel_tx,
+            crate::dma::DmaInterrupt::TransferComplete,
+        );
+
+        if let Some(ch_rx) = channel_rx {
+            dma::clear_interrupt(
+                dma_periph,
+                ch_rx,
+                crate::dma::DmaInterrupt::TransferComplete,
+            );
+        }
+
+        self.stop_dma(channel_tx, channel_rx, dma_periph);
+    }
+
     #[cfg(not(any(feature = "h5", feature = "h7")))]
     /// Enable an interrupt. Note that unlike on other peripherals, there's no explicit way to
     /// clear these. RM: "Writing to the transmit data register always clears the TXE bit.