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Minimal SDR with Lattice MachXO2 FPGA. And a port to Cyclone3 by Steven Groom

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FPGASDR_tcr.dir
FPGASDR_tcr.dir
 
 
NCOCalculator
NCOCalculator
 
 
SDR_CycloneIII
SDR_CycloneIII
 
 
g3r
g3r
 
 
impl1
impl1
 
 
n6
n6
 
 
sim2
sim2
 
 
._Real_._Math_.vhd
._Real_._Math_.vhd
 
 
.floorplanner.ini
.floorplanner.ini
 
 
.recovery
.recovery
 
 
.run_manager.ini
.run_manager.ini
 
 
.setting.ini
.setting.ini
 
 
.spread_sheet.ini
.spread_sheet.ini
 
 
.spreadsheet_view.ini
.spreadsheet_view.ini
 
 
AMDemod.v
AMDemod.v
 
 
CIC.v
CIC.v
 
 
FPGASDR.ccl
FPGASDR.ccl
 
 
FPGASDR.ldf
FPGASDR.ldf
 
 
FPGASDR.lpf
FPGASDR.lpf
 
 
FPGASDR1.sty
FPGASDR1.sty
 
 
FPGASDR_tcl.html
FPGASDR_tcl.html
 
 
HP_shift.v
HP_shift.v
 
 
LICENSE.md
LICENSE.md
 
 
Mixer.v
Mixer.v
 
 
MixerSim.v
MixerSim.v
 
 
Multiplier.edn
Multiplier.edn
 
 
Multiplier.ipx
Multiplier.ipx
 
 
Multiplier.lpc
Multiplier.lpc
 
 
Multiplier.naf
Multiplier.naf
 
 
Multiplier.sort
Multiplier.sort
 
 
Multiplier.srp
Multiplier.srp
 
 
Multiplier.sym
Multiplier.sym
 
 
Multiplier.v
Multiplier.v
 
 
Multiplier_generate.log
Multiplier_generate.log
 
 
Multiplier_tmpl.v
Multiplier_tmpl.v
 
 
NCO.v
NCO.v
 
 
NCOAdder.edn
NCOAdder.edn
 
 
NCOAdder.ipx
NCOAdder.ipx
 
 
NCOAdder.lpc
NCOAdder.lpc
 
 
NCOAdder.naf
NCOAdder.naf
 
 
NCOAdder.sort
NCOAdder.sort
 
 
NCOAdder.srp
NCOAdder.srp
 
 
NCOAdder.sym
NCOAdder.sym
 
 
NCOAdder.v
NCOAdder.v
 
 
NCOAdder_generate.log
NCOAdder_generate.log
 
 
NCOAdder_tmpl.v
NCOAdder_tmpl.v
 
 
PLL.edn
PLL.edn
 
 
PLL.ipx
PLL.ipx
 
 
PLL.lpc
PLL.lpc
 
 
PLL.naf
PLL.naf
 
 
PLL.sort
PLL.sort
 
 
PLL.srp
PLL.srp
 
 
PLL.sym
PLL.sym
 
 
PLL.v
PLL.v
 
 
PLL_generate.log
PLL_generate.log
 
 
PLL_tmpl.v
PLL_tmpl.v
 
 
PWM.v
PWM.v
 
 
README.md
README.md
 
 
SinCos.edn
SinCos.edn
 
 
SinCos.ipx
SinCos.ipx
 
 
SinCos.lpc
SinCos.lpc
 
 
SinCos.naf
SinCos.naf
 
 
SinCos.sort
SinCos.sort
 
 
SinCos.srp
SinCos.srp
 
 
SinCos.sym
SinCos.sym
 
 
SinCos.v
SinCos.v
 
 
SinCos_generate.log
SinCos_generate.log
 
 
SinCos_tmpl.v
SinCos_tmpl.v
 
 
TestFifo.v
TestFifo.v
 
 
TestFifo_tmpl.v
TestFifo_tmpl.v
 
 
TestUart.v
TestUart.v
 
 
Uart1.v
Uart1.v
 
 
UartRX.v
UartRX.v
 
 
UartTX.v
UartTX.v
 
 
Untitled.tpf
Untitled.tpf
 
 
frequency_select.v
frequency_select.v
 
 
generate_core.tcl
generate_core.tcl
 
 
generate_ngd.tcl
generate_ngd.tcl
 
 
msg_file.log
msg_file.log
 
 
promote.xml
promote.xml
 
 
reportview.xml
reportview.xml
 
 
tb_Multiplier_tmpl.v
tb_Multiplier_tmpl.v
 
 
tb_NCOAdder_tmpl.v
tb_NCOAdder_tmpl.v
 
 
tb_SinCos_tmpl.v
tb_SinCos_tmpl.v
 
 
timingstrategytest1.sty
timingstrategytest1.sty
 
 
top.v
top.v
 
 

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Minimal SDR with Lattice MachXO2 FPGA. And a port to Cyclone3 by Steven Groom

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