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release/_sources/comp/axis_tools/storage/asfifox/readme.rst.txt
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| .. _axis_asfifox: | ||
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| AXIS_ASFIFOX | ||
| ------------ | ||
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| .. vhdl:autoentity:: AXIS_ASFIFOX |
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148
release/_sources/ndk_apps/minimal/tests/cocotb/readme.rst.txt
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| ===================== | ||
| Top-level simulations | ||
| ===================== | ||
|
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| The top-level simulations (TLS) are suitable for: | ||
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| - software testing without access to real acceleration card | ||
| - whole design compile and basic functionality check | ||
| - address space debugging | ||
| - resets, clocks, clock domain crossings check | ||
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| Basics | ||
| ====== | ||
|
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| What simulation includes / excludes | ||
| ----------------------------------- | ||
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| The TLS doesn’t simulate IP cores but emulates their I/O signals. The | ||
| primary effort is to emulate the Ethernet and PCIe I/O and DMA for the most used FPGA families | ||
| (Xilinx US+, Intel P-TILE, Intel E-TILE, ...). | ||
|
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| Common tips for cocotb | ||
| ---------------------- | ||
|
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| - Use ``sys.stderr`` stream for ModelSim / Questa to achieve instant | ||
| display of log: | ||
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| .. code:: python | ||
| logging.basicConfig(stream=sys.stderr, force=True) | ||
| - Verbose messages for all loggers except some: | ||
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| .. code:: python | ||
| logging.getLogger().setLevel(logging.INFO) | ||
| logging.getLogger("cocotbext.nfb.ext.grpc.server").setLevel(logging.WARNING) | ||
| gRPC example | ||
| ============ | ||
|
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| This variant enables the usage of external processes and is intended for | ||
| manual interaction. The TLS doesn’t contain any real test cases. Instead, it | ||
| starts the gRPC server, runs for a specified simulation time (e.g., 10ms), and | ||
| expects the user to execute an application that uses the acceleration | ||
| card through the ``libnfb`` gRPC extension. The application then generates | ||
| I/O read and write requests and the simulator translates them to the bus | ||
| interface and back. | ||
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| A feature in ``libnfb-ext-grpc`` enables simple handling of DMA requests | ||
| from the simulated design. If the ``dma_vas`` tag is present in the device | ||
| string, the library opens a reverse stream. As soon as the DMA request | ||
| arrives in the process, ``libnfb-ext-grpc`` copies data from/to the virtual | ||
| address space of the process. Just use the virtual address for | ||
| descriptor values. There are no boundary checks and the request can | ||
| potentially harm the process, which probably gets killed by ``SIGSEGV`` | ||
| signal in the case of an error. | ||
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| The simple DMA request handling is most suitable for a DPDK application; | ||
| see the section below. | ||
|
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| Prerequisites | ||
| ------------- | ||
|
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| libnfb-ext-grpc.so from the libnfb-ext-grpc package (RPM) | ||
|
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| Running | ||
| ------- | ||
|
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| 1. Prepare a Python environment and install packages | ||
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| .. code:: shell | ||
| . ./prepare.sh | ||
| 2. Install specific dependencies for the gRPC-based simulation | ||
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| .. code:: shell | ||
| pip install .[grpc] | ||
| 3. Run the simulation | ||
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| .. code:: shell | ||
| make COCOTB_MODULE=cocotb_grpc | ||
| 4. Wait until this message appears in the console | ||
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| ``gRPC server started, listening on 50051. Device string: libnfb-ext-grpc.so:grpc:localhost:50051`` | ||
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| 5. Run your software application and specify the device string | ||
|
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| .. code:: shell | ||
| $ nfb-eth -ri0 -d libnfb-ext-grpc.so:grpc:localhost:50051 | ||
| DPDK usage | ||
| ---------- | ||
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| DPDK needs to be executed with the ``--vdev`` argument: | ||
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| .. code:: shell | ||
| sudo dpdk-testpmd --vdev=eth_vdev_nfb,dev=libnfb-ext-grpc.so:grpc+dma_vas:localhost:50051,queue_driver=native --iova-mode=va -- -i | ||
| The ``queue_driver=native`` is currently the only supported mode, for which the | ||
| ``--iova-mode=va`` is essential. The ``dma_vas`` tag also | ||
| must be stated in the device string: | ||
| ``libnfb-ext-grpc.so:grpc+dma_vas:localhost:50051``. | ||
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| Do not forget to alloc hugepages. | ||
|
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| Tips | ||
| ---- | ||
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| Concurrent processes | ||
| ^^^^^^^^^^^^^^^^^^^^ | ||
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| The simulation environment can handle requests from multiple running | ||
| applications at once. For example: start the ``dpdk-testpmd`` in | ||
| interactive mode, enable MACs with ``nfb-eth -e1`` and then type | ||
| ``start`` in the DPDK app prompt. Be aware that only one application should use | ||
| the ``dma_vas`` tag in the device string at a time. | ||
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| *There is an issue with nfb locks: nfb_comp_lock / nfb_comp_unlock is not | ||
| implemented. Two processes mixing requests on one lock-aware component | ||
| will probably break its function.* | ||
|
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| Locally build libnfb-ext-grpc.so | ||
| ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ | ||
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| If the gRPC client library is not in the standard system path (``/usr/lib``), | ||
| use the full path in the device parameter: | ||
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| .. code:: shell | ||
| nfb-info -d /home/joe/ndk-sw/cmake-build/ext/libnfb-ext-grpc/libnfb-ext-grpc.so:grpc:localhost:50051 | ||
| Remote access to TLS | ||
| ^^^^^^^^^^^^^^^^^^^^ | ||
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| Listen on all IP addresses: | ||
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| ``NfbDmaThreadedGrpcServer(ram, dev, addr='0.0.0.0')`` | ||
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| and run the application on another machine with the ``target_addr:port`` string in the device parameter. | ||
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release/_sources/ndk_cards/bittware/ia-440i/readme.rst.txt
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| .. _card_ia-440i: | ||
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| Bittware IA-440I | ||
| ---------------- | ||
|
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| - Card information: | ||
| - Vendor: Bittware | ||
| - Name: IA-440I | ||
| - Ethernet ports: 1x QSFP-DD | ||
| - PCIe conectors: Edge connector | ||
| - `FPGA Card Website <https://www.bittware.com/fpga/ia-440i/>`_ | ||
| - FPGA specification: | ||
| - FPGA part number: ``AGIB023R18A1E1V`` | ||
| - Ethernet Hard IP: F-Tile (up to 400G Ethernet) | ||
| - PCIe Hard IP: R-Tile (up to PCIe Gen5 x16) | ||
|
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| NDK firmware support | ||
| ^^^^^^^^^^^^^^^^^^^^ | ||
|
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| - Ethernet cores that are supported in the NDK firmware: | ||
| - :ref:`F-Tile in the Network Module <ndk_intel_net_mod>` | ||
| - PCIe cores that are supported in the NDK firmware: | ||
| - :ref:`R-Tile in the PCIe Module <ndk_intel_pcie_mod>` | ||
| - See the ``<NDK-FPGA_root_directory>/cards/bittware/ia-440i/config/card_conf.tcl`` file for supported PCIe configurations. | ||
| - Makefile targets for building the NDK firmware (valid for NDK-APP-Minimal, may vary for other apps): | ||
| - Use ``make 400g1`` command for firmware with 1x400GE (default). | ||
| - Support for booting the NDK firmware using the nfb-boot tool: | ||
| - NO. | ||
|
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| .. note:: | ||
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| To build the NDK firmware for this card, you must have the Intel Quartus Prime Pro installed, including a valid license. | ||
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| Boot instructions | ||
| ^^^^^^^^^^^^^^^^^ | ||
|
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| Before you can work with the card, you will need to install Bittware's SDK and IA-440i Card Support Package (CSP) on your host system. | ||
| To be able to do that, you will also need Python 3 (version >= 3.8) present on your system, so be sure to get that first. | ||
| Next, proceed with the following steps: | ||
|
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| - Download the Bittware SDK and IA-440i CSP installers from the `Bittware Developer Website <https://developer.bittware.com>`_ (version 2024.2). | ||
| - Install both downloaded packages by following the instructions in the Bittware SDK and CSP Installation manual (accessible on the same website). | ||
| - Connect your IA-440i card to the host using the dedicated USB cable. | ||
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| Once this is done, you can check the card status by issuing ``bw_card_list -v``. | ||
| If everything is OK (card has been found and is available via USB), you can use the ``bw_bmc_fpga_load`` utility to manage designs for your card. | ||
|
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| - To get more info about the usage and available subprograms of the ``bw_bmc_fpga_load`` utility, type ``bw_bmc_fpga_load -h``. | ||
| - Use ``bw_bmc_fpga_load table`` to list all stored flash images. | ||
| - Use ``bw_bmc_fpga_load program <ia-440i_design_name>.rbf <address>`` to write the image into the configuration flash on the given address. | ||
| - Use ``bw_bmc_fpga_load default <ia-440i_design_name>.rbf`` to make your design the default boot option. | ||
| - Use ``bw_bmc_fpga_load load <ia-440i_design_name>.rbf`` to configure the fpga with your design from the flash. | ||
| - Use ``bw_bmc_fpga_load stream <ia-440i_design_name>.rbf`` to configure the fpga directly without writing it into the flash. | ||
|
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| .. note:: | ||
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| All designs stored inside the configuration flash (or directly loaded into the fpga) must be built using the same version of Quartus Prime Pro. | ||
|
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| .. warning:: | ||
|
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| So far, there are features of the nfb framework that are not yet fully supported for this card (e. g. ``nfb-eth -T`` or ``nfb-boot``). |
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| .. _card_g35p: | ||
|
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| iWave G35P | ||
| ------------- | ||
|
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| - Card information: | ||
| - Vendor: iWave | ||
| - Name: G35P | ||
| - Ethernet ports: 3x QSFP-DD | ||
| - 2x 200G | ||
| - 1x 40G | ||
| - PCIe conectors: Edge connector | ||
| - `FPGA Card Website <https://www.iwavesystems.com/product/smartnic-storage-accelerator-card-zynq-ultrascale/>`_ | ||
| - FPGA specification: | ||
| - FPGA part number: ``xczu19eg-ffvc1760-2-i`` | ||
| - Ethernet Hard IP: CMAC (up to 100G Ethernet) | ||
| - PCIe Hard IP: USP (up to PCIe Gen3 x16) | ||
|
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| NDK firmware support | ||
| ^^^^^^^^^^^^^^^^^^^^ | ||
|
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||
| - Ethernet cores that are supported in the NDK firmware: | ||
| - :ref:`CMAC in the Network Module <ndk_intel_net_mod>` | ||
| - PCIe cores that are supported in the NDK firmware: | ||
| - :ref:`USP in the PCIe Module <ndk_intel_pcie_mod>` | ||
| - See the ``<NDK-FPGA_root_directory>/card/iwave/g35p/config/card_conf.tcl`` file for supported PCIe configurations. | ||
| - Makefile targets for building the NDK firmware (valid for Minimal app, may vary for other apps): | ||
| - Use ``make 100g2`` command for firmware with 2x100GbE (default). | ||
| - Support for booting the NDK firmware using the nfb-boot tool: | ||
| - NO. | ||
|
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| Boot instructions | ||
| ^^^^^^^^^^^^^^^^^ | ||
|
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| - Set Switch 1 (SW1(3:0)) to SD1 mode: | ||
| - SW1(0) - ON | ||
| - SW1(1) - OFF | ||
| - SW1(2) - ON | ||
| - SW1(3) - OFF | ||
| - Note that default setting is set to SW1: OFF ON ON OFF | ||
| - Note that SW1 is present on the SOM module (under the heatsink) | ||
|
|
||
| - Write the BOOT.bin file to the SD card: | ||
| - BOOT.bin can be generated by `AMD VitisTM <https://www.amd.com/en/products/software/adaptive-socs-and-fpgas/vitis.html>` | ||
| - In order to generate BOOT.bin, it is necessary to have the fsbl.elf file (first stage boot loader) and the generated bit stream. | ||
| - [bootloader] zynqmp_fsbl.elf | ||
| - [destination_device = pl] fpga.bit | ||
|
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| - Insert the SD card into the SD connector at the bottom of the FPGA card. | ||
|
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||
| .. note:: | ||
|
|
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| To build the NDK firmware for this card, you must have the Xilinx Vivado installed, including a valid license. |
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