optimize some code

.cargo/config.toml

@@ -1,7 +1,7 @@
 # 编译的目标平台
 [build]
-# target = 'riscv64imac-unknown-none-elf'
-target = 'x86_64-unknown-none'
+target = 'riscv64imac-unknown-none-elf'
+# target = 'x86_64-unknown-none'
 
 # This flags also can be set from every target.
 rustflags = [

Cargo.toml

@@ -10,8 +10,6 @@ members = [
     "crates/timestamp",
     "crates/vfscore",
     "crates/cv1811-sd",
-    "crates/page_table",
-    "crates/page_table_entry",
     "crates/memory_addr",
     "crates/crate_interface",
 

arch/src/lib.rs

@@ -106,3 +106,18 @@ pub fn clear_bss() {
             .fill(0);
     }
 }
+
+bitflags::bitflags! {
+    #[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)]
+    pub struct MappingFlags: u64 {
+        const None = 0;
+        const U = 1 << 0;
+        const R = 1 << 1;
+        const W = 1 << 2;
+        const X = 1 << 3;
+        const A = 1 << 4;
+        const D = 1 << 5;
+        const Device = 1 << 6;
+        const Cache = 1 << 7;
+    }
+}

arch/src/riscv64/page_table/sv39.rs

@@ -135,17 +135,6 @@ pub fn get_pte_list(paddr: PhysAddr) -> &'static mut [PTE] {
     unsafe { core::slice::from_raw_parts_mut(paddr.get_mut_ptr::<PTE>(), PAGE_ITEM_COUNT) }
 }
 
-fn destory_pte_leaf(paddr: PhysAddr) {
-    let pte_list = get_pte_list(paddr);
-    for pte in pte_list {
-        if pte.is_leaf() {
-            destory_pte_leaf(pte.to_ppn().into());
-            ArchInterface::frame_unalloc(pte.to_ppn());
-        }
-    }
-    ArchInterface::frame_unalloc(paddr.into());
-}
-
 #[derive(Debug)]
 pub struct PageTable(pub(crate) PhysAddr);
 
@@ -244,6 +233,13 @@ impl PageTable {
 
 impl Drop for PageTable {
     fn drop(&mut self) {
-        destory_pte_leaf(self.0);
+        for root_pte in get_pte_list(self.0)[..0x100].iter().filter(|x| x.is_leaf()) {
+            get_pte_list(root_pte.to_ppn().into())
+                .iter()
+                .filter(|x| x.is_leaf())
+                .for_each(|x| ArchInterface::frame_unalloc(x.to_ppn()));
+            ArchInterface::frame_unalloc(root_pte.to_ppn());
+        }
+        ArchInterface::frame_unalloc(self.0.into());
     }
 }

arch/src/x86_64/mod.rs

@@ -23,37 +23,6 @@ use x86_64::instructions::port::PortWriteOnly;
 
 use crate::x86_64::multiboot::use_multiboot;
 
-#[link_section = ".data.prepage.entry"]
-static KERNEL_PDPT: PDPT = {
-    let mut arr: PDPT = [PDPTEntry(0); PAGE_SIZE_ENTRIES];
-    // 0x00000000_80000000 -> 0x80000000 (1G)
-    // arr[0] = PDPTEntry::new(PAddr(0x0), PDPTFlags::P | PDPTFlags::RW | PDPTFlags::PS);
-    // arr[1] = PDPTEntry::new(PAddr(0x40000000), PDPTFlags::P | PDPTFlags::RW | PDPTFlags::PS);
-    // arr[2] = PDPTEntry::new(PAddr(0x80000000), PDPTFlags::P | PDPTFlags::RW | PDPTFlags::PS);
-    // arr[3] = PDPTEntry::new(PAddr(0xc0000000), PDPTFlags::P | PDPTFlags::RW | PDPTFlags::PS);
-    arr[0] = PDPTEntry(0x0 | 0x83);
-    arr[1] = PDPTEntry(0x40000000 | 0x83);
-    arr[2] = PDPTEntry(0x80000000 | 0x83);
-    arr[3] = PDPTEntry(0xc0000000 | 0x83);
-    arr
-};
-
-// #[link_section = ".data.prepage.entry"]
-// static PAGE_TABLE: PML4 = {
-//     let mut arr: PML4 = [PML4Entry(0); PAGE_SIZE_ENTRIES];
-
-//     // arr[2] = PTE::from_addr(0x8000_0000, PTEFlags::ADVRWX);
-//     // arr[0x100] = PTE::from_addr(0x0000_0000, PTEFlags::ADGVRWX);
-//     // arr[0x101] = PTE::from_addr(0x4000_0000, PTEFlags::ADGVRWX);
-//     // arr[0x102] = PTE::from_addr(0x8000_0000, PTEFlags::ADGVRWX);
-//     // arr[0x106] = PTE::from_addr(0x8000_0000, PTEFlags::ADVRWX);
-//     // arr[0] = PML4Entry::new(PAddr(KERNEL_PDPT.as_ptr() as u64 - VIRT_ADDR_START as u64), PML4Flags::P | PML4Flags::RW);
-//     let ptr = &KERNEL_PDPT as *const [PDPTEntry; PAGE_SIZE_ENTRIES] as *const PDPTEntry;
-//     let paddr: u64 = unsafe { transmute(ptr.sub(VIRT_ADDR_START)) };
-//     arr[0] = PML4Entry(paddr | 3);
-//     arr
-// };
-
 pub fn shutdown() -> ! {
     unsafe { PortWriteOnly::new(0x604).write(0x2000u16) };
 

arch/src/x86_64/page_table.rs

@@ -5,7 +5,6 @@ use crate::{ArchInterface, PhysAddr, PhysPage, VirtAddr, VirtPage, PAGE_ITEM_COU
 
 use super::sigtrx::get_trx_mapping;
 
-
 #[derive(Copy, Clone, Debug)]
 pub struct PTE(usize);
 impl PTE {
@@ -122,17 +121,6 @@ pub fn get_pte_list(paddr: PhysAddr) -> &'static mut [PTE] {
     unsafe { core::slice::from_raw_parts_mut(paddr.get_mut_ptr::<PTE>(), PAGE_ITEM_COUNT) }
 }
 
-fn destory_pte_leaf(paddr: PhysAddr) {
-    let pte_list = get_pte_list(paddr);
-    for pte in pte_list {
-        if pte.is_leaf() {
-            destory_pte_leaf(pte.to_ppn().into());
-            ArchInterface::frame_unalloc(pte.to_ppn());
-        }
-    }
-    ArchInterface::frame_unalloc(paddr.into());
-}
-
 #[derive(Debug)]
 pub struct PageTable(pub(crate) PhysAddr);
 
@@ -169,8 +157,7 @@ impl PageTable {
     }
 
     #[inline]
-    pub fn map(&self, ppn: PhysPage, vpn: VirtPage, flags: PTEFlags, level: usize)
-    {
+    pub fn map(&self, ppn: PhysPage, vpn: VirtPage, flags: PTEFlags, level: usize) {
         // TODO: Add huge page support.
         let mut pte_list = get_pte_list(self.0);
         for i in (1..level).rev() {
@@ -225,9 +212,15 @@ impl PageTable {
 
 impl Drop for PageTable {
     fn drop(&mut self) {
-        destory_pte_leaf(self.0);
+        for root_pte in get_pte_list(self.0)[..0x100].iter().filter(|x| x.is_leaf()) {
+            get_pte_list(root_pte.to_ppn().into())
+                .iter()
+                .filter(|x| x.is_leaf())
+                .for_each(|x| ArchInterface::frame_unalloc(x.to_ppn()));
+            ArchInterface::frame_unalloc(root_pte.to_ppn());
+        }
+        ArchInterface::frame_unalloc(self.0.into());
     }
 }
 
-pub fn switch_to_kernel_page_table() {
-}
+pub fn switch_to_kernel_page_table() {}