fix some code and loongarch64

arch/src/aarch64/context.rs

@@ -117,31 +117,31 @@ impl Index<ContextArgs> for Context {
 
     fn index(&self, index: ContextArgs) -> &Self::Output {
         match index {
-            ContextArgs::SEPC       => &self.elr,
-            ContextArgs::RA         => &self.regs[30],
-            ContextArgs::SP         => &self.sp,
-            ContextArgs::RET        => &self.regs[0],
-            ContextArgs::ARG0       => &self.regs[0],
-            ContextArgs::ARG1       => &self.regs[1],
-            ContextArgs::ARG2       => &self.regs[2],
-            ContextArgs::TLS        => &self.tpidr,
-            ContextArgs::SYSCALL    => &self.regs[8],
+            ContextArgs::SEPC => &self.elr,
+            ContextArgs::RA => &self.regs[30],
+            ContextArgs::SP => &self.sp,
+            ContextArgs::RET => &self.regs[0],
+            ContextArgs::ARG0 => &self.regs[0],
+            ContextArgs::ARG1 => &self.regs[1],
+            ContextArgs::ARG2 => &self.regs[2],
+            ContextArgs::TLS => &self.tpidr,
+            ContextArgs::SYSCALL => &self.regs[8],
         }
     }
 }
 
 impl IndexMut<ContextArgs> for Context {
     fn index_mut(&mut self, index: ContextArgs) -> &mut Self::Output {
         match index {
-            ContextArgs::SEPC       => &mut self.elr,
-            ContextArgs::RA         => &mut self.regs[30],
-            ContextArgs::SP         => &mut self.sp,
-            ContextArgs::RET        => &mut self.regs[0],
-            ContextArgs::ARG0       => &mut self.regs[0],
-            ContextArgs::ARG1       => &mut self.regs[1],
-            ContextArgs::ARG2       => &mut self.regs[2],
-            ContextArgs::TLS        => &mut self.tpidr,
-            ContextArgs::SYSCALL    => &mut self.regs[8],
+            ContextArgs::SEPC => &mut self.elr,
+            ContextArgs::RA => &mut self.regs[30],
+            ContextArgs::SP => &mut self.sp,
+            ContextArgs::RET => &mut self.regs[0],
+            ContextArgs::ARG0 => &mut self.regs[0],
+            ContextArgs::ARG1 => &mut self.regs[1],
+            ContextArgs::ARG2 => &mut self.regs[2],
+            ContextArgs::TLS => &mut self.tpidr,
+            ContextArgs::SYSCALL => &mut self.regs[8],
         }
     }
 }

arch/src/aarch64/page_table.rs

@@ -151,7 +151,9 @@ impl PageTable {
     #[inline]
     pub fn restore(&self) {
         let drop_l3 = |l3: PhysAddr| {
-            l3.slice_mut_with_len::<PTE>(0x200).iter_mut().for_each(|x| *x = PTE(0));
+            l3.slice_mut_with_len::<PTE>(0x200)
+                .iter_mut()
+                .for_each(|x| *x = PTE(0));
         };
         let drop_l2 = |l2: PhysAddr| {
             l2.slice_mut_with_len::<PTE>(0x200).iter().for_each(|x| {
@@ -160,11 +162,14 @@ impl PageTable {
                 }
             })
         };
-        self.0.slice_mut_with_len::<PTE>(0x200).iter().for_each(|x| {
-            if x.0 & 0b11 == 0b11 {
-                drop_l2(x.to_ppn().into())
-            }
-        });
+        self.0
+            .slice_mut_with_len::<PTE>(0x200)
+            .iter()
+            .for_each(|x| {
+                if x.0 & 0b11 == 0b11 {
+                    drop_l2(x.to_ppn().into())
+                }
+            });
         flush_tlb(None)
     }
 

arch/src/addr.rs

@@ -1,5 +1,8 @@
 use core::{
-    ffi::CStr, fmt::{Debug, Display}, mem::size_of, ops::Add
+    ffi::CStr,
+    fmt::{Debug, Display},
+    mem::size_of,
+    ops::Add,
 };
 
 use crate::{PAGE_SIZE, VIRT_ADDR_START};
@@ -205,7 +208,11 @@ impl PhysPage {
     pub fn drop_clear(&self) {
         // self.get_buffer().fill(0);
         unsafe {
-            core::slice::from_raw_parts_mut((self.0 << 12 | VIRT_ADDR_START) as *mut usize, PAGE_SIZE / size_of::<usize>()).fill(0);
+            core::slice::from_raw_parts_mut(
+                (self.0 << 12 | VIRT_ADDR_START) as *mut usize,
+                PAGE_SIZE / size_of::<usize>(),
+            )
+            .fill(0);
         }
         #[cfg(c906)]
         unsafe {

arch/src/lib.rs

@@ -126,8 +126,11 @@ pub fn clear_bss() {
         fn _ebss();
     }
     unsafe {
-        core::slice::from_raw_parts_mut(_sbss as usize as *mut u128, (_ebss as usize - _sbss as usize) / size_of::<u128>())
-            .fill(0);
+        core::slice::from_raw_parts_mut(
+            _sbss as usize as *mut u128,
+            (_ebss as usize - _sbss as usize) / size_of::<u128>(),
+        )
+        .fill(0);
     }
 }
 

arch/src/loongarch64/boot.rs

@@ -1,14 +1,3 @@
-use crate::{PTEFlags, VirtAddr};
-use core::arch::asm;
-
-#[link_section = ".data.prepage"]
-static mut BOOT_PT_L1: [usize; 512] = [0; 512];
-
-#[inline]
-pub fn flush_tlb(vaddr: Option<VirtAddr>) {
-    todo!("flush_tlb")
-}
-
 /// The earliest entry point for the primary CPU.
 ///
 /// We can't use bl to jump to higher address, so we use jirl to jump to higher address.

arch/src/loongarch64/console.rs

@@ -60,11 +60,10 @@ pub fn console_putchar(c: u8) {
 }
 
 pub fn write_fmt(args: core::fmt::Arguments) {
-    use core::fmt::Write;
     COM1.lock().write_fmt(args).unwrap();
 }
 
 /// read a byte, return -1 if nothing exists.
-pub fn console_getchar() -> u8 {
-    COM1.lock().getchar().unwrap_or(u8::MAX)
+pub fn console_getchar() -> Option<u8> {
+    COM1.lock().getchar()
 }

arch/src/loongarch64/context.rs

@@ -1,51 +1,18 @@
-use crate::ContextOps;
+use core::ops::{Index, IndexMut};
 
-#[repr(C)]
-#[derive(Debug, Default, Clone, Copy)]
-pub struct GeneralRegs {
-    x0: usize,
-    x1: usize,
-    x2: usize,
-    x3: usize,
-    x4: usize,
-    x5: usize,
-    x6: usize,
-    x7: usize,
-    x8: usize,
-    x9: usize,
-    x10: usize,
-    x11: usize,
-    x12: usize,
-    x13: usize,
-    x14: usize,
-    x15: usize,
-    x16: usize,
-    x17: usize,
-    x18: usize,
-    x19: usize,
-    x20: usize,
-    x21: usize,
-    x22: usize,
-    x23: usize,
-    x24: usize,
-    x25: usize,
-    x26: usize,
-    x27: usize,
-    x28: usize,
-    x29: usize,
-    x30: usize,
-}
+use crate::ContextArgs;
 
 /// Saved registers when a trap (interrupt or exception) occurs.
 #[allow(missing_docs)]
 #[repr(C)]
 #[derive(Debug, Default, Clone, Copy)]
 pub struct Context {
-    pub regs: GeneralRegs,
-    pub sp: usize,
-    pub elr: usize,
-    pub spsr: usize,
-    pub tpidr: usize,
+    /// General Registers
+    pub regs: [usize; 32],
+    /// Pre-exception Mode information
+    pub prmd: usize,
+    /// Exception Return Address
+    pub era: usize,
 }
 
 impl Context {
@@ -58,76 +25,47 @@ impl Context {
     }
 }
 
-impl ContextOps for Context {
-    #[inline]
-    fn set_sp(&mut self, sp: usize) {
-        self.sp = sp
-    }
-
-    #[inline]
-    fn sp(&self) -> usize {
-        self.sp
-    }
-    #[inline]
-    fn set_ra(&mut self, _ra: usize) {
-        unimplemented!("set ra in x86_64 is not implemented")
-    }
-
-    #[inline]
-    fn ra(&self) -> usize {
-        unimplemented!("get ra in x86_64 is not implemented")
-    }
-
-    #[inline]
-    fn set_sepc(&mut self, sepc: usize) {
-        self.elr = sepc;
-    }
-
-    #[inline]
-    fn sepc(&self) -> usize {
-        self.elr
-    }
-
-    #[inline]
-    fn syscall_number(&self) -> usize {
-        self.regs.x8
-    }
-
-    #[inline]
-    fn args(&self) -> [usize; 6] {
-        [
-            self.regs.x0,
-            self.regs.x1,
-            self.regs.x2,
-            self.regs.x3,
-            self.regs.x4,
-            self.regs.x5,
-        ]
+impl Context {
+    pub fn syscall_ok(&self) {
+        todo!("syscall ok");
     }
 
     #[inline]
-    fn syscall_ok(&mut self) {
-        // self.sepc += 4;
-    }
-
-    fn set_ret(&mut self, ret: usize) {
-        self.regs.x0 = ret;
-    }
-
-    fn set_arg0(&mut self, ret: usize) {
-        self.regs.x0 = ret;
-    }
-
-    fn set_arg1(&mut self, ret: usize) {
-        self.regs.x1 = ret;
+    pub fn args(&self) -> [usize; 6] {
+        todo!("get args");
     }
+}
 
-    fn set_arg2(&mut self, ret: usize) {
-        self.regs.x2 = ret;
+impl Index<ContextArgs> for Context {
+    type Output = usize;
+
+    fn index(&self, index: ContextArgs) -> &Self::Output {
+        match index {
+            ContextArgs::SEPC => &self.era,
+            ContextArgs::RA => &self.regs[1],
+            ContextArgs::SP => &self.regs[3],
+            ContextArgs::RET => &self.regs[4],
+            ContextArgs::ARG0 => &self.regs[4],
+            ContextArgs::ARG1 => &self.regs[5],
+            ContextArgs::ARG2 => &self.regs[6],
+            ContextArgs::TLS => &self.regs[2],
+            ContextArgs::SYSCALL => &self.regs[7],
+        }
     }
+}
 
-    #[inline]
-    fn set_tls(&mut self, tls: usize) {
-        self.tpidr = tls
+impl IndexMut<ContextArgs> for Context {
+    fn index_mut(&mut self, index: ContextArgs) -> &mut Self::Output {
+        match index {
+            ContextArgs::SEPC => &mut self.era,
+            ContextArgs::RA => &mut self.regs[1],
+            ContextArgs::SP => &mut self.regs[3],
+            ContextArgs::RET => &mut self.regs[4],
+            ContextArgs::ARG0 => &mut self.regs[4],
+            ContextArgs::ARG1 => &mut self.regs[5],
+            ContextArgs::ARG2 => &mut self.regs[6],
+            ContextArgs::TLS => &mut self.regs[2],
+            ContextArgs::SYSCALL => &mut self.regs[7],
+        }
     }
 }

arch/src/loongarch64/mod.rs

@@ -6,28 +6,29 @@ mod page_table;
 mod timer;
 mod trap;
 
-use alloc::vec::Vec;
 pub use console::{console_getchar, console_putchar};
 pub use consts::*;
 pub use context::Context;
-use fdt::Fdt;
 pub use page_table::*;
 pub use timer::get_time;
-pub use trap::{enable_external_irq, enable_irq, init_interrupt, trap_pre_handle, user_restore};
+pub use trap::{enable_external_irq, enable_irq, init_interrupt, run_user_task};
 
 use crate::{clear_bss, ArchInterface};
 
 pub fn rust_tmp_main(hart_id: usize) {
     clear_bss();
     ArchInterface::init_logging();
     allocator::init();
+    trap::set_trap_vector_base();
 
     ArchInterface::add_memory_region(
         VIRT_ADDR_START | 0x9000_0000,
-        VIRT_ADDR_START | (0x9000_0000 + 0x2f00_0000),
+        VIRT_ADDR_START | (0x9000_0000 + 0x2000_0000),
     );
     info!("hart_id: {}", hart_id);
-
+    unsafe {
+        core::arch::asm!("break 2");
+    }
     ArchInterface::prepare_drivers();
 
     shutdown();

arch/src/loongarch64/page_table.rs

@@ -1,14 +1,9 @@
-use core::arch::asm;
-
 use alloc::sync::Arc;
-use bitflags::bitflags;
 
 use crate::{
     ArchInterface, MappingFlags, PhysAddr, PhysPage, VirtAddr, VirtPage, PAGE_ITEM_COUNT, PAGE_SIZE,
 };
 
-use super::boot::flush_tlb;
-
 #[derive(Copy, Clone, Debug)]
 pub struct PTE(usize);
 
@@ -177,20 +172,8 @@ impl PageTable {
     }
 
     #[inline]
-    pub fn unmap(&self, vpn: VirtPage) {
+    pub fn unmap(&self, _vpn: VirtPage) {
         todo!("unmap pages");
-        // TODO: Add huge page support.
-        let mut pte_list = get_pte_list(self.0);
-        for i in (1..3).rev() {
-            let value = (vpn.0 >> 9 * i) & 0x1ff;
-            let pte = &mut pte_list[value];
-            if !pte.is_valid() {
-                return;
-            }
-            pte_list = get_pte_list(pte.to_ppn().into());
-        }
-
-        pte_list[vpn.0 & 0x1ff] = PTE::new();
     }
 
     #[inline]
@@ -222,3 +205,8 @@ impl PageTable {
 //         ArchInterface::frame_unalloc(self.0.into());
 //     }
 // }
+
+#[inline]
+pub fn flush_tlb(_vaddr: Option<VirtAddr>) {
+    todo!("flush_tlb")
+}