[Feature] always_* blocks inside interface

[taichi-ishitani]

SV interface can have always_* blocks.
Veryl should also support this feature.

refs: #908

[taichi-ishitani]

AssignDeclaration should also be supported.

[dalance]

I have no experience of these usage. Could you explain actual use case?

[taichi-ishitani]

For example, ack logic is commnly used for handshake protocols.
By supporting this feature, this ack logic can be declared in an interface like below.

interface foo_if;
  logic       ready;
  logic       valid;
  logic [7:0] data;
  logic       ack;

  always_comb ack = ready && valid;

  modport master (
    input  ready,
    output valid,
    output data,
    input  ack
  );

  modport slave (
    output ready,
    input  valid,
    input  data,
    input  ack
  );
endinterface

And it can be used like below.

always_ff @(posedge i_clk) begin
  if (foo_if.ack) begin
    data <= foo_if.data;
  end
end

I think this feature can help to increase readability and maintainability.

[dalance]

Thanks!
I understood the use case.