[Feature] Infer clock domain

[taichi-ishitani]

We need to add clock domain annotation to all variables if a module have multiple clock domains.
I think Veryl compiler can infer clock domains in almost cases like bwlow and it would be nace to support it.

i_a: input `a logic,
i_b: input `a logic,

let c: logic = a & b; // Clock domain of `c` can be infered

[taichi-ishitani]

I think following limitations are reasonable for ease of implementation.

• Add clock domain annotation to signals which are connected module instances
• Variables used as function argument belong to the same clock domain