Not check type mismatch between connected interface and port declaration

[taichi-ishitani]

Currently, Veryl compiler does not check type of connected interface.
Following code includes type mismatch between connected interface and port declaration but no error is raised.

interface foo_if {
  var a: logic;
  modport mp {
    a: output
  }
}

interface bar_if {
  var a: logic;
  modport mp {
    a: output
  }
}

module sub (
  foo: modport foo_if::mp
){
  assign foo.a = 0;
}

module top (
  o_a: output logic
) {
  inst bar: bar_if;
  inst u_sub: sub (foo: bar); // type mismatch

  assign o_a = bar.a;
}

[dalance]

Related: #1017