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nano6502.gprj
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<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE gowin-fpga-project>
<Project>
<Template>FPGA</Template>
<Version>5</Version>
<Device name="GW2AR-18C" pn="GW2AR-LV18QN88C8/I7">gw2ar18c-000</Device>
<FileList>
<File path="src/UART/uart.v" type="file.verilog" enable="1"/>
<File path="src/UART/uart_rx.v" type="file.verilog" enable="1"/>
<File path="src/UART/uart_rx_flex.v" type="file.verilog" enable="1"/>
<File path="src/UART/uart_tx.v" type="file.verilog" enable="1"/>
<File path="src/UART/uart_tx_flex.v" type="file.verilog" enable="1"/>
<File path="src/addr_decoder.v" type="file.verilog" enable="1"/>
<File path="src/bootrom.v" type="file.verilog" enable="1"/>
<File path="src/charbuf_dpram/charbuf_dpram.v" type="file.verilog" enable="1"/>
<File path="src/dvi_tx/dvi_tx.v" type="file.verilog" enable="1"/>
<File path="src/gowin_dpb/sector_dpram.v" type="file.verilog" enable="1"/>
<File path="src/gpio.v" type="file.verilog" enable="1"/>
<File path="src/instram.v" type="file.verilog" enable="1"/>
<File path="src/leds.v" type="file.verilog" enable="1"/>
<File path="src/nano6502_top.v" type="file.verilog" enable="1"/>
<File path="src/sdcard/sd_interface.v" type="file.verilog" enable="1"/>
<File path="src/sdcard/sd_rw.v" type="file.verilog" enable="1"/>
<File path="src/sdcard/sdcmd_ctrl.v" type="file.verilog" enable="1"/>
<File path="src/soundgen/adsr.v" type="file.verilog" enable="1"/>
<File path="src/soundgen/audio_drive.v" type="file.verilog" enable="1"/>
<File path="src/soundgen/mixer.v" type="file.verilog" enable="1"/>
<File path="src/soundgen/oscillator.v" type="file.verilog" enable="1"/>
<File path="src/soundgen/soundgen_interface.v" type="file.verilog" enable="1"/>
<File path="src/timer.v" type="file.verilog" enable="1"/>
<File path="src/usb_hid_host/usb_hid_host.v" type="file.verilog" enable="1"/>
<File path="src/usb_hid_host/usb_hid_host_rom.v" type="file.verilog" enable="1"/>
<File path="src/usb_hid_host/usb_interface.v" type="file.verilog" enable="1"/>
<File path="src/verilog-6502/ALU.v" type="file.verilog" enable="1"/>
<File path="src/verilog-6502/cpu_65c02.v" type="file.verilog" enable="1"/>
<File path="src/video/fontrom.v" type="file.verilog" enable="1"/>
<File path="src/video/video.v" type="file.verilog" enable="1"/>
<File path="src/nano6502_top.cst" type="file.cst" enable="1"/>
<File path="src/nano6502_top.sdc" type="file.sdc" enable="1"/>
</FileList>
</Project>