diff --git a/fpga/common/rtl/mqnic_interface.v b/fpga/common/rtl/mqnic_interface.v index 94e94bc33..5426cfd45 100644 --- a/fpga/common/rtl/mqnic_interface.v +++ b/fpga/common/rtl/mqnic_interface.v @@ -2227,15 +2227,18 @@ wire [SCHEDULERS-1:0] tx_sched_req_ready; wire [SCHEDULERS-1:0] tx_sched_status_dequeue_empty; wire [SCHEDULERS-1:0] tx_sched_status_dequeue_error; +wire [SCHEDULERS*TX_QUEUE_INDEX_WIDTH-1:0] tx_sched_status_dequeue_queue; wire [SCHEDULERS*REQ_TAG_WIDTH-1:0] tx_sched_status_dequeue_tag; wire [SCHEDULERS-1:0] tx_sched_status_dequeue_valid; wire [SCHEDULERS-1:0] tx_sched_status_start_error; wire [SCHEDULERS*DMA_CLIENT_LEN_WIDTH-1:0] tx_sched_status_start_len; +wire [SCHEDULERS*TX_QUEUE_INDEX_WIDTH-1:0] tx_sched_status_start_queue; wire [SCHEDULERS*REQ_TAG_WIDTH-1:0] tx_sched_status_start_tag; wire [SCHEDULERS-1:0] tx_sched_status_start_valid; wire [SCHEDULERS*DMA_CLIENT_LEN_WIDTH-1:0] tx_sched_status_finish_len; +wire [SCHEDULERS*TX_QUEUE_INDEX_WIDTH-1:0] tx_sched_status_finish_queue; wire [SCHEDULERS*REQ_TAG_WIDTH-1:0] tx_sched_status_finish_tag; wire [SCHEDULERS-1:0] tx_sched_status_finish_valid; @@ -2247,15 +2250,18 @@ wire tx_req_ready; wire tx_status_dequeue_empty; wire tx_status_dequeue_error; +wire [TX_QUEUE_INDEX_WIDTH-1:0] tx_status_dequeue_queue; wire [REQ_TAG_WIDTH-1:0] tx_status_dequeue_tag; wire tx_status_dequeue_valid; wire tx_status_start_error; wire [DMA_CLIENT_LEN_WIDTH-1:0] tx_status_start_len; +wire [TX_QUEUE_INDEX_WIDTH-1:0] tx_status_start_queue; wire [REQ_TAG_WIDTH-1:0] tx_status_start_tag; wire tx_status_start_valid; wire [DMA_CLIENT_LEN_WIDTH-1:0] tx_status_finish_len; +wire [TX_QUEUE_INDEX_WIDTH-1:0] tx_status_finish_queue; wire [REQ_TAG_WIDTH-1:0] tx_status_finish_tag; wire tx_status_finish_valid; @@ -2366,15 +2372,18 @@ for (n = 0; n < SCHEDULERS; n = n + 1) begin : sched */ .s_axis_tx_status_dequeue_empty(tx_sched_status_dequeue_empty[n +: 1]), .s_axis_tx_status_dequeue_error(tx_sched_status_dequeue_error[n +: 1]), + .s_axis_tx_status_dequeue_queue(tx_sched_status_dequeue_queue[n*TX_QUEUE_INDEX_WIDTH +: TX_QUEUE_INDEX_WIDTH]), .s_axis_tx_status_dequeue_tag(tx_sched_status_dequeue_tag[n*REQ_TAG_WIDTH_INT +: REQ_TAG_WIDTH_INT]), .s_axis_tx_status_dequeue_valid(tx_sched_status_dequeue_valid[n +: 1]), .s_axis_tx_status_start_error(tx_sched_status_start_error[n +: 1]), .s_axis_tx_status_start_len(tx_sched_status_start_len[n*DMA_CLIENT_LEN_WIDTH +: DMA_CLIENT_LEN_WIDTH]), + .s_axis_tx_status_start_queue(tx_sched_status_start_queue[n*TX_QUEUE_INDEX_WIDTH +: TX_QUEUE_INDEX_WIDTH]), .s_axis_tx_status_start_tag(tx_sched_status_start_tag[n*REQ_TAG_WIDTH_INT +: REQ_TAG_WIDTH_INT]), .s_axis_tx_status_start_valid(tx_sched_status_start_valid[n +: 1]), .s_axis_tx_status_finish_len(tx_sched_status_finish_len[n*DMA_CLIENT_LEN_WIDTH +: DMA_CLIENT_LEN_WIDTH]), + .s_axis_tx_status_finish_queue(tx_sched_status_finish_queue[n*TX_QUEUE_INDEX_WIDTH +: TX_QUEUE_INDEX_WIDTH]), .s_axis_tx_status_finish_tag(tx_sched_status_finish_tag[n*REQ_TAG_WIDTH_INT +: REQ_TAG_WIDTH_INT]), .s_axis_tx_status_finish_valid(tx_sched_status_finish_valid[n +: 1]), @@ -2442,15 +2451,18 @@ if (SCHEDULERS > 1) begin */ .s_axis_status_dequeue_empty(tx_status_dequeue_empty), .s_axis_status_dequeue_error(tx_status_dequeue_error), + .s_axis_status_dequeue_queue(tx_status_dequeue_queue), .s_axis_status_dequeue_tag(tx_status_dequeue_tag), .s_axis_status_dequeue_valid(tx_status_dequeue_valid), .s_axis_status_start_error(tx_status_start_error), .s_axis_status_start_len(tx_status_start_len), + .s_axis_status_start_queue(tx_status_start_queue), .s_axis_status_start_tag(tx_status_start_tag), .s_axis_status_start_valid(tx_status_start_valid), .s_axis_status_finish_len(tx_status_finish_len), + .s_axis_status_finish_queue(tx_status_finish_queue), .s_axis_status_finish_tag(tx_status_finish_tag), .s_axis_status_finish_valid(tx_status_finish_valid), @@ -2468,15 +2480,18 @@ if (SCHEDULERS > 1) begin */ .m_axis_status_dequeue_empty(tx_sched_status_dequeue_empty), .m_axis_status_dequeue_error(tx_sched_status_dequeue_error), + .m_axis_status_dequeue_queue(tx_sched_status_dequeue_queue), .m_axis_status_dequeue_tag(tx_sched_status_dequeue_tag), .m_axis_status_dequeue_valid(tx_sched_status_dequeue_valid), .m_axis_status_start_error(tx_sched_status_start_error), .m_axis_status_start_len(tx_sched_status_start_len), + .m_axis_status_start_queue(tx_sched_status_start_queue), .m_axis_status_start_tag(tx_sched_status_start_tag), .m_axis_status_start_valid(tx_sched_status_start_valid), .m_axis_status_finish_len(tx_sched_status_finish_len), + .m_axis_status_finish_queue(tx_sched_status_finish_queue), .m_axis_status_finish_tag(tx_sched_status_finish_tag), .m_axis_status_finish_valid(tx_sched_status_finish_valid) ); @@ -2491,15 +2506,18 @@ end else begin assign tx_sched_status_dequeue_empty = tx_status_dequeue_empty; assign tx_sched_status_dequeue_error = tx_status_dequeue_error; + assign tx_sched_status_dequeue_queue = tx_status_dequeue_queue; assign tx_sched_status_dequeue_tag = tx_status_dequeue_tag; assign tx_sched_status_dequeue_valid = tx_status_dequeue_valid; assign tx_sched_status_start_error = tx_status_start_error; assign tx_sched_status_start_len = tx_status_start_len; + assign tx_sched_status_start_queue = tx_status_start_queue; assign tx_sched_status_start_tag = tx_status_start_tag; assign tx_sched_status_start_valid = tx_status_start_valid; assign tx_sched_status_finish_len = tx_status_finish_len; + assign tx_sched_status_finish_queue = tx_status_finish_queue; assign tx_sched_status_finish_tag = tx_status_finish_tag; assign tx_sched_status_finish_valid = tx_status_finish_valid; @@ -2593,15 +2611,18 @@ interface_tx_inst ( */ .m_axis_tx_status_dequeue_empty(tx_status_dequeue_empty), .m_axis_tx_status_dequeue_error(tx_status_dequeue_error), + .m_axis_tx_status_dequeue_queue(tx_status_dequeue_queue), .m_axis_tx_status_dequeue_tag(tx_status_dequeue_tag), .m_axis_tx_status_dequeue_valid(tx_status_dequeue_valid), .m_axis_tx_status_start_error(tx_status_start_error), .m_axis_tx_status_start_len(tx_status_start_len), + .m_axis_tx_status_start_queue(tx_status_start_queue), .m_axis_tx_status_start_tag(tx_status_start_tag), .m_axis_tx_status_start_valid(tx_status_start_valid), .m_axis_tx_status_finish_len(tx_status_finish_len), + .m_axis_tx_status_finish_queue(tx_status_finish_queue), .m_axis_tx_status_finish_tag(tx_status_finish_tag), .m_axis_tx_status_finish_valid(tx_status_finish_valid), diff --git a/fpga/common/rtl/mqnic_interface_tx.v b/fpga/common/rtl/mqnic_interface_tx.v index 06d9627af..bc365a9f5 100644 --- a/fpga/common/rtl/mqnic_interface_tx.v +++ b/fpga/common/rtl/mqnic_interface_tx.v @@ -85,15 +85,18 @@ module mqnic_interface_tx # */ output wire m_axis_tx_status_dequeue_empty, output wire m_axis_tx_status_dequeue_error, + output wire [QUEUE_INDEX_WIDTH-1:0] m_axis_tx_status_dequeue_queue, output wire [REQ_TAG_WIDTH-1:0] m_axis_tx_status_dequeue_tag, output wire m_axis_tx_status_dequeue_valid, output wire m_axis_tx_status_start_error, output wire [DMA_CLIENT_LEN_WIDTH-1:0] m_axis_tx_status_start_len, + output wire [QUEUE_INDEX_WIDTH-1:0] m_axis_tx_status_start_queue, output wire [REQ_TAG_WIDTH-1:0] m_axis_tx_status_start_tag, output wire m_axis_tx_status_start_valid, output wire [DMA_CLIENT_LEN_WIDTH-1:0] m_axis_tx_status_finish_len, + output wire [QUEUE_INDEX_WIDTH-1:0] m_axis_tx_status_finish_queue, output wire [REQ_TAG_WIDTH-1:0] m_axis_tx_status_finish_tag, output wire m_axis_tx_status_finish_valid, @@ -327,15 +330,18 @@ tx_engine_inst ( */ .m_axis_tx_status_dequeue_empty(m_axis_tx_status_dequeue_empty), .m_axis_tx_status_dequeue_error(m_axis_tx_status_dequeue_error), + .m_axis_tx_status_dequeue_queue(m_axis_tx_status_dequeue_queue), .m_axis_tx_status_dequeue_tag(m_axis_tx_status_dequeue_tag), .m_axis_tx_status_dequeue_valid(m_axis_tx_status_dequeue_valid), .m_axis_tx_status_start_error(m_axis_tx_status_start_error), .m_axis_tx_status_start_len(m_axis_tx_status_start_len), + .m_axis_tx_status_start_queue(m_axis_tx_status_start_queue), .m_axis_tx_status_start_tag(m_axis_tx_status_start_tag), .m_axis_tx_status_start_valid(m_axis_tx_status_start_valid), .m_axis_tx_status_finish_len(m_axis_tx_status_finish_len), + .m_axis_tx_status_finish_queue(m_axis_tx_status_finish_queue), .m_axis_tx_status_finish_tag(m_axis_tx_status_finish_tag), .m_axis_tx_status_finish_valid(m_axis_tx_status_finish_valid), diff --git a/fpga/common/rtl/mqnic_tx_scheduler_block_rr.v b/fpga/common/rtl/mqnic_tx_scheduler_block_rr.v index c5049adab..2e4a19f62 100644 --- a/fpga/common/rtl/mqnic_tx_scheduler_block_rr.v +++ b/fpga/common/rtl/mqnic_tx_scheduler_block_rr.v @@ -114,15 +114,18 @@ module mqnic_tx_scheduler_block # */ input wire s_axis_tx_status_dequeue_empty, input wire s_axis_tx_status_dequeue_error, + input wire [QUEUE_INDEX_WIDTH-1:0] s_axis_tx_status_dequeue_queue, input wire [TX_REQ_TAG_WIDTH-1:0] s_axis_tx_status_dequeue_tag, input wire s_axis_tx_status_dequeue_valid, input wire s_axis_tx_status_start_error, input wire [DMA_LEN_WIDTH-1:0] s_axis_tx_status_start_len, + input wire [QUEUE_INDEX_WIDTH-1:0] s_axis_tx_status_start_queue, input wire [TX_REQ_TAG_WIDTH-1:0] s_axis_tx_status_start_tag, input wire s_axis_tx_status_start_valid, input wire [DMA_LEN_WIDTH-1:0] s_axis_tx_status_finish_len, + input wire [QUEUE_INDEX_WIDTH-1:0] s_axis_tx_status_finish_queue, input wire [TX_REQ_TAG_WIDTH-1:0] s_axis_tx_status_finish_tag, input wire s_axis_tx_status_finish_valid, @@ -279,15 +282,18 @@ tx_scheduler_inst ( */ .s_axis_tx_status_dequeue_empty(s_axis_tx_status_dequeue_empty), .s_axis_tx_status_dequeue_error(s_axis_tx_status_dequeue_error), + .s_axis_tx_status_dequeue_queue(s_axis_tx_status_dequeue_queue), .s_axis_tx_status_dequeue_tag(s_axis_tx_status_dequeue_tag), .s_axis_tx_status_dequeue_valid(s_axis_tx_status_dequeue_valid), .s_axis_tx_status_start_error(s_axis_tx_status_start_error), .s_axis_tx_status_start_len(s_axis_tx_status_start_len), + .s_axis_tx_status_start_queue(s_axis_tx_status_start_queue), .s_axis_tx_status_start_tag(s_axis_tx_status_start_tag), .s_axis_tx_status_start_valid(s_axis_tx_status_start_valid), .s_axis_tx_status_finish_len(s_axis_tx_status_finish_len), + .s_axis_tx_status_finish_queue(s_axis_tx_status_finish_queue), .s_axis_tx_status_finish_tag(s_axis_tx_status_finish_tag), .s_axis_tx_status_finish_valid(s_axis_tx_status_finish_valid), diff --git a/fpga/common/rtl/mqnic_tx_scheduler_block_rr_tdma.v b/fpga/common/rtl/mqnic_tx_scheduler_block_rr_tdma.v index f2b118ea8..3659ddecb 100644 --- a/fpga/common/rtl/mqnic_tx_scheduler_block_rr_tdma.v +++ b/fpga/common/rtl/mqnic_tx_scheduler_block_rr_tdma.v @@ -114,15 +114,18 @@ module mqnic_tx_scheduler_block # */ input wire s_axis_tx_status_dequeue_empty, input wire s_axis_tx_status_dequeue_error, + input wire [QUEUE_INDEX_WIDTH-1:0] s_axis_tx_status_dequeue_queue, input wire [TX_REQ_TAG_WIDTH-1:0] s_axis_tx_status_dequeue_tag, input wire s_axis_tx_status_dequeue_valid, input wire s_axis_tx_status_start_error, input wire [DMA_LEN_WIDTH-1:0] s_axis_tx_status_start_len, + input wire [QUEUE_INDEX_WIDTH-1:0] s_axis_tx_status_start_queue, input wire [TX_REQ_TAG_WIDTH-1:0] s_axis_tx_status_start_tag, input wire s_axis_tx_status_start_valid, input wire [DMA_LEN_WIDTH-1:0] s_axis_tx_status_finish_len, + input wire [QUEUE_INDEX_WIDTH-1:0] s_axis_tx_status_finish_queue, input wire [TX_REQ_TAG_WIDTH-1:0] s_axis_tx_status_finish_tag, input wire s_axis_tx_status_finish_valid, @@ -450,15 +453,18 @@ tx_scheduler_inst ( */ .s_axis_tx_status_dequeue_empty(s_axis_tx_status_dequeue_empty), .s_axis_tx_status_dequeue_error(s_axis_tx_status_dequeue_error), + .s_axis_tx_status_dequeue_queue(s_axis_tx_status_dequeue_queue), .s_axis_tx_status_dequeue_tag(s_axis_tx_status_dequeue_tag), .s_axis_tx_status_dequeue_valid(s_axis_tx_status_dequeue_valid), .s_axis_tx_status_start_error(s_axis_tx_status_start_error), .s_axis_tx_status_start_len(s_axis_tx_status_start_len), + .s_axis_tx_status_start_queue(s_axis_tx_status_start_queue), .s_axis_tx_status_start_tag(s_axis_tx_status_start_tag), .s_axis_tx_status_start_valid(s_axis_tx_status_start_valid), .s_axis_tx_status_finish_len(s_axis_tx_status_finish_len), + .s_axis_tx_status_finish_queue(s_axis_tx_status_finish_queue), .s_axis_tx_status_finish_tag(s_axis_tx_status_finish_tag), .s_axis_tx_status_finish_valid(s_axis_tx_status_finish_valid), diff --git a/fpga/common/rtl/tx_engine.v b/fpga/common/rtl/tx_engine.v index 221c56a34..796e126bd 100644 --- a/fpga/common/rtl/tx_engine.v +++ b/fpga/common/rtl/tx_engine.v @@ -97,15 +97,18 @@ module tx_engine # */ output wire m_axis_tx_status_dequeue_empty, output wire m_axis_tx_status_dequeue_error, + output wire [QUEUE_INDEX_WIDTH-1:0] m_axis_tx_status_dequeue_queue, output wire [REQ_TAG_WIDTH-1:0] m_axis_tx_status_dequeue_tag, output wire m_axis_tx_status_dequeue_valid, output wire m_axis_tx_status_start_error, output wire [DMA_CLIENT_LEN_WIDTH-1:0] m_axis_tx_status_start_len, + output wire [QUEUE_INDEX_WIDTH-1:0] m_axis_tx_status_start_queue, output wire [REQ_TAG_WIDTH-1:0] m_axis_tx_status_start_tag, output wire m_axis_tx_status_start_valid, output wire [DMA_CLIENT_LEN_WIDTH-1:0] m_axis_tx_status_finish_len, + output wire [QUEUE_INDEX_WIDTH-1:0] m_axis_tx_status_finish_queue, output wire [REQ_TAG_WIDTH-1:0] m_axis_tx_status_finish_tag, output wire m_axis_tx_status_finish_valid, @@ -270,15 +273,18 @@ reg s_axis_tx_req_ready_reg = 1'b0, s_axis_tx_req_ready_next; reg m_axis_tx_status_dequeue_empty_reg = 1'b0, m_axis_tx_status_dequeue_empty_next; reg m_axis_tx_status_dequeue_error_reg = 1'b0, m_axis_tx_status_dequeue_error_next; +reg [QUEUE_INDEX_WIDTH-1:0] m_axis_tx_status_dequeue_queue_reg = {QUEUE_INDEX_WIDTH{1'b0}}, m_axis_tx_status_dequeue_queue_next; reg [REQ_TAG_WIDTH-1:0] m_axis_tx_status_dequeue_tag_reg = {REQ_TAG_WIDTH{1'b0}}, m_axis_tx_status_dequeue_tag_next; reg m_axis_tx_status_dequeue_valid_reg = 1'b0, m_axis_tx_status_dequeue_valid_next; reg m_axis_tx_status_start_error_reg = 1'b0, m_axis_tx_status_start_error_next; reg [DMA_CLIENT_LEN_WIDTH-1:0] m_axis_tx_status_start_len_reg = {DMA_CLIENT_LEN_WIDTH{1'b0}}, m_axis_tx_status_start_len_next; +reg [QUEUE_INDEX_WIDTH-1:0] m_axis_tx_status_start_queue_reg = {QUEUE_INDEX_WIDTH{1'b0}}, m_axis_tx_status_start_queue_next; reg [REQ_TAG_WIDTH-1:0] m_axis_tx_status_start_tag_reg = {REQ_TAG_WIDTH{1'b0}}, m_axis_tx_status_start_tag_next; reg m_axis_tx_status_start_valid_reg = 1'b0, m_axis_tx_status_start_valid_next; reg [DMA_CLIENT_LEN_WIDTH-1:0] m_axis_tx_status_finish_len_reg = {DMA_CLIENT_LEN_WIDTH{1'b0}}, m_axis_tx_status_finish_len_next; +reg [QUEUE_INDEX_WIDTH-1:0] m_axis_tx_status_finish_queue_reg = {QUEUE_INDEX_WIDTH{1'b0}}, m_axis_tx_status_finish_queue_next; reg [REQ_TAG_WIDTH-1:0] m_axis_tx_status_finish_tag_reg = {REQ_TAG_WIDTH{1'b0}}, m_axis_tx_status_finish_tag_next; reg m_axis_tx_status_finish_valid_reg = 1'b0, m_axis_tx_status_finish_valid_next; @@ -409,15 +415,18 @@ assign s_axis_tx_req_ready = s_axis_tx_req_ready_reg; assign m_axis_tx_status_dequeue_empty = m_axis_tx_status_dequeue_empty_reg; assign m_axis_tx_status_dequeue_error = m_axis_tx_status_dequeue_error_reg; +assign m_axis_tx_status_dequeue_queue = m_axis_tx_status_dequeue_queue_reg; assign m_axis_tx_status_dequeue_tag = m_axis_tx_status_dequeue_tag_reg; assign m_axis_tx_status_dequeue_valid = m_axis_tx_status_dequeue_valid_reg; assign m_axis_tx_status_start_error = m_axis_tx_status_start_error_reg; assign m_axis_tx_status_start_len = m_axis_tx_status_start_len_reg; +assign m_axis_tx_status_start_queue = m_axis_tx_status_start_queue_reg; assign m_axis_tx_status_start_tag = m_axis_tx_status_start_tag_reg; assign m_axis_tx_status_start_valid = m_axis_tx_status_start_valid_reg; assign m_axis_tx_status_finish_len = m_axis_tx_status_finish_len_reg; +assign m_axis_tx_status_finish_queue = m_axis_tx_status_finish_queue_reg; assign m_axis_tx_status_finish_tag = m_axis_tx_status_finish_tag_reg; assign m_axis_tx_status_finish_valid = m_axis_tx_status_finish_valid_reg; @@ -559,15 +568,18 @@ always @* begin m_axis_tx_status_dequeue_empty_next = s_axis_desc_req_status_empty; m_axis_tx_status_dequeue_error_next = s_axis_desc_req_status_error; + m_axis_tx_status_dequeue_queue_next = desc_table_queue[s_axis_desc_req_status_tag & DESC_PTR_MASK]; m_axis_tx_status_dequeue_tag_next = desc_table_tag[s_axis_desc_req_status_tag & DESC_PTR_MASK]; m_axis_tx_status_dequeue_valid_next = 1'b0; m_axis_tx_status_start_error_next = 1'b0; m_axis_tx_status_start_len_next = desc_len_next; + m_axis_tx_status_start_queue_next = desc_table_queue[s_axis_desc_tid & DESC_PTR_MASK]; m_axis_tx_status_start_tag_next = desc_table_tag[s_axis_desc_tid & DESC_PTR_MASK]; m_axis_tx_status_start_valid_next = 1'b0; m_axis_tx_status_finish_len_next = desc_table_len[desc_table_finish_ptr_reg & DESC_PTR_MASK]; + m_axis_tx_status_finish_queue_next = desc_table_queue[desc_table_finish_ptr_reg & DESC_PTR_MASK]; m_axis_tx_status_finish_tag_next = desc_table_tag[desc_table_finish_ptr_reg & DESC_PTR_MASK]; m_axis_tx_status_finish_valid_next = 1'b0; @@ -688,6 +700,7 @@ always @* begin // return dequeue status m_axis_tx_status_dequeue_empty_next = s_axis_desc_req_status_empty; m_axis_tx_status_dequeue_error_next = s_axis_desc_req_status_error; + m_axis_tx_status_dequeue_queue_next = desc_table_queue[s_axis_desc_req_status_tag & DESC_PTR_MASK]; m_axis_tx_status_dequeue_tag_next = desc_table_tag[s_axis_desc_req_status_tag & DESC_PTR_MASK]; m_axis_tx_status_dequeue_valid_next = 1'b1; @@ -746,6 +759,7 @@ always @* begin m_axis_tx_status_start_error_next = 1'b0; m_axis_tx_status_start_len_next = desc_len_next; + m_axis_tx_status_start_queue_next = desc_table_queue[s_axis_desc_tid & DESC_PTR_MASK]; m_axis_tx_status_start_tag_next = desc_table_tag[s_axis_desc_tid & DESC_PTR_MASK]; if (s_axis_desc_tlast) begin @@ -886,6 +900,7 @@ always @* begin // return transmit finish status m_axis_tx_status_finish_len_next = desc_table_len[desc_table_finish_ptr_reg & DESC_PTR_MASK]; + m_axis_tx_status_finish_queue_next = desc_table_queue[desc_table_finish_ptr_reg & DESC_PTR_MASK]; m_axis_tx_status_finish_tag_next = desc_table_tag[desc_table_finish_ptr_reg & DESC_PTR_MASK]; m_axis_tx_status_finish_valid_next = 1'b1; end @@ -898,15 +913,18 @@ always @(posedge clk) begin m_axis_tx_status_dequeue_empty_reg <= m_axis_tx_status_dequeue_empty_next; m_axis_tx_status_dequeue_error_reg <= m_axis_tx_status_dequeue_error_next; m_axis_tx_status_dequeue_tag_reg <= m_axis_tx_status_dequeue_tag_next; + m_axis_tx_status_dequeue_queue_reg <= m_axis_tx_status_dequeue_queue_next; m_axis_tx_status_dequeue_valid_reg <= m_axis_tx_status_dequeue_valid_next; m_axis_tx_status_start_error_reg <= m_axis_tx_status_start_error_next; m_axis_tx_status_start_len_reg <= m_axis_tx_status_start_len_next; m_axis_tx_status_start_tag_reg <= m_axis_tx_status_start_tag_next; + m_axis_tx_status_start_queue_reg <= m_axis_tx_status_start_queue_next; m_axis_tx_status_start_valid_reg <= m_axis_tx_status_start_valid_next; m_axis_tx_status_finish_len_reg <= m_axis_tx_status_finish_len_next; m_axis_tx_status_finish_tag_reg <= m_axis_tx_status_finish_tag_next; + m_axis_tx_status_finish_queue_reg <= m_axis_tx_status_finish_queue_next; m_axis_tx_status_finish_valid_reg <= m_axis_tx_status_finish_valid_next; m_axis_desc_req_queue_reg <= m_axis_desc_req_queue_next; diff --git a/fpga/common/rtl/tx_req_mux.v b/fpga/common/rtl/tx_req_mux.v index 95fce0682..e0cb11e8a 100644 --- a/fpga/common/rtl/tx_req_mux.v +++ b/fpga/common/rtl/tx_req_mux.v @@ -50,15 +50,18 @@ module tx_req_mux # */ input wire s_axis_status_dequeue_empty, input wire s_axis_status_dequeue_error, + input wire [QUEUE_INDEX_WIDTH-1:0] s_axis_status_dequeue_queue, input wire [M_REQ_TAG_WIDTH-1:0] s_axis_status_dequeue_tag, input wire s_axis_status_dequeue_valid, input wire s_axis_status_start_error, input wire [LEN_WIDTH-1:0] s_axis_status_start_len, + input wire [QUEUE_INDEX_WIDTH-1:0] s_axis_status_start_queue, input wire [M_REQ_TAG_WIDTH-1:0] s_axis_status_start_tag, input wire s_axis_status_start_valid, input wire [LEN_WIDTH-1:0] s_axis_status_finish_len, + input wire [QUEUE_INDEX_WIDTH-1:0] s_axis_status_finish_queue, input wire [M_REQ_TAG_WIDTH-1:0] s_axis_status_finish_tag, input wire s_axis_status_finish_valid, @@ -76,15 +79,18 @@ module tx_req_mux # */ output wire [PORTS-1:0] m_axis_status_dequeue_empty, output wire [PORTS-1:0] m_axis_status_dequeue_error, + output wire [PORTS*QUEUE_INDEX_WIDTH-1:0] m_axis_status_dequeue_queue, output wire [PORTS*S_REQ_TAG_WIDTH-1:0] m_axis_status_dequeue_tag, output wire [PORTS-1:0] m_axis_status_dequeue_valid, output wire [PORTS-1:0] m_axis_status_start_error, output wire [PORTS*LEN_WIDTH-1:0] m_axis_status_start_len, + output wire [PORTS*QUEUE_INDEX_WIDTH-1:0] m_axis_status_start_queue, output wire [PORTS*S_REQ_TAG_WIDTH-1:0] m_axis_status_start_tag, output wire [PORTS-1:0] m_axis_status_start_valid, output wire [PORTS*LEN_WIDTH-1:0] m_axis_status_finish_len, + output wire [PORTS*QUEUE_INDEX_WIDTH-1:0] m_axis_status_finish_queue, output wire [PORTS*S_REQ_TAG_WIDTH-1:0] m_axis_status_finish_tag, output wire [PORTS-1:0] m_axis_status_finish_valid ); @@ -260,44 +266,53 @@ end // request status demux reg m_axis_status_dequeue_empty_reg = 1'b0; reg m_axis_status_dequeue_error_reg = 1'b0; +reg [QUEUE_INDEX_WIDTH-1:0] m_axis_status_dequeue_queue_reg = {QUEUE_INDEX_WIDTH{1'b0}}; reg [S_REQ_TAG_WIDTH-1:0] m_axis_status_dequeue_tag_reg = {S_REQ_TAG_WIDTH{1'b0}}; reg [PORTS-1:0] m_axis_status_dequeue_valid_reg = {PORTS{1'b0}}; reg m_axis_status_start_error_reg = 1'b0; reg [LEN_WIDTH-1:0] m_axis_status_start_len_reg = {LEN_WIDTH{1'b0}}; +reg [QUEUE_INDEX_WIDTH-1:0] m_axis_status_start_queue_reg = {QUEUE_INDEX_WIDTH{1'b0}}; reg [S_REQ_TAG_WIDTH-1:0] m_axis_status_start_tag_reg = {S_REQ_TAG_WIDTH{1'b0}}; reg [PORTS-1:0] m_axis_status_start_valid_reg = {PORTS{1'b0}}; reg [LEN_WIDTH-1:0] m_axis_status_finish_len_reg = {LEN_WIDTH{1'b0}}; +reg [QUEUE_INDEX_WIDTH-1:0] m_axis_status_finish_queue_reg = {QUEUE_INDEX_WIDTH{1'b0}}; reg [S_REQ_TAG_WIDTH-1:0] m_axis_status_finish_tag_reg = {S_REQ_TAG_WIDTH{1'b0}}; reg [PORTS-1:0] m_axis_status_finish_valid_reg = {PORTS{1'b0}}; assign m_axis_status_dequeue_empty = {PORTS{m_axis_status_dequeue_empty_reg}}; assign m_axis_status_dequeue_error = {PORTS{m_axis_status_dequeue_error_reg}}; +assign m_axis_status_dequeue_queue = {PORTS{m_axis_status_dequeue_queue_reg}}; assign m_axis_status_dequeue_tag = {PORTS{m_axis_status_dequeue_tag_reg}}; assign m_axis_status_dequeue_valid = m_axis_status_dequeue_valid_reg; assign m_axis_status_start_error = {PORTS{m_axis_status_start_error_reg}}; assign m_axis_status_start_len = {PORTS{m_axis_status_start_len_reg}}; +assign m_axis_status_start_queue = {PORTS{m_axis_status_start_queue_reg}}; assign m_axis_status_start_tag = {PORTS{m_axis_status_start_tag_reg}}; assign m_axis_status_start_valid = m_axis_status_start_valid_reg; assign m_axis_status_finish_len = {PORTS{m_axis_status_finish_len_reg}}; +assign m_axis_status_finish_queue = {PORTS{m_axis_status_finish_queue_reg}}; assign m_axis_status_finish_tag = {PORTS{m_axis_status_finish_tag_reg}}; assign m_axis_status_finish_valid = m_axis_status_finish_valid_reg; always @(posedge clk) begin m_axis_status_dequeue_empty_reg <= s_axis_status_dequeue_empty; m_axis_status_dequeue_error_reg <= s_axis_status_dequeue_error; + m_axis_status_dequeue_queue_reg <= s_axis_status_dequeue_queue; m_axis_status_dequeue_tag_reg <= s_axis_status_dequeue_tag; m_axis_status_dequeue_valid_reg <= s_axis_status_dequeue_valid << (PORTS > 1 ? (s_axis_status_dequeue_tag >> S_REQ_TAG_WIDTH) : 0); m_axis_status_start_error_reg <= s_axis_status_start_error; m_axis_status_start_len_reg <= s_axis_status_start_len; + m_axis_status_start_queue_reg <= s_axis_status_start_queue; m_axis_status_start_tag_reg <= s_axis_status_start_tag; m_axis_status_start_valid_reg <= s_axis_status_start_valid << (PORTS > 1 ? (s_axis_status_start_tag >> S_REQ_TAG_WIDTH) : 0); m_axis_status_finish_len_reg <= s_axis_status_finish_len; + m_axis_status_finish_queue_reg <= s_axis_status_finish_queue; m_axis_status_finish_tag_reg <= s_axis_status_finish_tag; m_axis_status_finish_valid_reg <= s_axis_status_finish_valid << (PORTS > 1 ? (s_axis_status_finish_tag >> S_REQ_TAG_WIDTH) : 0); diff --git a/fpga/common/rtl/tx_scheduler_rr.v b/fpga/common/rtl/tx_scheduler_rr.v index 0d827e5ce..c2649c576 100644 --- a/fpga/common/rtl/tx_scheduler_rr.v +++ b/fpga/common/rtl/tx_scheduler_rr.v @@ -73,15 +73,18 @@ module tx_scheduler_rr # */ input wire s_axis_tx_status_dequeue_empty, input wire s_axis_tx_status_dequeue_error, + input wire [QUEUE_INDEX_WIDTH-1:0] s_axis_tx_status_dequeue_queue, input wire [REQ_TAG_WIDTH-1:0] s_axis_tx_status_dequeue_tag, input wire s_axis_tx_status_dequeue_valid, input wire s_axis_tx_status_start_error, input wire [LEN_WIDTH-1:0] s_axis_tx_status_start_len, + input wire [QUEUE_INDEX_WIDTH-1:0] s_axis_tx_status_start_queue, input wire [REQ_TAG_WIDTH-1:0] s_axis_tx_status_start_tag, input wire s_axis_tx_status_start_valid, input wire [LEN_WIDTH-1:0] s_axis_tx_status_finish_len, + input wire [QUEUE_INDEX_WIDTH-1:0] s_axis_tx_status_finish_queue, input wire [REQ_TAG_WIDTH-1:0] s_axis_tx_status_finish_tag, input wire s_axis_tx_status_finish_valid, diff --git a/fpga/common/tb/tx_scheduler_rr/test_tx_scheduler_rr.py b/fpga/common/tb/tx_scheduler_rr/test_tx_scheduler_rr.py index 22d43fe35..a41cfbb7c 100644 --- a/fpga/common/tb/tx_scheduler_rr/test_tx_scheduler_rr.py +++ b/fpga/common/tb/tx_scheduler_rr/test_tx_scheduler_rr.py @@ -24,7 +24,7 @@ TxStatusBus, TxStatusTransaction, TxStatusSource, TxStatusSink, TxStatusMonitor = define_stream("TxStatus", - signals=["tag", "valid"], + signals=["queue", "tag", "valid"], optional_signals=["empty", "error", "len", "ready"] ) @@ -193,7 +193,7 @@ async def run_test_single(dut, idle_inserter=None, backpressure_inserter=None): assert tx_req.queue == 0 - status = TxStatusTransaction(empty=0, error=0, len=1000, tag=tx_req.tag) + status = TxStatusTransaction(empty=0, error=0, len=1000, queue=tx_req.queue, tag=tx_req.tag) tb.log.info("TX status: %s", status) await tb.tx_status_dequeue_source.send(status) await tb.tx_status_start_source.send(status) @@ -204,7 +204,7 @@ async def run_test_single(dut, idle_inserter=None, backpressure_inserter=None): assert tx_req.queue == 0 - status = TxStatusTransaction(empty=1, error=0, len=0, tag=tx_req.tag) + status = TxStatusTransaction(empty=1, error=0, len=0, queue=tx_req.queue, tag=tx_req.tag) tb.log.info("TX status: %s", status) await tb.tx_status_dequeue_source.send(status) @@ -217,7 +217,7 @@ async def run_test_single(dut, idle_inserter=None, backpressure_inserter=None): assert tx_req.queue == 0 - status = TxStatusTransaction(empty=1, error=0, len=0, tag=tx_req.tag) + status = TxStatusTransaction(empty=1, error=0, len=0, queue=tx_req.queue, tag=tx_req.tag) tb.log.info("TX status: %s", status) await tb.tx_status_dequeue_source.send(status) @@ -260,7 +260,7 @@ async def run_test_multiple(dut, idle_inserter=None, backpressure_inserter=None) assert tx_req.queue == k % 10 - status = TxStatusTransaction(empty=0, error=0, len=1000, tag=tx_req.tag) + status = TxStatusTransaction(empty=0, error=0, len=1000, queue=tx_req.queue, tag=tx_req.tag) tb.log.info("TX status: %s", status) await tb.tx_status_dequeue_source.send(status) await tb.tx_status_start_source.send(status) @@ -270,7 +270,7 @@ async def run_test_multiple(dut, idle_inserter=None, backpressure_inserter=None) tx_req = await tb.tx_req_sink.recv() tb.log.info("TX request: %s", tx_req) - status = TxStatusTransaction(empty=1, error=0, len=0, tag=tx_req.tag) + status = TxStatusTransaction(empty=1, error=0, len=0, queue=tx_req.queue, tag=tx_req.tag) tb.log.info("TX status: %s", status) await tb.tx_status_dequeue_source.send(status) @@ -281,7 +281,7 @@ async def run_test_multiple(dut, idle_inserter=None, backpressure_inserter=None) tx_req = await tb.tx_req_sink.recv() tb.log.info("TX request: %s", tx_req) - status = TxStatusTransaction(empty=1, error=0, len=0, tag=tx_req.tag) + status = TxStatusTransaction(empty=1, error=0, len=0, queue=tx_req.queue, tag=tx_req.tag) tb.log.info("TX status: %s", status) await tb.tx_status_dequeue_source.send(status) @@ -319,7 +319,7 @@ async def run_test_doorbell(dut, idle_inserter=None, backpressure_inserter=None) assert tx_req.queue == 0 - status = TxStatusTransaction(empty=0, error=0, len=1000, tag=tx_req.tag) + status = TxStatusTransaction(empty=0, error=0, len=1000, queue=tx_req.queue, tag=tx_req.tag) tb.log.info("TX status: %s", status) await tb.tx_status_dequeue_source.send(status) await tb.tx_status_start_source.send(status) @@ -333,7 +333,7 @@ async def run_test_doorbell(dut, idle_inserter=None, backpressure_inserter=None) assert tx_req.queue == 0 - status = TxStatusTransaction(empty=1, error=0, len=0, tag=tx_req.tag) + status = TxStatusTransaction(empty=1, error=0, len=0, queue=tx_req.queue, tag=tx_req.tag) tb.log.info("TX status: %s", status) await tb.tx_status_dequeue_source.send(status) @@ -344,7 +344,7 @@ async def run_test_doorbell(dut, idle_inserter=None, backpressure_inserter=None) assert tx_req.queue == 0 - status = TxStatusTransaction(empty=1, error=0, len=0, tag=tx_req.tag) + status = TxStatusTransaction(empty=1, error=0, len=0, queue=tx_req.queue, tag=tx_req.tag) tb.log.info("TX status: %s", status) await tb.tx_status_dequeue_source.send(status) @@ -353,7 +353,7 @@ async def run_test_doorbell(dut, idle_inserter=None, backpressure_inserter=None) assert tx_req.queue == 0 - status = TxStatusTransaction(empty=1, error=0, len=0, tag=tx_req.tag) + status = TxStatusTransaction(empty=1, error=0, len=0, queue=tx_req.queue, tag=tx_req.tag) tb.log.info("TX status: %s", status) await tb.tx_status_dequeue_source.send(status) @@ -363,7 +363,7 @@ async def run_test_doorbell(dut, idle_inserter=None, backpressure_inserter=None) assert tx_req.queue == 0 - status = TxStatusTransaction(empty=0, error=0, len=1000, tag=tx_req.tag) + status = TxStatusTransaction(empty=0, error=0, len=1000, queue=tx_req.queue, tag=tx_req.tag) tb.log.info("TX status: %s", status) await tb.tx_status_dequeue_source.send(status) await tb.tx_status_start_source.send(status) @@ -377,7 +377,7 @@ async def run_test_doorbell(dut, idle_inserter=None, backpressure_inserter=None) assert tx_req.queue == 0 - status = TxStatusTransaction(empty=1, error=0, len=0, tag=tx_req.tag) + status = TxStatusTransaction(empty=1, error=0, len=0, queue=tx_req.queue, tag=tx_req.tag) tb.log.info("TX status: %s", status) await tb.tx_status_dequeue_source.send(status) @@ -390,7 +390,7 @@ async def run_test_doorbell(dut, idle_inserter=None, backpressure_inserter=None) assert tx_req.queue == 0 - status = TxStatusTransaction(empty=1, error=0, len=0, tag=tx_req.tag) + status = TxStatusTransaction(empty=1, error=0, len=0, queue=tx_req.queue, tag=tx_req.tag) tb.log.info("TX status: %s", status) await tb.tx_status_dequeue_source.send(status)