diff --git a/e2e/Makefile b/e2e/Makefile
index 6b2a2fa09..9c547110e 100644
--- a/e2e/Makefile
+++ b/e2e/Makefile
@@ -43,3 +43,6 @@ $(HAMMER_D_MK):
 	hammer-vlsi --obj_dir $(OBJ_DIR) -e $(ENV_YML) $(HAMMER_EXTRA_ARGS) build
 
 -include $(HAMMER_D_MK)
+
+clean:
+    rm -rf $(OBJ_DIR) hammer-vlsi-*.log
diff --git a/hammer/synthesis/genus/__init__.py b/hammer/synthesis/genus/__init__.py
index 558a08729..9caec5386 100644
--- a/hammer/synthesis/genus/__init__.py
+++ b/hammer/synthesis/genus/__init__.py
@@ -224,7 +224,7 @@ def init_environment(self) -> bool:
         ))
 
         # Load input files and check that they are all Verilog.
-        if not self.check_input_files([".v", ".sv"]):
+        if not self.check_input_files([".v", ".sv", "vh"]):
             return False
         # We are switching working directories and Genus still needs to find paths.
         abspath_input_files = list(map(lambda name: os.path.join(os.getcwd(), name), self.input_files))  # type: List[str]