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A recent feature was added to enable L1 sharded tensors to be sharded across custom core lists/ranges. This issue tracks the enablement of that feature in sharded addrgen, which is used by CCL operations.
sharded addrgens can be found here: ttnn/cpp/ttnn/operations/ccl/shared_with_host/sharded_tensor_addr_gen.hpp
To support this feature mainly three changes will be needed:
A new WorkerToNocCoordLookup will need to be implemented (e.g. ArbitraryShardCoreListCoordLookup)
Please add corresponding tests to tests/ttnn/unit_tests/gtests/ccl/test_ccl_tensor_slicers.cpp - should also simplify initial bringup and testing
kernel side: the kernel will need to have a different codepath for instantiating this new type of coord lookup - based off of a new CT arg we pass in
Runtime args will accordingly need to be interpreted in a different way
Luckily we are already consuming RT args for coord lookup today for harvesting, so the general type of codepath already exists
Update RT/CT arg generators: emit_address_generator_runtime_args for this mode (to be detected from the mem config)
A recent feature was added to enable L1 sharded tensors to be sharded across custom core lists/ranges. This issue tracks the enablement of that feature in sharded addrgen, which is used by CCL operations.
sharded addrgens can be found here:
ttnn/cpp/ttnn/operations/ccl/shared_with_host/sharded_tensor_addr_gen.hpp
To support this feature mainly three changes will be needed:
WorkerToNocCoordLookup
will need to be implemented (e.g. ArbitraryShardCoreListCoordLookup)tests/ttnn/unit_tests/gtests/ccl/test_ccl_tensor_slicers.cpp
- should also simplify initial bringup and testingemit_address_generator_runtime_args
for this mode (to be detected from the mem config)The text was updated successfully, but these errors were encountered: