[F133/D1s uboot] Does smaeul/u-boot support F133/D1s?

[xiaguangbo]

Is there a configuration available？
I used the 'd1-wip' branch and tried to imitate defconfig, but it was all problematic

U-Boot SPL 2024.01-rc1-45338-g2e89b706f5-dirty (Jul 10 2024 - 16:53:42 +0800)
size=30, ptr=11b0, limit=4000: 41180
size=98, ptr=1248, limit=4000: 411b0
size=18, ptr=1260, limit=4000: 41248
ofnode_read_u32_array: ranges: fdtdec_get_int_array: ranges
get_prop_check_min_len: ranges
bind node cpu@0
   - attempt to match compatible string 'thead,c906'
   - attempt to match compatible string 'riscv'
   - found match at 'riscv_cpu': 'riscv' matches 'riscv'
size=98, ptr=12f8, limit=4000: 41260
size=20, ptr=1318, limit=4000: 412f8
fdtdec_get_addr_size_auto_parent: na=1, ns=0, fdtdec_get_addr_size_fixed: reg: adx
ofnode_read_u32_index: timebase-frequency: (not found)
ofnode_read_u32_index: timebase-frequency: x (24000000)
size=30, ptr=1348, limit=4000: 41318
size=98, ptr=13e0, limit=4000: 41348
clk_set_defaults(cpus)
clk_set_default_parents: could not read assigned-clock-parents for 411b0
ofnode_read_prop: assigned-clock-rates: <not found>
clk_set_defaults(cpu@0)
clk_set_default_parents: could not read assigned-clock-parents for 41260
ofnode_read_prop: assigned-clock-rates: <not found>
fdtdec_get_int: #clock-cells: x (1)
Looking for clock-controller@2001000
Looking for clock-controller@2001000
   - result for clock-controller@2001000: clock-controller@2001000 (ret=0)
   - result for clock-controller@2001000: clock-controller@2001000 (ret=0)
clk_of_xlate_default(clk=47f28)
clk_request(dev=40968, clk=47f28)
clk_enable(clk=47f28)
sunxi_set_gate: (CLK#132) off#0xd04, BIT(31)om 2.9 | VT102 | 脱机 | ttyUSB0       
clk_free(clk=47f28)
size=8, ptr=13e8, limit=4000: 413e0
clk_set_defaults(dram-controller@3102000)
clk_set_default_parents: could not read assigned-clock-parents for 40bf8
ofnode_read_prop: assigned-clock-rates: <not found>
sunxi_ram_probe: dram-controller@3102000: probing
DRAM BOOT DRIVE INFO: V0.24
DRAM CLK = 528 MHz
DRAM Type = 2 (2:DDR2,3:DDR3)
DRAMC read ODT off
ofnode_read_prop: tick-timer: <not found>
size=8, ptr=13f0, limit=4000: 413e8
ZQ value = 0x2f
DDR efuse: 0xa
DX0 state: 3
DX1 state: 0
ERROR: auto scan dram rank & width failed
auto_scan_dram_config() FAILED
DRAM init failed
spl_board_init_f() failed: -19

resetting ...
reset not supported yet
### ERROR ### Please RESET the board ###