From caf8b39aa1b9807056be780a4511ba80303df1da Mon Sep 17 00:00:00 2001 From: Curtis Millar Date: Wed, 10 Mar 2021 10:51:37 +1100 Subject: [PATCH 1/8] WIP: IMX.8 MAC address The IMX.6 ethernet driver is compatible with the IMX.8 but our implementation assumes the IMX.6 OCOTP which stores the MAC address at boot and is not compatible with the IMX.8. It's also possible that the ethernet device already has the register initialised by the bootloader already at this point... Signed-off-by: Curtis Millar Signed-off-by: Lucy --- libethdrivers/src/plat/imx6/imx6.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/libethdrivers/src/plat/imx6/imx6.c b/libethdrivers/src/plat/imx6/imx6.c index 9cd257fe4..3c62064b3 100644 --- a/libethdrivers/src/plat/imx6/imx6.c +++ b/libethdrivers/src/plat/imx6/imx6.c @@ -23,6 +23,9 @@ #include "uboot/micrel.h" #include "unimplemented.h" +// Temporary fix: set to imx8mq mac +#define DEFAULT_MAC "\x00\x04\x9f\x05\x93\xdf" + #define IRQ_MASK (NETIRQ_RXF | NETIRQ_TXF | NETIRQ_EBERR) #define BUF_SIZE MAX_PKT_SIZE #define DMA_ALIGN 32 From 11b5a0720b4a31941270481e95dd94fb7fa70d2a Mon Sep 17 00:00:00 2001 From: Curtis Millar Date: Tue, 10 Aug 2021 10:37:09 +1000 Subject: [PATCH 2/8] WIP: Temporary fixes Signed-off-by: Lucy --- libethdrivers/src/plat/imx6/enet.c | 4 + libethdrivers/src/plat/imx6/imx6.c | 14 +- libethdrivers/src/plat/imx6/uboot/imx-regs.h | 778 +------------------ 3 files changed, 18 insertions(+), 778 deletions(-) diff --git a/libethdrivers/src/plat/imx6/enet.c b/libethdrivers/src/plat/imx6/enet.c index 1dc1f98a6..1bfe7c448 100644 --- a/libethdrivers/src/plat/imx6/enet.c +++ b/libethdrivers/src/plat/imx6/enet.c @@ -606,8 +606,12 @@ struct enet *enet_init(void *mapped_peripheral, uintptr_t tx_phys, regs->gaur = 0; regs->galr = 0; +#ifndef CONFIG_PLAT_IMX8MQ_EVK + /* For iMX.8 we assume that the bootloader has already correctly + * configured the MAC address */ /* Set MAC and pause frame type field */ enet_set_mac(enet, mac); +#endif /* Configure pause frames (continues into MAC registers...) */ regs->opd = PAUSE_OPCODE_FIELD << 16; diff --git a/libethdrivers/src/plat/imx6/imx6.c b/libethdrivers/src/plat/imx6/imx6.c index 3c62064b3..8fa2bce6e 100644 --- a/libethdrivers/src/plat/imx6/imx6.c +++ b/libethdrivers/src/plat/imx6/imx6.c @@ -639,6 +639,17 @@ static int init_device(imx6_eth_driver_t *dev, const nic_config_t *nic_config) int ret; +#ifdef CONFIG_PLAT_IMX8MQ_EVK + /* Don't attempt to obtain the MAC address for iMX8. + * + * The code to obtain the MAC address assumes an iMX6 compatible + * OCOTP which the iMX8 does not have. + * + * Instead, we assume that the bootloader has already configured the + * hardware MAC address. */ + uint64_t mac = 0; + ZF_LOGI("using MAC configured by bootloader"); +#else uint64_t mac = obtain_mac(nic_config, &(dev->eth_drv.io_ops.io_mapper)); if (0 == mac) { ZF_LOGE("Failed to obtain a MAC"); @@ -652,6 +663,7 @@ static int init_device(imx6_eth_driver_t *dev, const nic_config_t *nic_config) (uint8_t)(mac >> 16), (uint8_t)(mac >> 8), (uint8_t)(mac)); +#endif ret = setup_desc_ring(dev, &(dev->rx)); if (ret) { @@ -739,7 +751,7 @@ static int init_device(imx6_eth_driver_t *dev, const nic_config_t *nic_config) /* Initialise the phy library */ miiphy_init(); /* Initialise the phy */ -#if defined(CONFIG_PLAT_SABRE) || defined(CONFIG_PLAT_WANDQ) +#if defined(CONFIG_PLAT_SABRE) || defined(CONFIG_PLAT_WANDQ) || defined(CONFIG_PLAT_IMX8MQ_EVK) phy_micrel_init(); #elif defined(CONFIG_PLAT_NITROGEN6SX) phy_atheros_init(); diff --git a/libethdrivers/src/plat/imx6/uboot/imx-regs.h b/libethdrivers/src/plat/imx6/uboot/imx-regs.h index e395cdcef..3effd8225 100644 --- a/libethdrivers/src/plat/imx6/uboot/imx-regs.h +++ b/libethdrivers/src/plat/imx6/uboot/imx-regs.h @@ -30,200 +30,10 @@ #define CONFIG_SYS_CACHELINE_SIZE 32 -#define ROMCP_ARB_BASE_ADDR 0x00000000 -#define ROMCP_ARB_END_ADDR 0x000FFFFF - - -#if defined(CONFIG_PLAT_IMX6DQ) - -#define CAAM_ARB_BASE_ADDR 0x00100000 -#define CAAM_ARB_END_ADDR 0x00103FFF -#define APBH_DMA_ARB_BASE_ADDR 0x00110000 -#define APBH_DMA_ARB_END_ADDR 0x00117FFF -#define HDMI_ARB_BASE_ADDR 0x00120000 -#define HDMI_ARB_END_ADDR 0x00128FFF -#define GPU_3D_ARB_BASE_ADDR 0x00130000 -#define GPU_3D_ARB_END_ADDR 0x00133FFF -#define GPU_2D_ARB_BASE_ADDR 0x00134000 -#define GPU_2D_ARB_END_ADDR 0x00137FFF -#define DTCP_ARB_BASE_ADDR 0x00138000 -#define DTCP_ARB_END_ADDR 0x0013BFFF - -#elif defined(CONFIG_PLAT_IMX6SX) - -#define CAAM_ARB_BASE_ADDR 0x00100000 -#define CAAM_ARB_END_ADDR 0x00107FFF -#define GPU_ARB_BASE_ADDR 0x01800000 -#define GPU_ARB_END_ADDR 0x01803FFF -#define APBH_DMA_ARB_BASE_ADDR 0x01804000 -#define APBH_DMA_ARB_END_ADDR 0x0180BFFF -#define M4_BOOTROM_BASE_ADDR 0x007F8000 - -#else -#error "unknown i.MX6 SOC" -#endif - - -#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR -#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000) -#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000) - -/* GPV - PL301 configuration ports */ - -#if defined(CONFIG_PLAT_IMX6DQ) - -#define GPV2_BASE_ADDR 0x00200000 -#define GPV3_BASE_ADDR 0x00300000 -#define GPV4_BASE_ADDR 0x00800000 - -#elif defined(CONFIG_PLAT_IMX6SX) - -#define GPV2_BASE_ADDR 0x00D00000 -#define GPV3_BASE_ADDR 0x00E00000 -#define GPV4_BASE_ADDR 0x00F00000 -#define GPV5_BASE_ADDR 0x01000000 -#define GPV6_BASE_ADDR 0x01100000 - -#else -#error "unknown i.MX6 SOC" -#endif - - -#define IRAM_BASE_ADDR 0x00900000 - -#if defined(CONFIG_PLAT_IMX6DQ) -#define IRAM_SIZE 0x00020000 -#elif defined(CONFIG_PLAT_IMX6SX) -#define IRAM_SIZE 0x00040000 -#else -#error "unknown i.MX6 SOC" -#endif - - -#define SCU_BASE_ADDR 0x00A00000 -#define IC_INTERFACES_BASE_ADDR 0x00A00100 -#define GLOBAL_TIMER_BASE_ADDR 0x00A00200 -#define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600 -#define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000 -#define L2_PL310_BASE 0x00A02000 -#define GPV0_BASE_ADDR 0x00B00000 -#define GPV1_BASE_ADDR 0x00C00000 - - -#if defined(CONFIG_PLAT_IMX6DQ) - -#define PCIE_ARB_BASE_ADDR 0x01000000 -#define PCIE_ARB_END_ADDR 0x01FFFFFF - -#elif defined(CONFIG_PLAT_IMX6SX) - -#define PCIE_ARB_BASE_ADDR 0x08000000 -#define PCIE_ARB_END_ADDR 0x08FFFFFF - -#else -#error "unknown i.MX6 SOC" -#endif - - -#define AIPS1_ARB_BASE_ADDR 0x02000000 -#define AIPS1_ARB_END_ADDR 0x020FFFFF -#define AIPS2_ARB_BASE_ADDR 0x02100000 -#define AIPS2_ARB_END_ADDR 0x021FFFFF - -#if defined(CONFIG_PLAT_IMX6SX) -/* AIPS3 exists on i.MX6SX */ -#define AIPS3_ARB_BASE_ADDR 0x02200000 -#define AIPS3_ARB_END_ADDR 0x022FFFFF -#endif - - -#if defined(CONFIG_PLAT_IMX6DQ) - -#define SATA_ARB_BASE_ADDR 0x02200000 -#define SATA_ARB_END_ADDR 0x02203FFF -#define OPENVG_ARB_BASE_ADDR 0x02204000 -#define OPENVG_ARB_END_ADDR 0x02207FFF -#define HSI_ARB_BASE_ADDR 0x02208000 -#define HSI_ARB_END_ADDR 0x0220BFFF -#define IPU1_ARB_BASE_ADDR 0x02400000 -#define IPU1_ARB_END_ADDR 0x027FFFFF -#define IPU2_ARB_BASE_ADDR 0x02800000 -#define IPU2_ARB_END_ADDR 0x02BFFFFF -#define WEIM_ARB_BASE_ADDR 0x08000000 -#define WEIM_ARB_END_ADDR 0x0FFFFFFF - -#define MMDC0_ARB_BASE_ADDR 0x10000000 -#define MMDC0_ARB_END_ADDR 0x7FFFFFFF -#define MMDC1_ARB_BASE_ADDR 0x80000000 -#define MMDC1_ARB_END_ADDR 0xFFFFFFFF - -#define IPU_SOC_BASE_ADDR IPU1_ARB_BASE_ADDR -#define IPU_SOC_OFFSET 0x00200000 - -#elif defined(CONFIG_PLAT_IMX6SX) - -#define WEIM_ARB_BASE_ADDR 0x50000000 -#define WEIM_ARB_END_ADDR 0x57FFFFFF -#define QSPI0_AMBA_BASE 0x60000000 -#define QSPI0_AMBA_END 0x6FFFFFFF -#define QSPI1_AMBA_BASE 0x70000000 -#define QSPI1_AMBA_END 0x7FFFFFFF -#define MMDC0_ARB_BASE_ADDR 0x80000000 -#define MMDC0_ARB_END_ADDR 0xBFFFFFFF -#define MMDC1_ARB_BASE_ADDR 0xC0000000 -#define MMDC1_ARB_END_ADDR 0xFFFFFFFF - -#else -#error "unknown i.MX6 SOC" -#endif - -/* Defines for Blocks connected via AIPS (SkyBlue) */ +#define AIPS1_ARB_BASE_ADDR 0x02000000 #define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR -#define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR -#if defined(CONFIG_PLAT_IMX6SX) -/* ATZ3/AIPS3 exists on i.MX6SX */ -#define ATZ3_BASE_ADDR AIPS3_ARB_BASE_ADDR -#endif - -#define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR -#define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR -#if defined(CONFIG_PLAT_IMX6SX) -/* AIPS3 exists on i.MX6SX */ -#define AIPS3_BASE_ADDR AIPS3_ON_BASE_ADDR -#endif - -#define SPDIF_BASE_ADDR (ATZ1_BASE_ADDR + 0x04000) -#define ECSPI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x08000) -#define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000) -#define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000) -#define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000) - -#if defined(CONFIG_PLAT_IMX6DQ) -#define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) -#endif - -#define UART1_BASE (ATZ1_BASE_ADDR + 0x20000) -#define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) -#define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000) -#define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000) -#define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000) -#define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) - -#if defined(CONFIG_PLAT_IMX6DQ) -#define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000) -#define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000) -#endif - -#define AIPS1_ON_BASE_ADDR (ATZ1_BASE_ADDR + 0x7C000) #define AIPS1_OFF_BASE_ADDR (ATZ1_BASE_ADDR + 0x80000) -#define PWM1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0000) -#define PWM2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4000) -#define PWM3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x8000) -#define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000) -#define CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000) -#define CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000) -#define GPT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000) #define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000) #define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x20000) #define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x24000) @@ -231,589 +41,3 @@ #define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000) #define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000) #define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000) -#define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000) -#define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000) -#define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000) -#define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000) -#define USB_PHY0_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x49000) -#define USB_PHY1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4a000) -#define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000) -#define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4C000) -#define EPIT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x50000) -#define EPIT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x54000) -#define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000) -#define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000) -#define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000) - - -#if defined(CONFIG_PLAT_IMX6DQ) - -#define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) -#define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) -#define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) - -#elif defined(CONFIG_PLAT_IMX6SX) - -#define CANFD1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) -#define SDMA_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) -#define CANFD2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000) -#define SEMAPHORE1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000) -#define SEMAPHORE2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000) -#define RDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000) - -#else -#error "unknown i.MX6 SOC" -#endif - - -#define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000) -#define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) -#define CAAM_BASE_ADDR (ATZ2_BASE_ADDR) -#define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000) - -#define CONFIG_SYS_FSL_SEC_ADDR CAAM_BASE_ADDR -#define CONFIG_SYS_FSL_JR0_ADDR (CAAM_BASE_ADDR + 0x1000) - -#define USBOH3_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000) -#define USBOH3_USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000) -#define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000) -#define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000) -#define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000) -#define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000) -#define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000) -#define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000) -#define I2C1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x20000) -#define I2C2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x24000) -#define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000) -#define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000) -#define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000) - -#ifdef CONFIG_PLAT_IMX6SX -#define ENET2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) -#endif - -#define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) -#define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000) -#define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000) -#define IMX_IIM_BASE OCOTP_BASE_ADDR -#define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000) -#define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000) -#define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) - - -#if defined(CONFIG_PLAT_IMX6DQ) - -#define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000) -#define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000) -#define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000) -#define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000) -#define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) -#define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) -#define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000) - -#elif defined(CONFIG_PLAT_IMX6SX) - -#define DEBUG_MONITOR_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000) -#define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000) -#define SAI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000) -#define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000) -#define SAI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) -#define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) -#define QSPI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000) - -#else -#error "unknown i.MX6 SOC" -#endif - - -#define UART2_BASE (AIPS2_OFF_BASE_ADDR + 0x68000) -#define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000) -#define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000) -#define UART5_BASE (AIPS2_OFF_BASE_ADDR + 0x74000) -#define I2C4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000) -#define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000) -#define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) - -#if defined(CONFIG_PLAT_IMX6SX) -/* ATZ3/AIPS3 exists on i.MX6SX */ - -#define AIPS3_ON_BASE_ADDR (ATZ3_BASE_ADDR + 0x7C000) -#define AIPS3_OFF_BASE_ADDR (ATZ3_BASE_ADDR + 0x80000) - -#define GIS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x04000) -#define DCIC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x0C000) -#define DCIC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x10000) -#define CSI1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x14000) -#define PXP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x18000) -#define CSI2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x1C000) -#define LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000) -#define LCDIF2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x24000) -#define VADC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x28000) -#define VDEC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x2C000) -#define SPBA_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x3C000) -#define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000) -#define ADC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000) -#define ADC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000) -#define WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000) -#define ECSPI5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000) -#define HS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000) -#define MU_MCU_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000) -#define CANFD_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x98000) -#define MU_DSP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x9C000) -#define UART6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA0000) -#define PWM5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA4000) -#define PWM6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA8000) -#define PWM7_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xAC000) -#define PWM8_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xB0000) - -#endif /* defined(CONFIG_PLAT_IMX6SX) */ - - -#define CHIP_REV_1_0 0x10 - -#define FEC_QUIRK_ENET_MAC - - -#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) - -/* System Reset Controller (SRC) */ -struct src { - uint32_t scr; - uint32_t sbmr1; - uint32_t srsr; - uint32_t reserved1[2]; - uint32_t sisr; - uint32_t simr; - uint32_t sbmr2; - uint32_t gpr1; - uint32_t gpr2; - uint32_t gpr3; - uint32_t gpr4; - uint32_t gpr5; - uint32_t gpr6; - uint32_t gpr7; - uint32_t gpr8; - uint32_t gpr9; - uint32_t gpr10; -}; - -/* OCOTP Registers */ -struct ocotp_regs { - uint32_t reserved[0x198]; - uint32_t gp1; /* 0x660 */ -}; - -/* GPR3 bitfields */ -#define IOMUXC_GPR3_GPU_DBG_OFFSET 29 -#define IOMUXC_GPR3_GPU_DBG_MASK (3< Date: Thu, 23 Sep 2021 12:48:41 +1000 Subject: [PATCH 3/8] Fixed pin control for imx8mm Signed-off-by: Lucy --- libethdrivers/CMakeLists.txt | 2 +- libethdrivers/src/lwip.c | 4 ++- libethdrivers/src/plat/imx6/enet.c | 10 +++--- libethdrivers/src/plat/imx6/imx6.c | 13 +++++--- libethdrivers/src/plat/imx6/ocotp_ctrl.c | 12 +++++-- libethdrivers/src/plat/imx6/uboot/fec_mxc.c | 8 +++-- .../src/plat/imx6/uboot/imx8mq_pins.h | 2 +- libethdrivers/src/plat/imx6/uboot/imx_board.c | 33 ++++++++++++++++++- libethdrivers/src/plat/imx6/uboot/mxc_gpio.c | 2 +- libethdrivers/src/plat/imx6/uboot/phy.c | 1 + 10 files changed, 66 insertions(+), 21 deletions(-) diff --git a/libethdrivers/CMakeLists.txt b/libethdrivers/CMakeLists.txt index 39f3527ea..bea69d4f2 100644 --- a/libethdrivers/CMakeLists.txt +++ b/libethdrivers/CMakeLists.txt @@ -63,7 +63,7 @@ mark_as_advanced( ) add_config_library(ethdrivers "${configure_string}") -if("${KernelPlatform}" MATCHES "imx8mq-evk") +if(("${KernelPlatform}" MATCHES "imx8mq-evk") OR ("${KernelPlatform}" MATCHES "imx8mm-evk")) # Re-use the imx6 sources set(PlatPrefix "imx6") else() diff --git a/libethdrivers/src/lwip.c b/libethdrivers/src/lwip.c index e45fc3a81..3eae63178 100644 --- a/libethdrivers/src/lwip.c +++ b/libethdrivers/src/lwip.c @@ -58,7 +58,9 @@ static void initialize_free_bufs(lwip_iface_t *iface) } static uintptr_t lwip_allocate_rx_buf(void *iface, size_t buf_size, void **cookie) -{ +{ + ZF_LOGW("lwip.c in libethdrivers/src/plat called lwip_allocate_rx_buf()\n"); + lwip_iface_t *lwip_iface = (lwip_iface_t *)iface; if (buf_size > CONFIG_LIB_ETHDRIVER_PREALLOCATED_BUF_SIZE) { LOG_ERROR("Requested RX buffer of size %zu which can never be fullfilled by preallocated buffers of size %d", buf_size, diff --git a/libethdrivers/src/plat/imx6/enet.c b/libethdrivers/src/plat/imx6/enet.c index 1bfe7c448..db379d492 100644 --- a/libethdrivers/src/plat/imx6/enet.c +++ b/libethdrivers/src/plat/imx6/enet.c @@ -16,8 +16,8 @@ #include #include -#ifdef CONFIG_PLAT_IMX8MQ_EVK -#define CCM_PADDR 0x30380000 +#if (defined(CONFIG_PLAT_IMX8MQ_EVK) || defined(CONFIG_PLAT_IMX8MM_EVK)) +#define CCM_PADDR 0x30380000 // from: root/arch/arm/include/asm/arch-imx8m/imx-regs-imx8mm.h #define CCM_SIZE 0x10000 #endif @@ -314,7 +314,7 @@ static struct clock mdc_clk = { }; -#ifdef CONFIG_PLAT_IMX8MQ_EVK +#if (defined(CONFIG_PLAT_IMX8MQ_EVK) || defined(CONFIG_PLAT_IMX8MM_EVK)) static freq_t _enet_clk_get_freq(clk_t *clk) { @@ -558,7 +558,7 @@ struct enet *enet_init(void *mapped_peripheral, uintptr_t tx_phys, enet_clk_ptr = clk_get_clock(clk_sys, CLK_ENET); clk_set_freq(enet_clk_ptr, ENET_FREQ); -#elif defined(CONFIG_PLAT_IMX8MQ_EVK) +#elif defined(CONFIG_PLAT_IMX8MQ_EVK) || defined(CONFIG_PLAT_IMX8MM_EVK) enet_clk_ptr = &enet_clk; // TODO Implement an actual clock driver for the imx8mq @@ -606,7 +606,7 @@ struct enet *enet_init(void *mapped_peripheral, uintptr_t tx_phys, regs->gaur = 0; regs->galr = 0; -#ifndef CONFIG_PLAT_IMX8MQ_EVK +#if defined(CONFIG_PLAT_IMX8MQ_EVK) || defined(CONFIG_PLAT_IMX8MM_EVK) /* For iMX.8 we assume that the bootloader has already correctly * configured the MAC address */ /* Set MAC and pause frame type field */ diff --git a/libethdrivers/src/plat/imx6/imx6.c b/libethdrivers/src/plat/imx6/imx6.c index 8fa2bce6e..2ef1ab361 100644 --- a/libethdrivers/src/plat/imx6/imx6.c +++ b/libethdrivers/src/plat/imx6/imx6.c @@ -639,8 +639,8 @@ static int init_device(imx6_eth_driver_t *dev, const nic_config_t *nic_config) int ret; -#ifdef CONFIG_PLAT_IMX8MQ_EVK - /* Don't attempt to obtain the MAC address for iMX8. +#if defined(CONFIG_PLAT_IMX8MQ_EVK) + /* Don't attempt to obtain the MAC address for iMX8MQ. * * The code to obtain the MAC address assumes an iMX6 compatible * OCOTP which the iMX8 does not have. @@ -650,6 +650,7 @@ static int init_device(imx6_eth_driver_t *dev, const nic_config_t *nic_config) uint64_t mac = 0; ZF_LOGI("using MAC configured by bootloader"); #else + /* this works for imx8mm however */ uint64_t mac = obtain_mac(nic_config, &(dev->eth_drv.io_ops.io_mapper)); if (0 == mac) { ZF_LOGE("Failed to obtain a MAC"); @@ -753,7 +754,7 @@ static int init_device(imx6_eth_driver_t *dev, const nic_config_t *nic_config) /* Initialise the phy */ #if defined(CONFIG_PLAT_SABRE) || defined(CONFIG_PLAT_WANDQ) || defined(CONFIG_PLAT_IMX8MQ_EVK) phy_micrel_init(); -#elif defined(CONFIG_PLAT_NITROGEN6SX) +#elif defined(CONFIG_PLAT_NITROGEN6SX) || defined(CONFIG_PLAT_IMX8MM_EVK) phy_atheros_init(); #else #error "unsupported board" @@ -839,11 +840,12 @@ static int allocate_irq_callback(ps_irq_t irq, unsigned curr_num, assert(token); imx6_eth_driver_t *dev = (imx6_eth_driver_t *)token; - unsigned target_num = config_set(CONFIG_PLAT_IMX8MQ_EVK) ? 2 : 0; + /*unsigned target_num = config_set(CONFIG_PLAT_IMX8MQ_EVK) ? 2 : 0; + ZF_LOGW("target_num = %d", target_num); if (curr_num != target_num) { ZF_LOGW("Ignoring interrupt #%d with value %d", curr_num, irq); return 0; - } + }*/ dev->irq_id = ps_irq_register( &(dev->eth_drv.io_ops.irq_ops), @@ -990,6 +992,7 @@ static const char *compatible_strings[] = { "fsl,imx6q-fec", "fsl,imx6sx-fec", "fsl,imx8mq-fec", + "fsl,imx8mm-fec", NULL }; diff --git a/libethdrivers/src/plat/imx6/ocotp_ctrl.c b/libethdrivers/src/plat/imx6/ocotp_ctrl.c index 9f4d46e23..2d8482734 100644 --- a/libethdrivers/src/plat/imx6/ocotp_ctrl.c +++ b/libethdrivers/src/plat/imx6/ocotp_ctrl.c @@ -22,8 +22,8 @@ #define IMX6_OCOTP_PADDR 0x021BC000 #define IMX6_OCOTP_SIZE 0x00004000 -#elif defined(CONFIG_PLAT_IMX8MQ_EVK) - +#elif defined(CONFIG_PLAT_IMX8MQ_EVK) || defined(CONFIG_PLAT_IMX8MM_EVK) +// from: root/arch/arm/include/asm/arch-imx8m/imx-regs-imx8mm.h #define IMX6_OCOTP_PADDR 0x30350000 #define IMX6_OCOTP_SIZE 0x00010000 @@ -211,10 +211,16 @@ uint64_t ocotp_get_mac(struct ocotp *ocotp, unsigned int id) uint64_t mac = 0; switch (id) { +#if defined(CONFIG_PLAT_IMX8MM_EVK) || defined(CONFIG_IMX8MQ_EVK) + case 0: + mac = ((uint64_t)((uint16_t)regs->res37[4]) << 32) | regs->res37[0]; + break; +#else case 0: /* 0x0000
*/ mac = ((uint64_t)((uint16_t)regs->mac1) << 32) | regs->mac0; break; +#endif #ifdef CONFIG_PLAT_IMX6SX @@ -237,7 +243,7 @@ uint64_t ocotp_get_mac(struct ocotp *ocotp, unsigned int id) return 0; } - ZF_LOGI("OCOTP MAC #%u: %02x:%02x:%02x:%02x:%02x:%02x", + ZF_LOGW("OCOTP MAC #%u: %02x:%02x:%02x:%02x:%02x:%02x", id, (uint8_t)(mac >> 40), (uint8_t)(mac >> 32), (uint8_t)(mac >> 24), (uint8_t)(mac >> 16), (uint8_t)(mac >> 8), (uint8_t)mac); diff --git a/libethdrivers/src/plat/imx6/uboot/fec_mxc.c b/libethdrivers/src/plat/imx6/uboot/fec_mxc.c index fe724bbb9..f7dfcf4a0 100644 --- a/libethdrivers/src/plat/imx6/uboot/fec_mxc.c +++ b/libethdrivers/src/plat/imx6/uboot/fec_mxc.c @@ -176,9 +176,11 @@ struct phy_device *fec_init(unsigned int phy_mask, struct enet *enet, ZF_LOGW("SABRE: unexpected PHY with ID 0x%x", phydev->phy_id); } -#elif defined(CONFIG_PLAT_NITROGEN6SX) - - if (0x004dd072 == phydev->phy_id) { +#elif defined(CONFIG_PLAT_NITROGEN6SX) || defined(CONFIG_PLAT_IMX8MM_EVK) + /* imx6sx and imx8mm seem to use a very similar phy device. + The AR8031 (used in imx8mm) also has the SmartEEE feature but not sure if + this is necessary. */ + if (0x004dd072 == phydev->phy_id || 0x004dd074 == phydev->phy_id) { /* Disable Ar803x PHY SmartEEE feature, it causes link status glitches * that result in the ethernet link going down and up. */ diff --git a/libethdrivers/src/plat/imx6/uboot/imx8mq_pins.h b/libethdrivers/src/plat/imx6/uboot/imx8mq_pins.h index 68d833799..f76b70e50 100644 --- a/libethdrivers/src/plat/imx6/uboot/imx8mq_pins.h +++ b/libethdrivers/src/plat/imx6/uboot/imx8mq_pins.h @@ -24,7 +24,7 @@ #include "imx_pins.h" -#ifndef CONFIG_PLAT_IMX8MQ_EVK +#if !(defined(CONFIG_PLAT_IMX8MQ_EVK)) #error "CONFIG_PLAT_IMX8MQ_EVK must be defined to use this file" #endif diff --git a/libethdrivers/src/plat/imx6/uboot/imx_board.c b/libethdrivers/src/plat/imx6/uboot/imx_board.c index 3f29c309d..7287f583e 100644 --- a/libethdrivers/src/plat/imx6/uboot/imx_board.c +++ b/libethdrivers/src/plat/imx6/uboot/imx_board.c @@ -59,6 +59,12 @@ #define IOMUXC_PADDR 0x30330000 #define IOMUXC_SIZE 0x10000 +#elif defined(CONFIG_PLAT_IMX8MM_EVK) +#include "imx8mm_pins.h" + +#define IOMUXC_PADDR 0x30330000 // from: root/arch/arm/include/asm/arch-imx8m/imx-regs-imx8mm.h +#define IOMUXC_SIZE 0x10000 + #else #error "unknown i.MX SOC" #endif @@ -129,7 +135,6 @@ int setup_iomux_enet(ps_io_ops_t *io_ops) } #if defined(CONFIG_PLAT_IMX8MQ_EVK) - /* see the IMX8 reference manual for what the options mean, * Section 8.2.4 i.e. IOMUXC_SW_PAD_CTL_PAD_* registers */ IMX_IOMUX_V3_SETUP_MULTIPLE_PADS( @@ -158,6 +163,32 @@ int setup_iomux_enet(ps_io_ops_t *io_ops) /* Change ENET_TX to use internal clocks and not the external clocks */ *gpr1 = *gpr1 & ~(BIT(17) | BIT(13)); +#elif defined(CONFIG_PLAT_IMX8MM_EVK) + + /* Does PHY need to go into reset before this? */ + /* Pad configuration below from device tree on u-boot */ + IMX_IOMUX_V3_SETUP_MULTIPLE_PADS( + base, + IMX8MM_PAD_ENET_MDC_ENET1_MDC | MUX_PAD_CTRL(0x3), + IMX8MM_PAD_ENET_MDIO_ENET1_MDIO | MUX_PAD_CTRL(0x3), + IMX8MM_PAD_ENET_TD3_ENET1_RGMII_TD3 | MUX_PAD_CTRL(0x1f), + IMX8MM_PAD_ENET_TD2_ENET1_RGMII_TD2 | MUX_PAD_CTRL(0x1f), + IMX8MM_PAD_ENET_TD1_ENET1_RGMII_TD1 | MUX_PAD_CTRL(0x1f), + IMX8MM_PAD_ENET_TD0_ENET1_RGMII_TD0 | MUX_PAD_CTRL(0x1f), + IMX8MM_PAD_ENET_RD3_ENET1_RGMII_RD3 | MUX_PAD_CTRL(0x91), + IMX8MM_PAD_ENET_RD2_ENET1_RGMII_RD2 | MUX_PAD_CTRL(0x91), + IMX8MM_PAD_ENET_RD1_ENET1_RGMII_RD1 | MUX_PAD_CTRL(0x91), + IMX8MM_PAD_ENET_RD0_ENET1_RGMII_RD0 | MUX_PAD_CTRL(0x91), + IMX8MM_PAD_ENET_TXC_ENET1_RGMII_TXC | MUX_PAD_CTRL(0x1f), + IMX8MM_PAD_ENET_RXC_ENET1_RGMII_RXC | MUX_PAD_CTRL(0x91), + IMX8MM_PAD_ENET_RX_CTL_ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(0x91), + IMX8MM_PAD_ENET_TX_CTL_ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(0x1f) + ); + + uint32_t *gpr1 = base + 0x4; + /* Change ENET_TX to use internal clocks and not the external clocks */ + *gpr1 = *gpr1 & ~(BIT(17) | BIT(13)); + #elif defined(CONFIG_PLAT_IMX6DQ) #define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP | \ diff --git a/libethdrivers/src/plat/imx6/uboot/mxc_gpio.c b/libethdrivers/src/plat/imx6/uboot/mxc_gpio.c index 1339050c6..5b88d99ac 100644 --- a/libethdrivers/src/plat/imx6/uboot/mxc_gpio.c +++ b/libethdrivers/src/plat/imx6/uboot/mxc_gpio.c @@ -61,7 +61,7 @@ static unsigned long gpio_paddr[] = { [6] = GPIO7_BASE_ADDR, }; -#elif defined(CONFIG_PLAT_IMX8MQ_EVK) +#elif defined(CONFIG_PLAT_IMX8MQ_EVK) || defined(CONFIG_PLAT_IMX8MM_EVK) static unsigned long gpio_ports[] = { [0] = 0, diff --git a/libethdrivers/src/plat/imx6/uboot/phy.c b/libethdrivers/src/plat/imx6/uboot/phy.c index f837d9322..8114e6a50 100644 --- a/libethdrivers/src/plat/imx6/uboot/phy.c +++ b/libethdrivers/src/plat/imx6/uboot/phy.c @@ -511,6 +511,7 @@ static struct phy_device *phy_device_create(struct mii_dev *bus, int addr, /* We allocate the device, and initialize the * default values */ + dev = malloc(sizeof(*dev)); if (!dev) { ZF_LOGE("Failed to allocate PHY device for '%s':%d", bus->name, addr); From 9b687f2fbdd1b31271c2b1db419847e04520507e Mon Sep 17 00:00:00 2001 From: Lucy Date: Thu, 23 Sep 2021 12:49:26 +1000 Subject: [PATCH 4/8] pin set up for imx8mm machine Signed-off-by: Lucy --- libethdrivers/src/lwip.c | 2 + libethdrivers/src/plat/imx6/imx6.c | 7 +- .../src/plat/imx6/uboot/imx8mm_pins.h | 694 ++++++++++++++++++ 3 files changed, 700 insertions(+), 3 deletions(-) create mode 100644 libethdrivers/src/plat/imx6/uboot/imx8mm_pins.h diff --git a/libethdrivers/src/lwip.c b/libethdrivers/src/lwip.c index 3eae63178..f21d265d6 100644 --- a/libethdrivers/src/lwip.c +++ b/libethdrivers/src/lwip.c @@ -413,6 +413,8 @@ static err_t ethif_init(struct netif *netif) return ERR_ARG; } + printf("Does this file, lwip.c, get used\n"); + lwip_iface_t *iface = (lwip_iface_t *)netif->state; int mtu; iface->driver.i_fn.low_level_init(&iface->driver, netif->hwaddr, &mtu); diff --git a/libethdrivers/src/plat/imx6/imx6.c b/libethdrivers/src/plat/imx6/imx6.c index 2ef1ab361..2ba21a43d 100644 --- a/libethdrivers/src/plat/imx6/imx6.c +++ b/libethdrivers/src/plat/imx6/imx6.c @@ -188,6 +188,7 @@ static void fill_rx_bufs(imx6_eth_driver_t *dev) * small because CONFIG_LIB_ETHDRIVER_NUM_PREALLOCATED_BUFFERS * is less than CONFIG_LIB_ETHDRIVER_RX_DESC_COUNT. */ + ZF_LOGF("There are no buffers left."); break; } uint16_t stat = RXD_EMPTY; @@ -415,7 +416,8 @@ static void complete_tx(imx6_eth_driver_t *dev) if (!enet_tx_enabled(dev->enet)) { enet_tx_enable(dev->enet); } - return; + //ZF_LOGF("The buffer was not sent and we can't release any buffers."); + //enet_print_state(dev->enet);; } /* Go to next buffer, handle roll-over. */ @@ -423,14 +425,13 @@ static void complete_tx(imx6_eth_driver_t *dev) head = 0; } - if (0 == --cnt) { + if (0 == --cnt && !(d->stat & TXD_READY)) { ring->head = head; /* race condition if add/remove is not synchronized. */ ring->remain += cnt_org; /* give the buffer back */ cb_complete(cb_cookie, cookie); } - } /* The only reason to arrive here is when head equals tails. If cnt is not diff --git a/libethdrivers/src/plat/imx6/uboot/imx8mm_pins.h b/libethdrivers/src/plat/imx6/uboot/imx8mm_pins.h new file mode 100644 index 000000000..71fc2ab5a --- /dev/null +++ b/libethdrivers/src/plat/imx6/uboot/imx8mm_pins.h @@ -0,0 +1,694 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018-2019 NXP + * Taken from u-boot/arch/arm/include/asm/arch-imx8m/imx8mm_pins.h + */ + +#pragma once + +#include "imx_pins.h" + +#if !(defined(CONFIG_PLAT_IMX8MM_EVK)) +#error "CONFIG_PLAT_IMX8MM_EVK must be defined to use this file" +#endif + +enum { + IMX8MM_PAD_GPIO1_IO00_GPIO1_IO0 = IOMUX_PAD(0x0290, 0x0028, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT = IOMUX_PAD(0x0290, 0x0028, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO00_XTALOSC_REF_CLK_32K = IOMUX_PAD(0x0290, 0x0028, 5, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO00_CCM_EXT_CLK1 = IOMUX_PAD(0x0290, 0x0028, 6, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO01_GPIO1_IO1 = IOMUX_PAD(0x0294, 0x002C, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO01_PWM1_OUT = IOMUX_PAD(0x0294, 0x002C, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO01_XTALOSC_REF_CLK_24M = IOMUX_PAD(0x0294, 0x002C, 5, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO01_CCM_EXT_CLK2 = IOMUX_PAD(0x0294, 0x002C, 6, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO02_GPIO1_IO2 = IOMUX_PAD(0x0298, 0x0030, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B = IOMUX_PAD(0x0298, 0x0030, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_ANY = IOMUX_PAD(0x0298, 0x0030, 5, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO03_GPIO1_IO3 = IOMUX_PAD(0x029C, 0x0034, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO03_USDHC1_VSELECT = IOMUX_PAD(0x029C, 0x0034, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO03_SDMA1_EXT_EVENT0 = IOMUX_PAD(0x029C, 0x0034, 5, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO04_GPIO1_IO4 = IOMUX_PAD(0x02A0, 0x0038, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO04_USDHC2_VSELECT = IOMUX_PAD(0x02A0, 0x0038, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO04_SDMA1_EXT_EVENT1 = IOMUX_PAD(0x02A0, 0x0038, 5, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO05_GPIO1_IO5 = IOMUX_PAD(0x02A4, 0x003C, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO05_ARM_PLATFORM_M4_NMI = IOMUX_PAD(0x02A4, 0x003C, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO05_CCM_PMIC_READY = IOMUX_PAD(0x02A4, 0x003C, 5, 0x04BC, 0, 0), + IMX8MM_PAD_GPIO1_IO05_SRC_INT_BOOT = IOMUX_PAD(0x02A4, 0x003C, 6, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO06_GPIO1_IO6 = IOMUX_PAD(0x02A8, 0x0040, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO06_ENET1_MDC = IOMUX_PAD(0x02A8, 0x0040, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO06_USDHC1_CD_B = IOMUX_PAD(0x02A8, 0x0040, 5, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO06_CCM_EXT_CLK3 = IOMUX_PAD(0x02A8, 0x0040, 6, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO07_GPIO1_IO7 = IOMUX_PAD(0x02AC, 0x0044, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO07_ENET1_MDIO = IOMUX_PAD(0x02AC, 0x0044, 1, 0x04C0, 0, 0), + IMX8MM_PAD_GPIO1_IO07_USDHC1_WP = IOMUX_PAD(0x02AC, 0x0044, 5, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO07_CCM_EXT_CLK4 = IOMUX_PAD(0x02AC, 0x0044, 6, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO08_GPIO1_IO8 = IOMUX_PAD(0x02B0, 0x0048, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO08_ENET1_1588_EVENT0_IN = IOMUX_PAD(0x02B0, 0x0048, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO08_USDHC2_RESET_B = IOMUX_PAD(0x02B0, 0x0048, 5, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO08_CCM_WAIT = IOMUX_PAD(0x02B0, 0x0048, 6, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO09_GPIO1_IO9 = IOMUX_PAD(0x02B4, 0x004C, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO09_ENET1_1588_EVENT0_OUT = IOMUX_PAD(0x02B4, 0x004C, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO09_USDHC3_RESET_B = IOMUX_PAD(0x02B4, 0x004C, 4, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO09_SDMA2_EXT_EVENT0 = IOMUX_PAD(0x02B4, 0x004C, 5, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO09_CCM_STOP = IOMUX_PAD(0x02B4, 0x004C, 6, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO10_GPIO1_IO10 = IOMUX_PAD(0x02B8, 0x0050, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO10_USB1_OTG_ID = IOMUX_PAD(0x02B8, 0x0050, 1, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO11_GPIO1_IO11 = IOMUX_PAD(0x02BC, 0x0054, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO11_USB2_OTG_ID = IOMUX_PAD(0x02BC, 0x0054, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO11_USDHC3_VSELECT = IOMUX_PAD(0x02BC, 0x0054, 4, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO11_CCM_PMIC_READY = IOMUX_PAD(0x02BC, 0x0054, 5, 0x04BC, 1, 0), + IMX8MM_PAD_GPIO1_IO11_CCM_OUT0 = IOMUX_PAD(0x02BC, 0x0054, 6, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO12_GPIO1_IO12 = IOMUX_PAD(0x02C0, 0x0058, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO12_USB1_OTG_PWR = IOMUX_PAD(0x02C0, 0x0058, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO12_SDMA2_EXT_EVENT1 = IOMUX_PAD(0x02C0, 0x0058, 5, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO12_CCM_OUT1 = IOMUX_PAD(0x02C0, 0x0058, 6, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO13_GPIO1_IO13 = IOMUX_PAD(0x02C4, 0x005C, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO13_USB1_OTG_OC = IOMUX_PAD(0x02C4, 0x005C, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO13_PWM2_OUT = IOMUX_PAD(0x02C4, 0x005C, 5, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO13_CCM_OUT2 = IOMUX_PAD(0x02C4, 0x005C, 6, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO14_GPIO1_IO14 = IOMUX_PAD(0x02C8, 0x0060, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO14_USB2_OTG_PWR = IOMUX_PAD(0x02C8, 0x0060, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO14_USDHC3_CD_B = IOMUX_PAD(0x02C8, 0x0060, 4, 0x0544, 2, 0), + IMX8MM_PAD_GPIO1_IO14_PWM3_OUT = IOMUX_PAD(0x02C8, 0x0060, 5, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO14_CCM_CLKO1 = IOMUX_PAD(0x02C8, 0x0060, 6, 0x0000, 0, 0), + + IMX8MM_PAD_GPIO1_IO15_GPIO1_IO15 = IOMUX_PAD(0x02CC, 0x0064, 0, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO15_USB2_OTG_OC = IOMUX_PAD(0x02CC, 0x0064, 1, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO15_USDHC3_WP = IOMUX_PAD(0x02CC, 0x0064, 4, 0x0548, 2, 0), + IMX8MM_PAD_GPIO1_IO15_PWM4_OUT = IOMUX_PAD(0x02CC, 0x0064, 5, 0x0000, 0, 0), + IMX8MM_PAD_GPIO1_IO15_CCM_CLKO2 = IOMUX_PAD(0x02CC, 0x0064, 6, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_MDC_ENET1_MDC = IOMUX_PAD(0x02D0, 0x0068, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_MDC_GPIO1_IO16 = IOMUX_PAD(0x02D0, 0x0068, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_MDIO_ENET1_MDIO = IOMUX_PAD(0x02D4, 0x006C, 0, 0x04C0, 1, 0), + IMX8MM_PAD_ENET_MDIO_GPIO1_IO17 = IOMUX_PAD(0x02D4, 0x006C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_TD3_ENET1_RGMII_TD3 = IOMUX_PAD(0x02D8, 0x0070, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_TD3_GPIO1_IO18 = IOMUX_PAD(0x02D8, 0x0070, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_TD2_ENET1_RGMII_TD2 = IOMUX_PAD(0x02DC, 0x0074, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_TD2_ENET1_TX_CLK = IOMUX_PAD(0x02DC, 0x0074, 1, 0x0000, 0, 0), + IMX8MM_PAD_ENET_TD2_CCM_ENET_REF_CLK_ROOT = IOMUX_PAD(0x02DC, 0x0074, 1, 0x0000, 0, 0), + IMX8MM_PAD_ENET_TD2_GPIO1_IO19 = IOMUX_PAD(0x02DC, 0x0074, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_TD1_ENET1_RGMII_TD1 = IOMUX_PAD(0x02E0, 0x0078, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_TD1_GPIO1_IO20 = IOMUX_PAD(0x02E0, 0x0078, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_TD0_ENET1_RGMII_TD0 = IOMUX_PAD(0x02E4, 0x007C, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_TD0_GPIO1_IO21 = IOMUX_PAD(0x02E4, 0x007C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_TX_CTL_ENET1_RGMII_TX_CTL = IOMUX_PAD(0x02E8, 0x0080, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_TX_CTL_GPIO1_IO22 = IOMUX_PAD(0x02E8, 0x0080, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_TXC_ENET1_RGMII_TXC = IOMUX_PAD(0x02EC, 0x0084, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_TXC_ENET1_TX_ER = IOMUX_PAD(0x02EC, 0x0084, 1, 0x0000, 0, 0), + IMX8MM_PAD_ENET_TXC_GPIO1_IO23 = IOMUX_PAD(0x02EC, 0x0084, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_RX_CTL_ENET1_RGMII_RX_CTL = IOMUX_PAD(0x02F0, 0x0088, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_RX_CTL_GPIO1_IO24 = IOMUX_PAD(0x02F0, 0x0088, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_RXC_ENET1_RGMII_RXC = IOMUX_PAD(0x02F4, 0x008C, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_RXC_ENET1_RX_ER = IOMUX_PAD(0x02F4, 0x008C, 1, 0x0000, 0, 0), + IMX8MM_PAD_ENET_RXC_GPIO1_IO25 = IOMUX_PAD(0x02F4, 0x008C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_RD0_ENET1_RGMII_RD0 = IOMUX_PAD(0x02F8, 0x0090, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_RD0_GPIO1_IO26 = IOMUX_PAD(0x02F8, 0x0090, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_RD1_ENET1_RGMII_RD1 = IOMUX_PAD(0x02FC, 0x0094, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_RD1_GPIO1_IO27 = IOMUX_PAD(0x02FC, 0x0094, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_RD2_ENET1_RGMII_RD2 = IOMUX_PAD(0x0300, 0x0098, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_RD2_GPIO1_IO28 = IOMUX_PAD(0x0300, 0x0098, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ENET_RD3_ENET1_RGMII_RD3 = IOMUX_PAD(0x0304, 0x009C, 0, 0x0000, 0, 0), + IMX8MM_PAD_ENET_RD3_GPIO1_IO29 = IOMUX_PAD(0x0304, 0x009C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_CLK_USDHC1_CLK = IOMUX_PAD(0x0308, 0x00A0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_CLK_GPIO2_IO0 = IOMUX_PAD(0x0308, 0x00A0, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_CMD_USDHC1_CMD = IOMUX_PAD(0x030C, 0x00A4, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_CMD_GPIO2_IO1 = IOMUX_PAD(0x030C, 0x00A4, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_DATA0_USDHC1_DATA0 = IOMUX_PAD(0x0310, 0x00A8, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_DATA0_GPIO2_IO2 = IOMUX_PAD(0x0310, 0x00A8, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_DATA1_USDHC1_DATA1 = IOMUX_PAD(0x0314, 0x00AC, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_DATA1_GPIO2_IO3 = IOMUX_PAD(0x0314, 0x00AC, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_DATA2_USDHC1_DATA2 = IOMUX_PAD(0x0318, 0x00B0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_DATA2_GPIO2_IO4 = IOMUX_PAD(0x0318, 0x00B0, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_DATA3_USDHC1_DATA3 = IOMUX_PAD(0x031C, 0x00B4, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_DATA3_GPIO2_IO5 = IOMUX_PAD(0x031C, 0x00B4, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_DATA4_USDHC1_DATA4 = IOMUX_PAD(0x0320, 0x00B8, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_DATA4_GPIO2_IO6 = IOMUX_PAD(0x0320, 0x00B8, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_DATA5_USDHC1_DATA5 = IOMUX_PAD(0x0324, 0x00BC, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_DATA5_GPIO2_IO7 = IOMUX_PAD(0x0324, 0x00BC, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_DATA6_USDHC1_DATA6 = IOMUX_PAD(0x0328, 0x00C0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_DATA6_GPIO2_IO8 = IOMUX_PAD(0x0328, 0x00C0, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_DATA7_USDHC1_DATA7 = IOMUX_PAD(0x032C, 0x00C4, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_DATA7_GPIO2_IO9 = IOMUX_PAD(0x032C, 0x00C4, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_RESET_B_USDHC1_RESET_B = IOMUX_PAD(0x0330, 0x00C8, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_RESET_B_GPIO2_IO10 = IOMUX_PAD(0x0330, 0x00C8, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD1_STROBE_USDHC1_STROBE = IOMUX_PAD(0x0334, 0x00CC, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD1_STROBE_GPIO2_IO11 = IOMUX_PAD(0x0334, 0x00CC, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD2_CD_B_USDHC2_CD_B = IOMUX_PAD(0x0338, 0x00D0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD2_CD_B_GPIO2_IO12 = IOMUX_PAD(0x0338, 0x00D0, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SD2_CLK_USDHC2_CLK = IOMUX_PAD(0x033C, 0x00D4, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD2_CLK_GPIO2_IO13 = IOMUX_PAD(0x033C, 0x00D4, 5, 0x0000, 0, 0), + IMX8MM_PAD_SD2_CLK_CCM_OBSERVE0 = IOMUX_PAD(0x033C, 0x00D4, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SD2_CMD_USDHC2_CMD = IOMUX_PAD(0x0340, 0x00D8, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD2_CMD_GPIO2_IO14 = IOMUX_PAD(0x0340, 0x00D8, 5, 0x0000, 0, 0), + IMX8MM_PAD_SD2_CMD_CCM_OBSERVE1 = IOMUX_PAD(0x0340, 0x00D8, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SD2_DATA0_USDHC2_DATA0 = IOMUX_PAD(0x0344, 0x00DC, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD2_DATA0_GPIO2_IO15 = IOMUX_PAD(0x0344, 0x00DC, 5, 0x0000, 0, 0), + IMX8MM_PAD_SD2_DATA0_CCM_OBSERVE2 = IOMUX_PAD(0x0344, 0x00DC, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SD2_DATA1_USDHC2_DATA1 = IOMUX_PAD(0x0348, 0x00E0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD2_DATA1_GPIO2_IO16 = IOMUX_PAD(0x0348, 0x00E0, 5, 0x0000, 0, 0), + IMX8MM_PAD_SD2_DATA1_CCM_WAIT = IOMUX_PAD(0x0348, 0x00E0, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SD2_DATA2_USDHC2_DATA2 = IOMUX_PAD(0x034C, 0x00E4, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD2_DATA2_GPIO2_IO17 = IOMUX_PAD(0x034C, 0x00E4, 5, 0x0000, 0, 0), + IMX8MM_PAD_SD2_DATA2_CCM_STOP = IOMUX_PAD(0x034C, 0x00E4, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 = IOMUX_PAD(0x0350, 0x00E8, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD2_DATA3_GPIO2_IO18 = IOMUX_PAD(0x0350, 0x00E8, 5, 0x0000, 0, 0), + IMX8MM_PAD_SD2_DATA3_SRC_EARLY_RESET = IOMUX_PAD(0x0350, 0x00E8, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SD2_RESET_B_USDHC2_RESET_B = IOMUX_PAD(0x0354, 0x00EC, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD2_RESET_B_GPIO2_IO19 = IOMUX_PAD(0x0354, 0x00EC, 5, 0x0000, 0, 0), + IMX8MM_PAD_SD2_RESET_B_SRC_SYSTEM_RESET = IOMUX_PAD(0x0354, 0x00EC, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SD2_WP_USDHC2_WP = IOMUX_PAD(0x0358, 0x00F0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SD2_WP_GPIO2_IO20 = IOMUX_PAD(0x0358, 0x00F0, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_ALE_RAWNAND_ALE = IOMUX_PAD(0x035C, 0x00F4, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_ALE_QSPI_A_SCLK = IOMUX_PAD(0x035C, 0x00F4, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_ALE_GPIO3_IO0 = IOMUX_PAD(0x035C, 0x00F4, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_CE0_B_RAWNAND_CE0_B = IOMUX_PAD(0x0360, 0x00F8, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CE0_B_QSPI_A_SS0_B = IOMUX_PAD(0x0360, 0x00F8, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CE0_B_GPIO3_IO1 = IOMUX_PAD(0x0360, 0x00F8, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_CE1_B_RAWNAND_CE1_B = IOMUX_PAD(0x0364, 0x00FC, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CE1_B_QSPI_A_SS1_B = IOMUX_PAD(0x0364, 0x00FC, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CE1_B_USDHC3_STROBE = IOMUX_PAD(0x0364, 0x00FC, 2, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CE1_B_GPIO3_IO2 = IOMUX_PAD(0x0364, 0x00FC, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_CE2_B_RAWNAND_CE2_B = IOMUX_PAD(0x0368, 0x0100, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CE2_B_QSPI_B_SS0_B = IOMUX_PAD(0x0368, 0x0100, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CE2_B_USDHC3_DATA5 = IOMUX_PAD(0x0368, 0x0100, 2, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CE2_B_GPIO3_IO3 = IOMUX_PAD(0x0368, 0x0100, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_CE3_B_RAWNAND_CE3_B = IOMUX_PAD(0x036C, 0x0104, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CE3_B_QSPI_B_SS1_B = IOMUX_PAD(0x036C, 0x0104, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CE3_B_USDHC3_DATA6 = IOMUX_PAD(0x036C, 0x0104, 2, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CE3_B_GPIO3_IO4 = IOMUX_PAD(0x036C, 0x0104, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_CLE_RAWNAND_CLE = IOMUX_PAD(0x0370, 0x0108, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CLE_QSPI_B_SCLK = IOMUX_PAD(0x0370, 0x0108, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CLE_USDHC3_DATA7 = IOMUX_PAD(0x0370, 0x0108, 2, 0x0000, 0, 0), + IMX8MM_PAD_NAND_CLE_GPIO3_IO5 = IOMUX_PAD(0x0370, 0x0108, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_DATA00_RAWNAND_DATA00 = IOMUX_PAD(0x0374, 0x010C, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA00_QSPI_A_DATA0 = IOMUX_PAD(0x0374, 0x010C, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA00_GPIO3_IO6 = IOMUX_PAD(0x0374, 0x010C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_DATA01_RAWNAND_DATA01 = IOMUX_PAD(0x0378, 0x0110, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA01_QSPI_A_DATA1 = IOMUX_PAD(0x0378, 0x0110, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA01_GPIO3_IO7 = IOMUX_PAD(0x0378, 0x0110, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_DATA02_RAWNAND_DATA02 = IOMUX_PAD(0x037C, 0x0114, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA02_QSPI_A_DATA2 = IOMUX_PAD(0x037C, 0x0114, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA02_USDHC3_CD_B = IOMUX_PAD(0x037C, 0x0114, 2, 0x0544, 0, 0), + IMX8MM_PAD_NAND_DATA02_GPIO3_IO8 = IOMUX_PAD(0x037C, 0x0114, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_DATA03_RAWNAND_DATA03 = IOMUX_PAD(0x0380, 0x0118, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA03_QSPI_A_DATA3 = IOMUX_PAD(0x0380, 0x0118, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA03_USDHC3_WP = IOMUX_PAD(0x0380, 0x0118, 2, 0x0548, 0, 0), + IMX8MM_PAD_NAND_DATA03_GPIO3_IO9 = IOMUX_PAD(0x0380, 0x0118, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_DATA04_RAWNAND_DATA04 = IOMUX_PAD(0x0384, 0x011C, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA04_QSPI_B_DATA0 = IOMUX_PAD(0x0384, 0x011C, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA04_USDHC3_DATA0 = IOMUX_PAD(0x0384, 0x011C, 2, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA04_GPIO3_IO10 = IOMUX_PAD(0x0384, 0x011C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_DATA05_RAWNAND_DATA05 = IOMUX_PAD(0x0388, 0x0120, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA05_QSPI_B_DATA1 = IOMUX_PAD(0x0388, 0x0120, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA05_USDHC3_DATA1 = IOMUX_PAD(0x0388, 0x0120, 2, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA05_GPIO3_IO11 = IOMUX_PAD(0x0388, 0x0120, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_DATA06_RAWNAND_DATA06 = IOMUX_PAD(0x038C, 0x0124, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA06_QSPI_B_DATA2 = IOMUX_PAD(0x038C, 0x0124, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA06_USDHC3_DATA2 = IOMUX_PAD(0x038C, 0x0124, 2, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA06_GPIO3_IO12 = IOMUX_PAD(0x038C, 0x0124, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_DATA07_RAWNAND_DATA07 = IOMUX_PAD(0x0390, 0x0128, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA07_QSPI_B_DATA3 = IOMUX_PAD(0x0390, 0x0128, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA07_USDHC3_DATA3 = IOMUX_PAD(0x0390, 0x0128, 2, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DATA07_GPIO3_IO13 = IOMUX_PAD(0x0390, 0x0128, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_DQS_RAWNAND_DQS = IOMUX_PAD(0x0394, 0x012C, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DQS_QSPI_A_DQS = IOMUX_PAD(0x0394, 0x012C, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_DQS_GPIO3_IO14 = IOMUX_PAD(0x0394, 0x012C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_RE_B_RAWNAND_RE_B = IOMUX_PAD(0x0398, 0x0130, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_RE_B_QSPI_B_DQS = IOMUX_PAD(0x0398, 0x0130, 1, 0x0000, 0, 0), + IMX8MM_PAD_NAND_RE_B_USDHC3_DATA4 = IOMUX_PAD(0x0398, 0x0130, 2, 0x0000, 0, 0), + IMX8MM_PAD_NAND_RE_B_GPIO3_IO15 = IOMUX_PAD(0x0398, 0x0130, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_READY_B_RAWNAND_READY_B = IOMUX_PAD(0x039C, 0x0134, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_READY_B_USDHC3_RESET_B = IOMUX_PAD(0x039C, 0x0134, 2, 0x0000, 0, 0), + IMX8MM_PAD_NAND_READY_B_GPIO3_IO16 = IOMUX_PAD(0x039C, 0x0134, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_WE_B_RAWNAND_WE_B = IOMUX_PAD(0x03A0, 0x0138, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_WE_B_USDHC3_CLK = IOMUX_PAD(0x03A0, 0x0138, 2 | IOMUX_CONFIG_SION, 0x0000, 0, 0), + IMX8MM_PAD_NAND_WE_B_GPIO3_IO17 = IOMUX_PAD(0x03A0, 0x0138, 5, 0x0000, 0, 0), + + IMX8MM_PAD_NAND_WP_B_RAWNAND_WP_B = IOMUX_PAD(0x03A4, 0x013C, 0, 0x0000, 0, 0), + IMX8MM_PAD_NAND_WP_B_USDHC3_CMD = IOMUX_PAD(0x03A4, 0x013C, 2, 0x0000, 0, 0), + IMX8MM_PAD_NAND_WP_B_GPIO3_IO18 = IOMUX_PAD(0x03A4, 0x013C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI5_RXFS_SAI5_RX_SYNC = IOMUX_PAD(0x03A8, 0x0140, 0, 0x04E4, 0, 0), + IMX8MM_PAD_SAI5_RXFS_SAI1_TX_DATA0 = IOMUX_PAD(0x03A8, 0x0140, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI5_RXFS_GPIO3_IO19 = IOMUX_PAD(0x03A8, 0x0140, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI5_RXC_SAI5_RX_BCLK = IOMUX_PAD(0x03AC, 0x0144, 0, 0x04D0, 0, 0), + IMX8MM_PAD_SAI5_RXC_SAI1_TX_DATA1 = IOMUX_PAD(0x03AC, 0x0144, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI5_RXC_PDM_CLK = IOMUX_PAD(0x03AC, 0x0144, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI5_RXC_GPIO3_IO20 = IOMUX_PAD(0x03AC, 0x0144, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI5_RXD0_SAI5_RX_DATA0 = IOMUX_PAD(0x03B0, 0x0148, 0, 0x04D4, 0, 0), + IMX8MM_PAD_SAI5_RXD0_SAI1_TX_DATA2 = IOMUX_PAD(0x03B0, 0x0148, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI5_RXD0_PDM_BIT_STREAM0 = IOMUX_PAD(0x03B0, 0x0148, 4, 0x0534, 0, 0), + IMX8MM_PAD_SAI5_RXD0_GPIO3_IO21 = IOMUX_PAD(0x03B0, 0x0148, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI5_RXD1_SAI5_RX_DATA1 = IOMUX_PAD(0x03B4, 0x014C, 0, 0x04D8, 0, 0), + IMX8MM_PAD_SAI5_RXD1_SAI1_TX_DATA3 = IOMUX_PAD(0x03B4, 0x014C, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI5_RXD1_SAI1_TX_SYNC = IOMUX_PAD(0x03B4, 0x014C, 2, 0x04CC, 0, 0), + IMX8MM_PAD_SAI5_RXD1_SAI5_TX_SYNC = IOMUX_PAD(0x03B4, 0x014C, 3, 0x04EC, 0, 0), + IMX8MM_PAD_SAI5_RXD1_PDM_BIT_STREAM1 = IOMUX_PAD(0x03B4, 0x014C, 4, 0x0538, 0, 0), + IMX8MM_PAD_SAI5_RXD1_GPIO3_IO22 = IOMUX_PAD(0x03B4, 0x014C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI5_RXD2_SAI5_RX_DATA2 = IOMUX_PAD(0x03B8, 0x0150, 0, 0x04DC, 0, 0), + IMX8MM_PAD_SAI5_RXD2_SAI1_TX_DATA4 = IOMUX_PAD(0x03B8, 0x0150, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI5_RXD2_SAI1_TX_SYNC = IOMUX_PAD(0x03B8, 0x0150, 2, 0x04CC, 1, 0), + IMX8MM_PAD_SAI5_RXD2_SAI5_TX_BCLK = IOMUX_PAD(0x03B8, 0x0150, 3, 0x04E8, 0, 0), + IMX8MM_PAD_SAI5_RXD2_PDM_BIT_STREAM2 = IOMUX_PAD(0x03B8, 0x0150, 4, 0x053C, 0, 0), + IMX8MM_PAD_SAI5_RXD2_GPIO3_IO23 = IOMUX_PAD(0x03B8, 0x0150, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI5_RXD3_SAI5_RX_DATA3 = IOMUX_PAD(0x03BC, 0x0154, 0, 0x04E0, 0, 0), + IMX8MM_PAD_SAI5_RXD3_SAI1_TX_DATA5 = IOMUX_PAD(0x03BC, 0x0154, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI5_RXD3_SAI1_TX_SYNC = IOMUX_PAD(0x03BC, 0x0154, 2, 0x04CC, 2, 0), + IMX8MM_PAD_SAI5_RXD3_SAI5_TX_DATA0 = IOMUX_PAD(0x03BC, 0x0154, 3, 0x0000, 0, 0), + IMX8MM_PAD_SAI5_RXD3_PDM_BIT_STREAM3 = IOMUX_PAD(0x03BC, 0x0154, 4, 0x0540, 0, 0), + IMX8MM_PAD_SAI5_RXD3_GPIO3_IO24 = IOMUX_PAD(0x03BC, 0x0154, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI5_MCLK_SAI5_MCLK = IOMUX_PAD(0x03C0, 0x0158, 0, 0x052C, 0, 0), + IMX8MM_PAD_SAI5_MCLK_SAI1_TX_BCLK = IOMUX_PAD(0x03C0, 0x0158, 1, 0x04C8, 0, 0), + IMX8MM_PAD_SAI5_MCLK_GPIO3_IO25 = IOMUX_PAD(0x03C0, 0x0158, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI5_MCLK_SRC_TESTER_ACK = IOMUX_PAD(0x03C0, 0x0158, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_RXFS_SAI1_RX_SYNC = IOMUX_PAD(0x03C4, 0x015C, 0, 0x04C4, 0, 0), + IMX8MM_PAD_SAI1_RXFS_SAI5_RX_SYNC = IOMUX_PAD(0x03C4, 0x015C, 1, 0x04E4, 1, 0), + IMX8MM_PAD_SAI1_RXFS_ARM_PLATFORM_TRACE_CLK = IOMUX_PAD(0x03C4, 0x015C, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXFS_GPIO4_IO0 = IOMUX_PAD(0x03C4, 0x015C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_RXC_SAI1_RX_BCLK = IOMUX_PAD(0x03C8, 0x0160, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXC_SAI5_RX_BCLK = IOMUX_PAD(0x03C8, 0x0160, 1, 0x04D0, 1, 0), + IMX8MM_PAD_SAI1_RXC_ARM_PLATFORM_TRACE_CTL = IOMUX_PAD(0x03C8, 0x0160, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXC_GPIO4_IO1 = IOMUX_PAD(0x03C8, 0x0160, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_RXD0_SAI1_RX_DATA0 = IOMUX_PAD(0x03CC, 0x0164, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD0_SAI5_RX_DATA0 = IOMUX_PAD(0x03CC, 0x0164, 1, 0x04D4, 1, 0), + IMX8MM_PAD_SAI1_RXD0_SAI1_TX_DATA1 = IOMUX_PAD(0x03CC, 0x0164, 2, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD0_PDM_BIT_STREAM0 = IOMUX_PAD(0x03CC, 0x0164, 3, 0x0534, 1, 0), + IMX8MM_PAD_SAI1_RXD0_ARM_PLATFORM_TRACE0 = IOMUX_PAD(0x03CC, 0x0164, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD0_GPIO4_IO2 = IOMUX_PAD(0x03CC, 0x0164, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD0_SRC_BOOT_CFG0 = IOMUX_PAD(0x03CC, 0x0164, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_RXD1_SAI1_RX_DATA1 = IOMUX_PAD(0x03D0, 0x0168, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD1_SAI5_RX_DATA1 = IOMUX_PAD(0x03D0, 0x0168, 1, 0x04D8, 1, 0), + IMX8MM_PAD_SAI1_RXD1_PDM_BIT_STREAM1 = IOMUX_PAD(0x03D0, 0x0168, 3, 0x0538, 1, 0), + IMX8MM_PAD_SAI1_RXD1_ARM_PLATFORM_TRACE1 = IOMUX_PAD(0x03D0, 0x0168, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD1_GPIO4_IO3 = IOMUX_PAD(0x03D0, 0x0168, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD1_SRC_BOOT_CFG1 = IOMUX_PAD(0x03D0, 0x0168, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_RXD2_SAI1_RX_DATA2 = IOMUX_PAD(0x03D4, 0x016C, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD2_SAI5_RX_DATA2 = IOMUX_PAD(0x03D4, 0x016C, 1, 0x04DC, 1, 0), + IMX8MM_PAD_SAI1_RXD2_PDM_BIT_STREAM2 = IOMUX_PAD(0x03D4, 0x016C, 3, 0x053C, 1, 0), + IMX8MM_PAD_SAI1_RXD2_ARM_PLATFORM_TRACE2 = IOMUX_PAD(0x03D4, 0x016C, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD2_GPIO4_IO4 = IOMUX_PAD(0x03D4, 0x016C, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD2_SRC_BOOT_CFG2 = IOMUX_PAD(0x03D4, 0x016C, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_RXD3_SAI1_RX_DATA3 = IOMUX_PAD(0x03D8, 0x0170, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD3_SAI5_RX_DATA3 = IOMUX_PAD(0x03D8, 0x0170, 1, 0x04E0, 1, 0), + IMX8MM_PAD_SAI1_RXD3_PDM_BIT_STREAM3 = IOMUX_PAD(0x03D8, 0x0170, 3, 0x0540, 1, 0), + IMX8MM_PAD_SAI1_RXD3_ARM_PLATFORM_TRACE3 = IOMUX_PAD(0x03D8, 0x0170, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD3_GPIO4_IO5 = IOMUX_PAD(0x03D8, 0x0170, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD3_SRC_BOOT_CFG3 = IOMUX_PAD(0x03D8, 0x0170, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_RXD4_SAI1_RX_DATA4 = IOMUX_PAD(0x03DC, 0x0174, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD4_SAI6_TX_BCLK = IOMUX_PAD(0x03DC, 0x0174, 1, 0x051C, 0, 0), + IMX8MM_PAD_SAI1_RXD4_SAI6_RX_BCLK = IOMUX_PAD(0x03DC, 0x0174, 2, 0x0510, 0, 0), + IMX8MM_PAD_SAI1_RXD4_ARM_PLATFORM_TRACE4 = IOMUX_PAD(0x03DC, 0x0174, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD4_GPIO4_IO6 = IOMUX_PAD(0x03DC, 0x0174, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD4_SRC_BOOT_CFG4 = IOMUX_PAD(0x03DC, 0x0174, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_RXD5_SAI1_RX_DATA5 = IOMUX_PAD(0x03E0, 0x0178, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD5_SAI6_TX_DATA0 = IOMUX_PAD(0x03E0, 0x0178, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD5_SAI6_RX_DATA0 = IOMUX_PAD(0x03E0, 0x0178, 2, 0x0514, 0, 0), + IMX8MM_PAD_SAI1_RXD5_SAI1_RX_SYNC = IOMUX_PAD(0x03E0, 0x0178, 3, 0x04C4, 1, 0), + IMX8MM_PAD_SAI1_RXD5_ARM_PLATFORM_TRACE5 = IOMUX_PAD(0x03E0, 0x0178, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD5_GPIO4_IO7 = IOMUX_PAD(0x03E0, 0x0178, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD5_SRC_BOOT_CFG5 = IOMUX_PAD(0x03E0, 0x0178, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_RXD6_SAI1_RX_DATA6 = IOMUX_PAD(0x03E4, 0x017C, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD6_SAI6_TX_SYNC = IOMUX_PAD(0x03E4, 0x017C, 1, 0x0520, 0, 0), + IMX8MM_PAD_SAI1_RXD6_SAI6_RX_SYNC = IOMUX_PAD(0x03E4, 0x017C, 2, 0x0518, 0, 0), + IMX8MM_PAD_SAI1_RXD6_ARM_PLATFORM_TRACE6 = IOMUX_PAD(0x03E4, 0x017C, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD6_GPIO4_IO8 = IOMUX_PAD(0x03E4, 0x017C, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD6_SRC_BOOT_CFG6 = IOMUX_PAD(0x03E4, 0x017C, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_RXD7_SAI1_RX_DATA7 = IOMUX_PAD(0x03E8, 0x0180, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD7_SAI6_MCLK = IOMUX_PAD(0x03E8, 0x0180, 1, 0x0530, 0, 0), + IMX8MM_PAD_SAI1_RXD7_SAI1_TX_SYNC = IOMUX_PAD(0x03E8, 0x0180, 2, 0x04CC, 4, 0), + IMX8MM_PAD_SAI1_RXD7_SAI1_TX_DATA4 = IOMUX_PAD(0x03E8, 0x0180, 3, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD7_ARM_PLATFORM_TRACE7 = IOMUX_PAD(0x03E8, 0x0180, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD7_GPIO4_IO9 = IOMUX_PAD(0x03E8, 0x0180, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_RXD7_SRC_BOOT_CFG7 = IOMUX_PAD(0x03E8, 0x0180, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_TXFS_SAI1_TX_SYNC = IOMUX_PAD(0x03EC, 0x0184, 0, 0x04CC, 3, 0), + IMX8MM_PAD_SAI1_TXFS_SAI5_TX_SYNC = IOMUX_PAD(0x03EC, 0x0184, 1, 0x04EC, 1, 0), + IMX8MM_PAD_SAI1_TXFS_ARM_PLATFORM_EVENTO = IOMUX_PAD(0x03EC, 0x0184, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXFS_GPIO4_IO10 = IOMUX_PAD(0x03EC, 0x0184, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_TXC_SAI1_TX_BCLK = IOMUX_PAD(0x03F0, 0x0188, 0, 0x04C8, 1, 0), + IMX8MM_PAD_SAI1_TXC_SAI5_TX_BCLK = IOMUX_PAD(0x03F0, 0x0188, 1, 0x04E8, 1, 0), + IMX8MM_PAD_SAI1_TXC_ARM_PLATFORM_EVENTI = IOMUX_PAD(0x03F0, 0x0188, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXC_GPIO4_IO11 = IOMUX_PAD(0x03F0, 0x0188, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_TXD0_SAI1_TX_DATA0 = IOMUX_PAD(0x03F4, 0x018C, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD0_SAI5_TX_DATA0 = IOMUX_PAD(0x03F4, 0x018C, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD0_ARM_PLATFORM_TRACE8 = IOMUX_PAD(0x03F4, 0x018C, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD0_GPIO4_IO12 = IOMUX_PAD(0x03F4, 0x018C, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD0_SRC_BOOT_CFG8 = IOMUX_PAD(0x03F4, 0x018C, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_TXD1_SAI1_TX_DATA1 = IOMUX_PAD(0x03F8, 0x0190, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD1_SAI5_TX_DATA1 = IOMUX_PAD(0x03F8, 0x0190, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD1_ARM_PLATFORM_TRACE9 = IOMUX_PAD(0x03F8, 0x0190, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD1_GPIO4_IO13 = IOMUX_PAD(0x03F8, 0x0190, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD1_SRC_BOOT_CFG9 = IOMUX_PAD(0x03F8, 0x0190, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_TXD2_SAI1_TX_DATA2 = IOMUX_PAD(0x03FC, 0x0194, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD2_SAI5_TX_DATA2 = IOMUX_PAD(0x03FC, 0x0194, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD2_ARM_PLATFORM_TRACE10 = IOMUX_PAD(0x03FC, 0x0194, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD2_GPIO4_IO14 = IOMUX_PAD(0x03FC, 0x0194, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD2_SRC_BOOT_CFG10 = IOMUX_PAD(0x03FC, 0x0194, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_TXD3_SAI1_TX_DATA3 = IOMUX_PAD(0x0400, 0x0198, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD3_SAI5_TX_DATA3 = IOMUX_PAD(0x0400, 0x0198, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD3_ARM_PLATFORM_TRACE11 = IOMUX_PAD(0x0400, 0x0198, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD3_GPIO4_IO15 = IOMUX_PAD(0x0400, 0x0198, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD3_SRC_BOOT_CFG11 = IOMUX_PAD(0x0400, 0x0198, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_TXD4_SAI1_TX_DATA4 = IOMUX_PAD(0x0404, 0x019C, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD4_SAI6_RX_BCLK = IOMUX_PAD(0x0404, 0x019C, 1, 0x0510, 1, 0), + IMX8MM_PAD_SAI1_TXD4_SAI6_TX_BCLK = IOMUX_PAD(0x0404, 0x019C, 2, 0x051C, 1, 0), + IMX8MM_PAD_SAI1_TXD4_ARM_PLATFORM_TRACE12 = IOMUX_PAD(0x0404, 0x019C, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD4_GPIO4_IO16 = IOMUX_PAD(0x0404, 0x019C, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD4_SRC_BOOT_CFG12 = IOMUX_PAD(0x0404, 0x019C, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_TXD5_SAI1_TX_DATA5 = IOMUX_PAD(0x0408, 0x01A0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD5_SAI6_RX_DATA0 = IOMUX_PAD(0x0408, 0x01A0, 1, 0x0514, 1, 0), + IMX8MM_PAD_SAI1_TXD5_SAI6_TX_DATA0 = IOMUX_PAD(0x0408, 0x01A0, 2, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD5_ARM_PLATFORM_TRACE13 = IOMUX_PAD(0x0408, 0x01A0, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD5_GPIO4_IO17 = IOMUX_PAD(0x0408, 0x01A0, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD5_SRC_BOOT_CFG13 = IOMUX_PAD(0x0408, 0x01A0, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_TXD6_SAI1_TX_DATA6 = IOMUX_PAD(0x040C, 0x01A4, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD6_SAI6_RX_SYNC = IOMUX_PAD(0x040C, 0x01A4, 1, 0x0518, 1, 0), + IMX8MM_PAD_SAI1_TXD6_SAI6_TX_SYNC = IOMUX_PAD(0x040C, 0x01A4, 2, 0x0520, 1, 0), + IMX8MM_PAD_SAI1_TXD6_ARM_PLATFORM_TRACE14 = IOMUX_PAD(0x040C, 0x01A4, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD6_GPIO4_IO18 = IOMUX_PAD(0x040C, 0x01A4, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD6_SRC_BOOT_CFG14 = IOMUX_PAD(0x040C, 0x01A4, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_TXD7_SAI1_TX_DATA7 = IOMUX_PAD(0x0410, 0x01A8, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD7_SAI6_MCLK = IOMUX_PAD(0x0410, 0x01A8, 1, 0x0530, 1, 0), + IMX8MM_PAD_SAI1_TXD7_PDM_CLK = IOMUX_PAD(0x0410, 0x01A8, 3, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD7_ARM_PLATFORM_TRACE15 = IOMUX_PAD(0x0410, 0x01A8, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD7_GPIO4_IO19 = IOMUX_PAD(0x0410, 0x01A8, 5, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_TXD7_SRC_BOOT_CFG15 = IOMUX_PAD(0x0410, 0x01A8, 6, 0x0000, 0, 0), + + IMX8MM_PAD_SAI1_MCLK_SAI1_MCLK = IOMUX_PAD(0x0414, 0x01AC, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_MCLK_SAI5_MCLK = IOMUX_PAD(0x0414, 0x01AC, 1, 0x052C, 1, 0), + IMX8MM_PAD_SAI1_MCLK_SAI1_TX_BCLK = IOMUX_PAD(0x0414, 0x01AC, 2, 0x04C8, 2, 0), + IMX8MM_PAD_SAI1_MCLK_PDM_CLK = IOMUX_PAD(0x0414, 0x01AC, 3, 0x0000, 0, 0), + IMX8MM_PAD_SAI1_MCLK_GPIO4_IO20 = IOMUX_PAD(0x0414, 0x01AC, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI2_RXFS_SAI2_RX_SYNC = IOMUX_PAD(0x0418, 0x01B0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_RXFS_SAI5_TX_SYNC = IOMUX_PAD(0x0418, 0x01B0, 1, 0x04EC, 2, 0), + IMX8MM_PAD_SAI2_RXFS_SAI5_TX_DATA1 = IOMUX_PAD(0x0418, 0x01B0, 2, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_RXFS_SAI2_RX_DATA1 = IOMUX_PAD(0x0418, 0x01B0, 3, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_RXFS_UART1_TX = IOMUX_PAD(0x0418, 0x01B0, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_RXFS_UART1_RX = IOMUX_PAD(0x0418, 0x01B0, 4, 0x04F4, 2, 0), + IMX8MM_PAD_SAI2_RXFS_GPIO4_IO21 = IOMUX_PAD(0x0418, 0x01B0, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI2_RXC_SAI2_RX_BCLK = IOMUX_PAD(0x041C, 0x01B4, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_RXC_SAI5_TX_BCLK = IOMUX_PAD(0x041C, 0x01B4, 1, 0x04E8, 2, 0), + IMX8MM_PAD_SAI2_RXC_UART1_RX = IOMUX_PAD(0x041C, 0x01B4, 4, 0x04F4, 3, 0), + IMX8MM_PAD_SAI2_RXC_UART1_TX = IOMUX_PAD(0x041C, 0x01B4, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_RXC_GPIO4_IO22 = IOMUX_PAD(0x041C, 0x01B4, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI2_RXD0_SAI2_RX_DATA0 = IOMUX_PAD(0x0420, 0x01B8, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_RXD0_SAI5_TX_DATA0 = IOMUX_PAD(0x0420, 0x01B8, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_RXD0_UART1_RTS_B = IOMUX_PAD(0x0420, 0x01B8, 4, 0x04F0, 2, 0), + IMX8MM_PAD_SAI2_RXD0_UART1_CTS_B = IOMUX_PAD(0x0420, 0x01B8, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_RXD0_GPIO4_IO23 = IOMUX_PAD(0x0420, 0x01B8, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI2_TXFS_SAI2_TX_SYNC = IOMUX_PAD(0x0424, 0x01BC, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_TXFS_SAI5_TX_DATA1 = IOMUX_PAD(0x0424, 0x01BC, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_TXFS_SAI2_TX_DATA1 = IOMUX_PAD(0x0424, 0x01BC, 3, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_TXFS_UART1_CTS_B = IOMUX_PAD(0x0424, 0x01BC, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_TXFS_UART1_RTS_B = IOMUX_PAD(0x0424, 0x01BC, 4, 0x04F0, 3, 0), + IMX8MM_PAD_SAI2_TXFS_GPIO4_IO24 = IOMUX_PAD(0x0424, 0x01BC, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI2_TXC_SAI2_TX_BCLK = IOMUX_PAD(0x0428, 0x01C0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_TXC_SAI5_TX_DATA2 = IOMUX_PAD(0x0428, 0x01C0, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_TXC_GPIO4_IO25 = IOMUX_PAD(0x0428, 0x01C0, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI2_TXD0_SAI2_TX_DATA0 = IOMUX_PAD(0x042C, 0x01C4, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_TXD0_SAI5_TX_DATA3 = IOMUX_PAD(0x042C, 0x01C4, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_TXD0_GPIO4_IO26 = IOMUX_PAD(0x042C, 0x01C4, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI2_MCLK_SAI2_MCLK = IOMUX_PAD(0x0430, 0x01C8, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI2_MCLK_SAI5_MCLK = IOMUX_PAD(0x0430, 0x01C8, 1, 0x052C, 2, 0), + IMX8MM_PAD_SAI2_MCLK_GPIO4_IO27 = IOMUX_PAD(0x0430, 0x01C8, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI3_RXFS_SAI3_RX_SYNC = IOMUX_PAD(0x0434, 0x01CC, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_RXFS_GPT1_CAPTURE1 = IOMUX_PAD(0x0434, 0x01CC, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_RXFS_SAI5_RX_SYNC = IOMUX_PAD(0x0434, 0x01CC, 2, 0x04E4, 2, 0), + IMX8MM_PAD_SAI3_RXFS_SAI3_RX_DATA1 = IOMUX_PAD(0x0434, 0x01CC, 3, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_RXFS_GPIO4_IO28 = IOMUX_PAD(0x0434, 0x01CC, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI3_RXC_SAI3_RX_BCLK = IOMUX_PAD(0x0438, 0x01D0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_RXC_GPT1_CLK = IOMUX_PAD(0x0438, 0x01D0, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_RXC_SAI5_RX_BCLK = IOMUX_PAD(0x0438, 0x01D0, 2, 0x04D0, 2, 0), + IMX8MM_PAD_SAI3_RXC_UART2_CTS_B = IOMUX_PAD(0x0438, 0x01D0, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_RXC_UART2_RTS_B = IOMUX_PAD(0x0438, 0x01D0, 4, 0x04F8, 2, 0), + IMX8MM_PAD_SAI3_RXC_GPIO4_IO29 = IOMUX_PAD(0x0438, 0x01D0, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI3_RXD_SAI3_RX_DATA0 = IOMUX_PAD(0x043C, 0x01D4, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_RXD_GPT1_COMPARE1 = IOMUX_PAD(0x043C, 0x01D4, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_RXD_SAI5_RX_DATA0 = IOMUX_PAD(0x043C, 0x01D4, 2, 0x04D4, 2, 0), + IMX8MM_PAD_SAI3_RXD_UART2_RTS_B = IOMUX_PAD(0x043C, 0x01D4, 4, 0x04F8, 3, 0), + IMX8MM_PAD_SAI3_RXD_UART2_CTS_B = IOMUX_PAD(0x043C, 0x01D4, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_RXD_GPIO4_IO30 = IOMUX_PAD(0x043C, 0x01D4, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI3_TXFS_SAI3_TX_SYNC = IOMUX_PAD(0x0440, 0x01D8, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_TXFS_GPT1_CAPTURE2 = IOMUX_PAD(0x0440, 0x01D8, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_TXFS_SAI5_RX_DATA1 = IOMUX_PAD(0x0440, 0x01D8, 2, 0x04D8, 2, 0), + IMX8MM_PAD_SAI3_TXFS_SAI3_TX_DATA1 = IOMUX_PAD(0x0440, 0x01D8, 3, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_TXFS_UART2_RX = IOMUX_PAD(0x0440, 0x01D8, 4, 0x04FC, 2, 0), + IMX8MM_PAD_SAI3_TXFS_UART2_TX = IOMUX_PAD(0x0440, 0x01D8, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_TXFS_GPIO4_IO31 = IOMUX_PAD(0x0440, 0x01D8, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI3_TXC_SAI3_TX_BCLK = IOMUX_PAD(0x0444, 0x01DC, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_TXC_GPT1_COMPARE2 = IOMUX_PAD(0x0444, 0x01DC, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_TXC_SAI5_RX_DATA2 = IOMUX_PAD(0x0444, 0x01DC, 2, 0x04DC, 2, 0), + IMX8MM_PAD_SAI3_TXC_UART2_TX = IOMUX_PAD(0x0444, 0x01DC, 4, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_TXC_UART2_RX = IOMUX_PAD(0x0444, 0x01DC, 4, 0x04FC, 3, 0), + IMX8MM_PAD_SAI3_TXC_GPIO5_IO0 = IOMUX_PAD(0x0444, 0x01DC, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI3_TXD_SAI3_TX_DATA0 = IOMUX_PAD(0x0448, 0x01E0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_TXD_GPT1_COMPARE3 = IOMUX_PAD(0x0448, 0x01E0, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_TXD_SAI5_RX_DATA3 = IOMUX_PAD(0x0448, 0x01E0, 2, 0x04E0, 2, 0), + IMX8MM_PAD_SAI3_TXD_GPIO5_IO1 = IOMUX_PAD(0x0448, 0x01E0, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SAI3_MCLK_SAI3_MCLK = IOMUX_PAD(0x044C, 0x01E4, 0, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_MCLK_PWM4_OUT = IOMUX_PAD(0x044C, 0x01E4, 1, 0x0000, 0, 0), + IMX8MM_PAD_SAI3_MCLK_SAI5_MCLK = IOMUX_PAD(0x044C, 0x01E4, 2, 0x052C, 3, 0), + IMX8MM_PAD_SAI3_MCLK_GPIO5_IO2 = IOMUX_PAD(0x044C, 0x01E4, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SPDIF_TX_SPDIF1_OUT = IOMUX_PAD(0x0450, 0x01E8, 0, 0x0000, 0, 0), + IMX8MM_PAD_SPDIF_TX_PWM3_OUT = IOMUX_PAD(0x0450, 0x01E8, 1, 0x0000, 0, 0), + IMX8MM_PAD_SPDIF_TX_GPIO5_IO3 = IOMUX_PAD(0x0450, 0x01E8, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SPDIF_RX_SPDIF1_IN = IOMUX_PAD(0x0454, 0x01EC, 0, 0x0000, 0, 0), + IMX8MM_PAD_SPDIF_RX_PWM2_OUT = IOMUX_PAD(0x0454, 0x01EC, 1, 0x0000, 0, 0), + IMX8MM_PAD_SPDIF_RX_GPIO5_IO4 = IOMUX_PAD(0x0454, 0x01EC, 5, 0x0000, 0, 0), + + IMX8MM_PAD_SPDIF_EXT_CLK_SPDIF1_EXT_CLK = IOMUX_PAD(0x0458, 0x01F0, 0, 0x0000, 0, 0), + IMX8MM_PAD_SPDIF_EXT_CLK_PWM1_OUT = IOMUX_PAD(0x0458, 0x01F0, 1, 0x0000, 0, 0), + IMX8MM_PAD_SPDIF_EXT_CLK_GPIO5_IO5 = IOMUX_PAD(0x0458, 0x01F0, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ECSPI1_SCLK_ECSPI1_SCLK = IOMUX_PAD(0x045C, 0x01F4, 0, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI1_SCLK_UART3_RX = IOMUX_PAD(0x045C, 0x01F4, 1, 0x0504, 0, 0), + IMX8MM_PAD_ECSPI1_SCLK_UART3_TX = IOMUX_PAD(0x045C, 0x01F4, 1, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI1_SCLK_GPIO5_IO6 = IOMUX_PAD(0x045C, 0x01F4, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ECSPI1_MOSI_ECSPI1_MOSI = IOMUX_PAD(0x0460, 0x01F8, 0, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI1_MOSI_UART3_TX = IOMUX_PAD(0x0460, 0x01F8, 1, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI1_MOSI_UART3_RX = IOMUX_PAD(0x0460, 0x01F8, 1, 0x0504, 1, 0), + IMX8MM_PAD_ECSPI1_MOSI_GPIO5_IO7 = IOMUX_PAD(0x0460, 0x01F8, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ECSPI1_MISO_ECSPI1_MISO = IOMUX_PAD(0x0464, 0x01FC, 0, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI1_MISO_UART3_CTS_B = IOMUX_PAD(0x0464, 0x01FC, 1, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI1_MISO_UART3_RTS_B = IOMUX_PAD(0x0464, 0x01FC, 1, 0x0500, 0, 0), + IMX8MM_PAD_ECSPI1_MISO_GPIO5_IO8 = IOMUX_PAD(0x0464, 0x01FC, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ECSPI1_SS0_ECSPI1_SS0 = IOMUX_PAD(0x0468, 0x0200, 0, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI1_SS0_UART3_RTS_B = IOMUX_PAD(0x0468, 0x0200, 1, 0x0500, 1, 0), + IMX8MM_PAD_ECSPI1_SS0_UART3_CTS_B = IOMUX_PAD(0x0468, 0x0200, 1, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI1_SS0_GPIO5_IO9 = IOMUX_PAD(0x0468, 0x0200, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ECSPI2_SCLK_ECSPI2_SCLK = IOMUX_PAD(0x046C, 0x0204, 0, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI2_SCLK_UART4_RX = IOMUX_PAD(0x046C, 0x0204, 1, 0x050C, 0, 0), + IMX8MM_PAD_ECSPI2_SCLK_UART4_TX = IOMUX_PAD(0x046C, 0x0204, 1, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI2_SCLK_GPIO5_IO10 = IOMUX_PAD(0x046C, 0x0204, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ECSPI2_MOSI_ECSPI2_MOSI = IOMUX_PAD(0x0470, 0x0208, 0, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI2_MOSI_UART4_TX = IOMUX_PAD(0x0470, 0x0208, 1, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI2_MOSI_UART4_RX = IOMUX_PAD(0x0470, 0x0208, 1, 0x050C, 1, 0), + IMX8MM_PAD_ECSPI2_MOSI_GPIO5_IO11 = IOMUX_PAD(0x0470, 0x0208, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ECSPI2_MISO_ECSPI2_MISO = IOMUX_PAD(0x0474, 0x020C, 0, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI2_MISO_UART4_CTS_B = IOMUX_PAD(0x0474, 0x020C, 1, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI2_MISO_UART4_RTS_B = IOMUX_PAD(0x0474, 0x020C, 1, 0x0508, 0, 0), + IMX8MM_PAD_ECSPI2_MISO_GPIO5_IO12 = IOMUX_PAD(0x0474, 0x020C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_ECSPI2_SS0_ECSPI2_SS0 = IOMUX_PAD(0x0478, 0x0210, 0, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI2_SS0_UART4_RTS_B = IOMUX_PAD(0x0478, 0x0210, 1, 0x0508, 1, 0), + IMX8MM_PAD_ECSPI2_SS0_UART4_CTS_B = IOMUX_PAD(0x0478, 0x0210, 1, 0x0000, 0, 0), + IMX8MM_PAD_ECSPI2_SS0_GPIO5_IO13 = IOMUX_PAD(0x0478, 0x0210, 5, 0x0000, 0, 0), + + IMX8MM_PAD_I2C1_SCL_I2C1_SCL = IOMUX_PAD(0x047C, 0x0214, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), + IMX8MM_PAD_I2C1_SCL_ENET1_MDC = IOMUX_PAD(0x047C, 0x0214, 1, 0x0000, 0, 0), + IMX8MM_PAD_I2C1_SCL_GPIO5_IO14 = IOMUX_PAD(0x047C, 0x0214, 5, 0x0000, 0, 0), + + IMX8MM_PAD_I2C1_SDA_I2C1_SDA = IOMUX_PAD(0x0480, 0x0218, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), + IMX8MM_PAD_I2C1_SDA_ENET1_MDIO = IOMUX_PAD(0x0480, 0x0218, 1, 0x04C0, 2, 0), + IMX8MM_PAD_I2C1_SDA_GPIO5_IO15 = IOMUX_PAD(0x0480, 0x0218, 5, 0x0000, 0, 0), + + IMX8MM_PAD_I2C2_SCL_I2C2_SCL = IOMUX_PAD(0x0484, 0x021C, 0, 0x0000, 0, 0), + IMX8MM_PAD_I2C2_SCL_ENET1_1588_EVENT1_IN = IOMUX_PAD(0x0484, 0x021C, 1, 0x0000, 0, 0), + IMX8MM_PAD_I2C2_SCL_USDHC3_CD_B = IOMUX_PAD(0x0484, 0x021C, 2, 0x0544, 1, 0), + IMX8MM_PAD_I2C2_SCL_GPIO5_IO16 = IOMUX_PAD(0x0484, 0x021C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_I2C2_SDA_I2C2_SDA = IOMUX_PAD(0x0488, 0x0220, 0, 0x0000, 0, 0), + IMX8MM_PAD_I2C2_SDA_ENET1_1588_EVENT1_OUT = IOMUX_PAD(0x0488, 0x0220, 1, 0x0000, 0, 0), + IMX8MM_PAD_I2C2_SDA_USDHC3_WP = IOMUX_PAD(0x0488, 0x0220, 2, 0x0548, 1, 0), + IMX8MM_PAD_I2C2_SDA_GPIO5_IO17 = IOMUX_PAD(0x0488, 0x0220, 5, 0x0000, 0, 0), + + IMX8MM_PAD_I2C3_SCL_I2C3_SCL = IOMUX_PAD(0x048C, 0x0224, 0, 0x0000, 0, 0), + IMX8MM_PAD_I2C3_SCL_PWM4_OUT = IOMUX_PAD(0x048C, 0x0224, 1, 0x0000, 0, 0), + IMX8MM_PAD_I2C3_SCL_GPT2_CLK = IOMUX_PAD(0x048C, 0x0224, 2, 0x0000, 0, 0), + IMX8MM_PAD_I2C3_SCL_GPIO5_IO18 = IOMUX_PAD(0x048C, 0x0224, 5, 0x0000, 0, 0), + + IMX8MM_PAD_I2C3_SDA_I2C3_SDA = IOMUX_PAD(0x0490, 0x0228, 0, 0x0000, 0, 0), + IMX8MM_PAD_I2C3_SDA_PWM3_OUT = IOMUX_PAD(0x0490, 0x0228, 1, 0x0000, 0, 0), + IMX8MM_PAD_I2C3_SDA_GPT3_CLK = IOMUX_PAD(0x0490, 0x0228, 2, 0x0000, 0, 0), + IMX8MM_PAD_I2C3_SDA_GPIO5_IO19 = IOMUX_PAD(0x0490, 0x0228, 5, 0x0000, 0, 0), + + IMX8MM_PAD_I2C4_SCL_I2C4_SCL = IOMUX_PAD(0x0494, 0x022C, 0, 0x0000, 0, 0), + IMX8MM_PAD_I2C4_SCL_PWM2_OUT = IOMUX_PAD(0x0494, 0x022C, 1, 0x0000, 0, 0), + IMX8MM_PAD_I2C4_SCL_PCIE1_CLKREQ_B = IOMUX_PAD(0x0494, 0x022C, 2, 0x0524, 0, 0), + IMX8MM_PAD_I2C4_SCL_GPIO5_IO20 = IOMUX_PAD(0x0494, 0x022C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_I2C4_SDA_I2C4_SDA = IOMUX_PAD(0x0498, 0x0230, 0, 0x0000, 0, 0), + IMX8MM_PAD_I2C4_SDA_PWM1_OUT = IOMUX_PAD(0x0498, 0x0230, 1, 0x0000, 0, 0), + IMX8MM_PAD_I2C4_SDA_GPIO5_IO21 = IOMUX_PAD(0x0498, 0x0230, 5, 0x0000, 0, 0), + + IMX8MM_PAD_UART1_RXD_UART1_RX = IOMUX_PAD(0x049C, 0x0234, 0, 0x04F4, 0, 0), + IMX8MM_PAD_UART1_RXD_UART1_TX = IOMUX_PAD(0x049C, 0x0234, 0, 0x0000, 0, 0), + IMX8MM_PAD_UART1_RXD_ECSPI3_SCLK = IOMUX_PAD(0x049C, 0x0234, 1, 0x0000, 0, 0), + IMX8MM_PAD_UART1_RXD_GPIO5_IO22 = IOMUX_PAD(0x049C, 0x0234, 5, 0x0000, 0, 0), + + IMX8MM_PAD_UART1_TXD_UART1_TX = IOMUX_PAD(0x04A0, 0x0238, 0, 0x0000, 0, 0), + IMX8MM_PAD_UART1_TXD_UART1_RX = IOMUX_PAD(0x04A0, 0x0238, 0, 0x04F4, 1, 0), + IMX8MM_PAD_UART1_TXD_ECSPI3_MOSI = IOMUX_PAD(0x04A0, 0x0238, 1, 0x0000, 0, 0), + IMX8MM_PAD_UART1_TXD_GPIO5_IO23 = IOMUX_PAD(0x04A0, 0x0238, 5, 0x0000, 0, 0), + + IMX8MM_PAD_UART2_RXD_UART2_RX = IOMUX_PAD(0x04A4, 0x023C, 0, 0x04FC, 0, 0), + IMX8MM_PAD_UART2_RXD_UART2_TX = IOMUX_PAD(0x04A4, 0x023C, 0, 0x0000, 0, 0), + IMX8MM_PAD_UART2_RXD_ECSPI3_MISO = IOMUX_PAD(0x04A4, 0x023C, 1, 0x0000, 0, 0), + IMX8MM_PAD_UART2_RXD_GPIO5_IO24 = IOMUX_PAD(0x04A4, 0x023C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_UART2_TXD_UART2_TX = IOMUX_PAD(0x04A8, 0x0240, 0, 0x0000, 0, 0), + IMX8MM_PAD_UART2_TXD_UART2_RX = IOMUX_PAD(0x04A8, 0x0240, 0, 0x04FC, 1, 0), + IMX8MM_PAD_UART2_TXD_ECSPI3_SS0 = IOMUX_PAD(0x04A8, 0x0240, 1, 0x0000, 0, 0), + IMX8MM_PAD_UART2_TXD_GPIO5_IO25 = IOMUX_PAD(0x04A8, 0x0240, 5, 0x0000, 0, 0), + + IMX8MM_PAD_UART3_RXD_UART3_RX = IOMUX_PAD(0x04AC, 0x0244, 0, 0x0504, 2, 0), + IMX8MM_PAD_UART3_RXD_UART3_TX = IOMUX_PAD(0x04AC, 0x0244, 0, 0x0000, 0, 0), + IMX8MM_PAD_UART3_RXD_UART1_CTS_B = IOMUX_PAD(0x04AC, 0x0244, 1, 0x0000, 0, 0), + IMX8MM_PAD_UART3_RXD_UART1_RTS_B = IOMUX_PAD(0x04AC, 0x0244, 1, 0x04F0, 0, 0), + IMX8MM_PAD_UART3_RXD_USDHC3_RESET_B = IOMUX_PAD(0x04AC, 0x0244, 2, 0x0000, 0, 0), + IMX8MM_PAD_UART3_RXD_GPIO5_IO26 = IOMUX_PAD(0x04AC, 0x0244, 5, 0x0000, 0, 0), + + IMX8MM_PAD_UART3_TXD_UART3_TX = IOMUX_PAD(0x04B0, 0x0248, 0, 0x0000, 0, 0), + IMX8MM_PAD_UART3_TXD_UART3_RX = IOMUX_PAD(0x04B0, 0x0248, 0, 0x0504, 3, 0), + IMX8MM_PAD_UART3_TXD_UART1_RTS_B = IOMUX_PAD(0x04B0, 0x0248, 1, 0x04F0, 1, 0), + IMX8MM_PAD_UART3_TXD_UART1_CTS_B = IOMUX_PAD(0x04B0, 0x0248, 1, 0x0000, 0, 0), + IMX8MM_PAD_UART3_TXD_USDHC3_VSELECT = IOMUX_PAD(0x04B0, 0x0248, 2, 0x0000, 0, 0), + IMX8MM_PAD_UART3_TXD_GPIO5_IO27 = IOMUX_PAD(0x04B0, 0x0248, 5, 0x0000, 0, 0), + + IMX8MM_PAD_UART4_RXD_UART4_RX = IOMUX_PAD(0x04B4, 0x024C, 0, 0x050C, 2, 0), + IMX8MM_PAD_UART4_RXD_UART4_TX = IOMUX_PAD(0x04B4, 0x024C, 0, 0x0000, 0, 0), + IMX8MM_PAD_UART4_RXD_UART2_CTS_B = IOMUX_PAD(0x04B4, 0x024C, 1, 0x0000, 0, 0), + IMX8MM_PAD_UART4_RXD_UART2_RTS_B = IOMUX_PAD(0x04B4, 0x024C, 1, 0x04F8, 0, 0), + IMX8MM_PAD_UART4_RXD_PCIE1_CLKREQ_B = IOMUX_PAD(0x04B4, 0x024C, 2, 0x0524, 1, 0), + IMX8MM_PAD_UART4_RXD_GPIO5_IO28 = IOMUX_PAD(0x04B4, 0x024C, 5, 0x0000, 0, 0), + + IMX8MM_PAD_UART4_TXD_UART4_TX = IOMUX_PAD(0x04B8, 0x0250, 0, 0x0000, 0, 0), + IMX8MM_PAD_UART4_TXD_UART4_RX = IOMUX_PAD(0x04B8, 0x0250, 0, 0x050C, 3, 0), + IMX8MM_PAD_UART4_TXD_UART2_RTS_B = IOMUX_PAD(0x04B8, 0x0250, 1, 0x04F8, 1, 0), + IMX8MM_PAD_UART4_TXD_UART2_CTS_B = IOMUX_PAD(0x04B8, 0x0250, 1, 0x0000, 0, 0), + IMX8MM_PAD_UART4_TXD_GPIO5_IO29 = IOMUX_PAD(0x04B8, 0x0250, 5, 0x0000, 0, 0), +}; \ No newline at end of file From 2995bd8e847020b25993ece876e7754206139c4a Mon Sep 17 00:00:00 2001 From: Lucy Date: Wed, 13 Oct 2021 14:52:23 +1100 Subject: [PATCH 5/8] Created loop in irq handler to ensure we don't miss any irqs Signed-off-by: Lucy --- libethdrivers/include/ethdrivers/imx6.h | 3 ++ libethdrivers/src/plat/imx6/imx6.c | 45 ++++++++++++++++++------- 2 files changed, 35 insertions(+), 13 deletions(-) diff --git a/libethdrivers/include/ethdrivers/imx6.h b/libethdrivers/include/ethdrivers/imx6.h index f3923ffea..ce5b430b5 100644 --- a/libethdrivers/include/ethdrivers/imx6.h +++ b/libethdrivers/include/ethdrivers/imx6.h @@ -7,4 +7,7 @@ #pragma once +void reset_irqs(); +void get_irqs(); + /* nothing here */ diff --git a/libethdrivers/src/plat/imx6/imx6.c b/libethdrivers/src/plat/imx6/imx6.c index 2ba21a43d..0bb170ee1 100644 --- a/libethdrivers/src/plat/imx6/imx6.c +++ b/libethdrivers/src/plat/imx6/imx6.c @@ -30,6 +30,9 @@ #define BUF_SIZE MAX_PKT_SIZE #define DMA_ALIGN 32 +uint32_t transmit_irq = 0; +uint32_t receive_irq = 0; + struct descriptor { /* NOTE: little endian packing: len before stat */ #if BYTE_ORDER == LITTLE_ENDIAN @@ -417,7 +420,7 @@ static void complete_tx(imx6_eth_driver_t *dev) enet_tx_enable(dev->enet); } //ZF_LOGF("The buffer was not sent and we can't release any buffers."); - //enet_print_state(dev->enet);; + //enet_print_state(dev->enet); } /* Go to next buffer, handle roll-over. */ @@ -464,19 +467,25 @@ static void handle_irq(struct eth_driver *driver, int irq) struct enet *enet = dev->enet; assert(enet); + uint32_t e = enet_clr_events(enet, IRQ_MASK); - if (e & NETIRQ_TXF) { - complete_tx(dev); - } - if (e & NETIRQ_RXF) { - complete_rx(dev); - fill_rx_bufs(dev); - } - if (e & NETIRQ_EBERR) { - ZF_LOGE("Error: System bus/uDMA"); - // ethif_print_state(netif_get_eth_driver(netif)); - assert(0); - while (1); + while (e & IRQ_MASK) { + if (e & NETIRQ_TXF) { + //transmit_irq++; + complete_tx(dev); + } + if (e & NETIRQ_RXF) { + //receive_irq++; + complete_rx(dev); + fill_rx_bufs(dev); + } + if (e & NETIRQ_EBERR) { + ZF_LOGE("Error: System bus/uDMA"); + // ethif_print_state(netif_get_eth_driver(netif)); + assert(0); + while (1); + } + e = enet_clr_events(enet, IRQ_MASK); } } @@ -983,6 +992,16 @@ int ethif_imx_init_module(ps_io_ops_t *io_ops, const char *device_path) } +void reset_irqs() { + transmit_irq = 0; + receive_irq = 0; +} + +void get_irqs() { + printf("Transmit IRQs = %d\n", transmit_irq); + printf("Receive IRQs = %d\n", receive_irq); +} + static const char *compatible_strings[] = { /* Other i.MX platforms may also be compatible but the platforms that have * been tested are: From 947642a4d956189bcfb6108eb6f692f9e843c68c Mon Sep 17 00:00:00 2001 From: Lucy Date: Fri, 22 Oct 2021 13:08:45 +1100 Subject: [PATCH 6/8] Fixed small bug in complete_tx Signed-off-by: Lucy --- libethdrivers/include/ethdrivers/imx6.h | 3 +- libethdrivers/src/plat/imx6/enet.c | 10 +++- libethdrivers/src/plat/imx6/enet.h | 2 + libethdrivers/src/plat/imx6/imx6.c | 48 +++++++------------ libethdrivers/src/plat/imx6/uboot/imx_board.c | 8 +++- 5 files changed, 34 insertions(+), 37 deletions(-) diff --git a/libethdrivers/include/ethdrivers/imx6.h b/libethdrivers/include/ethdrivers/imx6.h index ce5b430b5..3968ad8b5 100644 --- a/libethdrivers/include/ethdrivers/imx6.h +++ b/libethdrivers/include/ethdrivers/imx6.h @@ -7,7 +7,6 @@ #pragma once -void reset_irqs(); -void get_irqs(); +struct eth_driver; /* nothing here */ diff --git a/libethdrivers/src/plat/imx6/enet.c b/libethdrivers/src/plat/imx6/enet.c index db379d492..fa8540469 100644 --- a/libethdrivers/src/plat/imx6/enet.c +++ b/libethdrivers/src/plat/imx6/enet.c @@ -456,6 +456,12 @@ void enet_disable(struct enet *enet) regs->ecr &= ~ECR_ETHEREN; } +int enet_get_mask(struct enet *enet) +{ + assert(enet); + return enet_get_regs(enet)->eimr; +} + void enet_set_mac(struct enet *enet, uint64_t mac) { enet_regs_t *regs = enet_get_regs(enet); @@ -692,9 +698,9 @@ void enet_print_mib(struct enet *enet) volatile struct mib_regs *mib = ®s->mib; regs->mibc |= MIBC_DIS; - printf("Ethernet Counter regs\n"); + /*printf("Ethernet Counter regs\n"); dump_regs((uint32_t *)mib, sizeof(*mib)); - printf("\n"); + printf("\n");*/ printf("-----------------------------\n"); printf("RX Frames RX OK: %d/%d\n", mib->ieee_r_frame_ok, diff --git a/libethdrivers/src/plat/imx6/enet.h b/libethdrivers/src/plat/imx6/enet.h index d836fde41..1e0aafe46 100644 --- a/libethdrivers/src/plat/imx6/enet.h +++ b/libethdrivers/src/plat/imx6/enet.h @@ -69,6 +69,8 @@ int enet_tx_enabled(struct enet *enet); void enet_rx_enable(struct enet *enet); int enet_rx_enabled(struct enet *enet); +int enet_get_mask(struct enet *enet); + void enet_set_mdcclk(struct enet *enet, uint32_t fout); uint32_t enet_get_mdcclk(struct enet *imx_eth); diff --git a/libethdrivers/src/plat/imx6/imx6.c b/libethdrivers/src/plat/imx6/imx6.c index 0bb170ee1..e540af1a7 100644 --- a/libethdrivers/src/plat/imx6/imx6.c +++ b/libethdrivers/src/plat/imx6/imx6.c @@ -30,9 +30,6 @@ #define BUF_SIZE MAX_PKT_SIZE #define DMA_ALIGN 32 -uint32_t transmit_irq = 0; -uint32_t receive_irq = 0; - struct descriptor { /* NOTE: little endian packing: len before stat */ #if BYTE_ORDER == LITTLE_ENDIAN @@ -395,7 +392,6 @@ static void complete_tx(imx6_eth_driver_t *dev) unsigned int cnt = 0; while (head != ring->tail) { - if (0 == cnt) { cnt = dev->tx_lengths[head]; if ((0 == cnt) || (cnt > dev->tx.cnt)) { @@ -412,15 +408,15 @@ static void complete_tx(imx6_eth_driver_t *dev) * every access happens as stated in the code. */ volatile struct descriptor *d = &(ring->descr[head]); - + /* If this buffer was not sent, we can't release any buffer. */ if (d->stat & TXD_READY) { assert(dev->enet); + /* give it another chance */ if (!enet_tx_enabled(dev->enet)) { enet_tx_enable(dev->enet); } - //ZF_LOGF("The buffer was not sent and we can't release any buffers."); - //enet_print_state(dev->enet); + if (d->stat & TXD_READY) return; } /* Go to next buffer, handle roll-over. */ @@ -428,7 +424,7 @@ static void complete_tx(imx6_eth_driver_t *dev) head = 0; } - if (0 == --cnt && !(d->stat & TXD_READY)) { + if (0 == --cnt) { ring->head = head; /* race condition if add/remove is not synchronized. */ ring->remain += cnt_org; @@ -467,21 +463,18 @@ static void handle_irq(struct eth_driver *driver, int irq) struct enet *enet = dev->enet; assert(enet); - uint32_t e = enet_clr_events(enet, IRQ_MASK); while (e & IRQ_MASK) { if (e & NETIRQ_TXF) { - //transmit_irq++; complete_tx(dev); } - if (e & NETIRQ_RXF) { - //receive_irq++; + if (e & NETIRQ_RXF && rx_irq_enabled(driver)) { complete_rx(dev); fill_rx_bufs(dev); } if (e & NETIRQ_EBERR) { ZF_LOGE("Error: System bus/uDMA"); - // ethif_print_state(netif_get_eth_driver(netif)); + //ethif_print_state(netif_get_eth_driver(netif)); assert(0); while (1); } @@ -524,6 +517,14 @@ static void raw_poll(struct eth_driver *driver) fill_rx_bufs(dev); } +static void checksum(unsigned char *buffer, unsigned int len) { + unsigned int csum; + unsigned char *p; + unsigned int i; + for (p = buffer, i=len, csum=0; i > 0; csum += *p++, --i); + printf("check sum = %zu\n", csum); +} + static int raw_tx(struct eth_driver *driver, unsigned int num, uintptr_t *phys, unsigned int *len, void *cookie) { @@ -567,6 +568,7 @@ static int raw_tx(struct eth_driver *driver, unsigned int num, uintptr_t *phys, tail_new = 0; stat |= TXD_WRAP; } + ZF_LOGW("Inserting buffer %p of length %d into ring", *phys, *len); update_ring_slot(ring, idx, *phys++, *len++, stat); } @@ -849,14 +851,7 @@ static int allocate_irq_callback(ps_irq_t irq, unsigned curr_num, { assert(token); imx6_eth_driver_t *dev = (imx6_eth_driver_t *)token; - - /*unsigned target_num = config_set(CONFIG_PLAT_IMX8MQ_EVK) ? 2 : 0; - ZF_LOGW("target_num = %d", target_num); - if (curr_num != target_num) { - ZF_LOGW("Ignoring interrupt #%d with value %d", curr_num, irq); - return 0; - }*/ - + dev->irq_id = ps_irq_register( &(dev->eth_drv.io_ops.irq_ops), irq, @@ -978,7 +973,6 @@ int ethif_imx_init_module(ps_io_ops_t *io_ops, const char *device_path) ret = -ENODEV; goto error; } - return 0; error: @@ -992,16 +986,6 @@ int ethif_imx_init_module(ps_io_ops_t *io_ops, const char *device_path) } -void reset_irqs() { - transmit_irq = 0; - receive_irq = 0; -} - -void get_irqs() { - printf("Transmit IRQs = %d\n", transmit_irq); - printf("Receive IRQs = %d\n", receive_irq); -} - static const char *compatible_strings[] = { /* Other i.MX platforms may also be compatible but the platforms that have * been tested are: diff --git a/libethdrivers/src/plat/imx6/uboot/imx_board.c b/libethdrivers/src/plat/imx6/uboot/imx_board.c index 7287f583e..1b292d8f3 100644 --- a/libethdrivers/src/plat/imx6/uboot/imx_board.c +++ b/libethdrivers/src/plat/imx6/uboot/imx_board.c @@ -169,6 +169,8 @@ int setup_iomux_enet(ps_io_ops_t *io_ops) /* Pad configuration below from device tree on u-boot */ IMX_IOMUX_V3_SETUP_MULTIPLE_PADS( base, + IMX8MM_PAD_SPDIF_TX_GPIO5_IO3 | MUX_PAD_CTRL(0x19), + IMX8MM_PAD_SAI3_MCLK_GPIO5_IO2 | MUX_PAD_CTRL(0x19), IMX8MM_PAD_ENET_MDC_ENET1_MDC | MUX_PAD_CTRL(0x3), IMX8MM_PAD_ENET_MDIO_ENET1_MDIO | MUX_PAD_CTRL(0x3), IMX8MM_PAD_ENET_TD3_ENET1_RGMII_TD3 | MUX_PAD_CTRL(0x1f), @@ -182,8 +184,12 @@ int setup_iomux_enet(ps_io_ops_t *io_ops) IMX8MM_PAD_ENET_TXC_ENET1_RGMII_TXC | MUX_PAD_CTRL(0x1f), IMX8MM_PAD_ENET_RXC_ENET1_RGMII_RXC | MUX_PAD_CTRL(0x91), IMX8MM_PAD_ENET_RX_CTL_ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(0x91), - IMX8MM_PAD_ENET_TX_CTL_ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(0x1f) + IMX8MM_PAD_ENET_TX_CTL_ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(0x1f), + IMX8MM_PAD_GPIO1_IO09_GPIO1_IO9 | MUX_PAD_CTRL(0x19) // ENET1_1588_EVENT0_OUT ); + gpio_direction_output(IMX_GPIO_NR(1, 9), 0, io_ops); + udelay(500); + gpio_direction_output(IMX_GPIO_NR(1, 9), 1, io_ops); uint32_t *gpr1 = base + 0x4; /* Change ENET_TX to use internal clocks and not the external clocks */ From 41be3109778e58dd037e16ba5706ae3dc657cc7f Mon Sep 17 00:00:00 2001 From: Lucy Date: Mon, 7 Mar 2022 14:15:54 +1100 Subject: [PATCH 7/8] Clean up Signed-off-by: Lucy --- libethdrivers/src/lwip.c | 9 +-------- libethdrivers/src/plat/imx6/imx6.c | 10 +--------- libethdrivers/src/plat/imx6/ocotp_ctrl.c | 1 - libethdrivers/src/plat/imx6/uboot/imx8mm_pins.h | 4 ++-- libethdrivers/src/plat/imx6/uboot/imx_board.c | 2 +- 5 files changed, 5 insertions(+), 21 deletions(-) diff --git a/libethdrivers/src/lwip.c b/libethdrivers/src/lwip.c index f21d265d6..cb50e4ce3 100644 --- a/libethdrivers/src/lwip.c +++ b/libethdrivers/src/lwip.c @@ -58,9 +58,7 @@ static void initialize_free_bufs(lwip_iface_t *iface) } static uintptr_t lwip_allocate_rx_buf(void *iface, size_t buf_size, void **cookie) -{ - ZF_LOGW("lwip.c in libethdrivers/src/plat called lwip_allocate_rx_buf()\n"); - +{ lwip_iface_t *lwip_iface = (lwip_iface_t *)iface; if (buf_size > CONFIG_LIB_ETHDRIVER_PREALLOCATED_BUF_SIZE) { LOG_ERROR("Requested RX buffer of size %zu which can never be fullfilled by preallocated buffers of size %d", buf_size, @@ -142,9 +140,6 @@ static void lwip_rx_complete(void *iface, unsigned int num_bufs, void **cookies, } } -// PKT_DEBUG(printf("Receiving packet\n")); -// PKT_DEBUG(print_packet(COL_RX, p->payload, len)); - #if ETH_PAD_SIZE pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */ #endif @@ -413,8 +408,6 @@ static err_t ethif_init(struct netif *netif) return ERR_ARG; } - printf("Does this file, lwip.c, get used\n"); - lwip_iface_t *iface = (lwip_iface_t *)netif->state; int mtu; iface->driver.i_fn.low_level_init(&iface->driver, netif->hwaddr, &mtu); diff --git a/libethdrivers/src/plat/imx6/imx6.c b/libethdrivers/src/plat/imx6/imx6.c index e540af1a7..a4fe0b02b 100644 --- a/libethdrivers/src/plat/imx6/imx6.c +++ b/libethdrivers/src/plat/imx6/imx6.c @@ -468,7 +468,7 @@ static void handle_irq(struct eth_driver *driver, int irq) if (e & NETIRQ_TXF) { complete_tx(dev); } - if (e & NETIRQ_RXF && rx_irq_enabled(driver)) { + if (e & NETIRQ_RXF) { complete_rx(dev); fill_rx_bufs(dev); } @@ -517,14 +517,6 @@ static void raw_poll(struct eth_driver *driver) fill_rx_bufs(dev); } -static void checksum(unsigned char *buffer, unsigned int len) { - unsigned int csum; - unsigned char *p; - unsigned int i; - for (p = buffer, i=len, csum=0; i > 0; csum += *p++, --i); - printf("check sum = %zu\n", csum); -} - static int raw_tx(struct eth_driver *driver, unsigned int num, uintptr_t *phys, unsigned int *len, void *cookie) { diff --git a/libethdrivers/src/plat/imx6/ocotp_ctrl.c b/libethdrivers/src/plat/imx6/ocotp_ctrl.c index 2d8482734..7a5e2c226 100644 --- a/libethdrivers/src/plat/imx6/ocotp_ctrl.c +++ b/libethdrivers/src/plat/imx6/ocotp_ctrl.c @@ -23,7 +23,6 @@ #define IMX6_OCOTP_SIZE 0x00004000 #elif defined(CONFIG_PLAT_IMX8MQ_EVK) || defined(CONFIG_PLAT_IMX8MM_EVK) -// from: root/arch/arm/include/asm/arch-imx8m/imx-regs-imx8mm.h #define IMX6_OCOTP_PADDR 0x30350000 #define IMX6_OCOTP_SIZE 0x00010000 diff --git a/libethdrivers/src/plat/imx6/uboot/imx8mm_pins.h b/libethdrivers/src/plat/imx6/uboot/imx8mm_pins.h index 71fc2ab5a..964767e37 100644 --- a/libethdrivers/src/plat/imx6/uboot/imx8mm_pins.h +++ b/libethdrivers/src/plat/imx6/uboot/imx8mm_pins.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2018-2019 NXP - * Taken from u-boot/arch/arm/include/asm/arch-imx8m/imx8mm_pins.h + * Content derived from u-boot/arch/arm/include/asm/arch-imx8m/imx8mm_pins.h */ #pragma once @@ -691,4 +691,4 @@ enum { IMX8MM_PAD_UART4_TXD_UART2_RTS_B = IOMUX_PAD(0x04B8, 0x0250, 1, 0x04F8, 1, 0), IMX8MM_PAD_UART4_TXD_UART2_CTS_B = IOMUX_PAD(0x04B8, 0x0250, 1, 0x0000, 0, 0), IMX8MM_PAD_UART4_TXD_GPIO5_IO29 = IOMUX_PAD(0x04B8, 0x0250, 5, 0x0000, 0, 0), -}; \ No newline at end of file +}; diff --git a/libethdrivers/src/plat/imx6/uboot/imx_board.c b/libethdrivers/src/plat/imx6/uboot/imx_board.c index 1b292d8f3..171cf650c 100644 --- a/libethdrivers/src/plat/imx6/uboot/imx_board.c +++ b/libethdrivers/src/plat/imx6/uboot/imx_board.c @@ -62,7 +62,7 @@ #elif defined(CONFIG_PLAT_IMX8MM_EVK) #include "imx8mm_pins.h" -#define IOMUXC_PADDR 0x30330000 // from: root/arch/arm/include/asm/arch-imx8m/imx-regs-imx8mm.h +#define IOMUXC_PADDR 0x30330000 #define IOMUXC_SIZE 0x10000 #else From 4c859c8388f9d8d39d7634f6f0bb0fcbf0208530 Mon Sep 17 00:00:00 2001 From: Lucy Date: Fri, 11 Mar 2022 13:47:57 +1100 Subject: [PATCH 8/8] Removed trailing whitespace Signed-off-by: Lucy --- libethdrivers/src/plat/imx6/imx6.c | 4 ++-- libethdrivers/src/plat/imx6/uboot/imx_board.c | 8 ++++---- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/libethdrivers/src/plat/imx6/imx6.c b/libethdrivers/src/plat/imx6/imx6.c index a4fe0b02b..88d5353db 100644 --- a/libethdrivers/src/plat/imx6/imx6.c +++ b/libethdrivers/src/plat/imx6/imx6.c @@ -408,7 +408,7 @@ static void complete_tx(imx6_eth_driver_t *dev) * every access happens as stated in the code. */ volatile struct descriptor *d = &(ring->descr[head]); - + /* If this buffer was not sent, we can't release any buffer. */ if (d->stat & TXD_READY) { assert(dev->enet); @@ -843,7 +843,7 @@ static int allocate_irq_callback(ps_irq_t irq, unsigned curr_num, { assert(token); imx6_eth_driver_t *dev = (imx6_eth_driver_t *)token; - + dev->irq_id = ps_irq_register( &(dev->eth_drv.io_ops.irq_ops), irq, diff --git a/libethdrivers/src/plat/imx6/uboot/imx_board.c b/libethdrivers/src/plat/imx6/uboot/imx_board.c index 171cf650c..a66958941 100644 --- a/libethdrivers/src/plat/imx6/uboot/imx_board.c +++ b/libethdrivers/src/plat/imx6/uboot/imx_board.c @@ -165,11 +165,11 @@ int setup_iomux_enet(ps_io_ops_t *io_ops) #elif defined(CONFIG_PLAT_IMX8MM_EVK) - /* Does PHY need to go into reset before this? */ - /* Pad configuration below from device tree on u-boot */ + /* Does PHY need to go into reset before this? */ + /* Pad configuration below from device tree on u-boot */ IMX_IOMUX_V3_SETUP_MULTIPLE_PADS( base, - IMX8MM_PAD_SPDIF_TX_GPIO5_IO3 | MUX_PAD_CTRL(0x19), + IMX8MM_PAD_SPDIF_TX_GPIO5_IO3 | MUX_PAD_CTRL(0x19), IMX8MM_PAD_SAI3_MCLK_GPIO5_IO2 | MUX_PAD_CTRL(0x19), IMX8MM_PAD_ENET_MDC_ENET1_MDC | MUX_PAD_CTRL(0x3), IMX8MM_PAD_ENET_MDIO_ENET1_MDIO | MUX_PAD_CTRL(0x3), @@ -185,7 +185,7 @@ int setup_iomux_enet(ps_io_ops_t *io_ops) IMX8MM_PAD_ENET_RXC_ENET1_RGMII_RXC | MUX_PAD_CTRL(0x91), IMX8MM_PAD_ENET_RX_CTL_ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(0x91), IMX8MM_PAD_ENET_TX_CTL_ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(0x1f), - IMX8MM_PAD_GPIO1_IO09_GPIO1_IO9 | MUX_PAD_CTRL(0x19) // ENET1_1588_EVENT0_OUT + IMX8MM_PAD_GPIO1_IO09_GPIO1_IO9 | MUX_PAD_CTRL(0x19) // ENET1_1588_EVENT0_OUT ); gpio_direction_output(IMX_GPIO_NR(1, 9), 0, io_ops); udelay(500);