diff --git a/libethdrivers/CMakeLists.txt b/libethdrivers/CMakeLists.txt index 39f3527ea..bea69d4f2 100644 --- a/libethdrivers/CMakeLists.txt +++ b/libethdrivers/CMakeLists.txt @@ -63,7 +63,7 @@ mark_as_advanced( ) add_config_library(ethdrivers "${configure_string}") -if("${KernelPlatform}" MATCHES "imx8mq-evk") +if(("${KernelPlatform}" MATCHES "imx8mq-evk") OR ("${KernelPlatform}" MATCHES "imx8mm-evk")) # Re-use the imx6 sources set(PlatPrefix "imx6") else() diff --git a/libethdrivers/include/ethdrivers/imx6.h b/libethdrivers/include/ethdrivers/imx6.h index f3923ffea..3968ad8b5 100644 --- a/libethdrivers/include/ethdrivers/imx6.h +++ b/libethdrivers/include/ethdrivers/imx6.h @@ -7,4 +7,6 @@ #pragma once +struct eth_driver; + /* nothing here */ diff --git a/libethdrivers/src/lwip.c b/libethdrivers/src/lwip.c index e45fc3a81..cb50e4ce3 100644 --- a/libethdrivers/src/lwip.c +++ b/libethdrivers/src/lwip.c @@ -140,9 +140,6 @@ static void lwip_rx_complete(void *iface, unsigned int num_bufs, void **cookies, } } -// PKT_DEBUG(printf("Receiving packet\n")); -// PKT_DEBUG(print_packet(COL_RX, p->payload, len)); - #if ETH_PAD_SIZE pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */ #endif diff --git a/libethdrivers/src/plat/imx6/enet.c b/libethdrivers/src/plat/imx6/enet.c index 1dc1f98a6..fa8540469 100644 --- a/libethdrivers/src/plat/imx6/enet.c +++ b/libethdrivers/src/plat/imx6/enet.c @@ -16,8 +16,8 @@ #include #include -#ifdef CONFIG_PLAT_IMX8MQ_EVK -#define CCM_PADDR 0x30380000 +#if (defined(CONFIG_PLAT_IMX8MQ_EVK) || defined(CONFIG_PLAT_IMX8MM_EVK)) +#define CCM_PADDR 0x30380000 // from: root/arch/arm/include/asm/arch-imx8m/imx-regs-imx8mm.h #define CCM_SIZE 0x10000 #endif @@ -314,7 +314,7 @@ static struct clock mdc_clk = { }; -#ifdef CONFIG_PLAT_IMX8MQ_EVK +#if (defined(CONFIG_PLAT_IMX8MQ_EVK) || defined(CONFIG_PLAT_IMX8MM_EVK)) static freq_t _enet_clk_get_freq(clk_t *clk) { @@ -456,6 +456,12 @@ void enet_disable(struct enet *enet) regs->ecr &= ~ECR_ETHEREN; } +int enet_get_mask(struct enet *enet) +{ + assert(enet); + return enet_get_regs(enet)->eimr; +} + void enet_set_mac(struct enet *enet, uint64_t mac) { enet_regs_t *regs = enet_get_regs(enet); @@ -558,7 +564,7 @@ struct enet *enet_init(void *mapped_peripheral, uintptr_t tx_phys, enet_clk_ptr = clk_get_clock(clk_sys, CLK_ENET); clk_set_freq(enet_clk_ptr, ENET_FREQ); -#elif defined(CONFIG_PLAT_IMX8MQ_EVK) +#elif defined(CONFIG_PLAT_IMX8MQ_EVK) || defined(CONFIG_PLAT_IMX8MM_EVK) enet_clk_ptr = &enet_clk; // TODO Implement an actual clock driver for the imx8mq @@ -606,8 +612,12 @@ struct enet *enet_init(void *mapped_peripheral, uintptr_t tx_phys, regs->gaur = 0; regs->galr = 0; +#if defined(CONFIG_PLAT_IMX8MQ_EVK) || defined(CONFIG_PLAT_IMX8MM_EVK) + /* For iMX.8 we assume that the bootloader has already correctly + * configured the MAC address */ /* Set MAC and pause frame type field */ enet_set_mac(enet, mac); +#endif /* Configure pause frames (continues into MAC registers...) */ regs->opd = PAUSE_OPCODE_FIELD << 16; @@ -688,9 +698,9 @@ void enet_print_mib(struct enet *enet) volatile struct mib_regs *mib = ®s->mib; regs->mibc |= MIBC_DIS; - printf("Ethernet Counter regs\n"); + /*printf("Ethernet Counter regs\n"); dump_regs((uint32_t *)mib, sizeof(*mib)); - printf("\n"); + printf("\n");*/ printf("-----------------------------\n"); printf("RX Frames RX OK: %d/%d\n", mib->ieee_r_frame_ok, diff --git a/libethdrivers/src/plat/imx6/enet.h b/libethdrivers/src/plat/imx6/enet.h index d836fde41..1e0aafe46 100644 --- a/libethdrivers/src/plat/imx6/enet.h +++ b/libethdrivers/src/plat/imx6/enet.h @@ -69,6 +69,8 @@ int enet_tx_enabled(struct enet *enet); void enet_rx_enable(struct enet *enet); int enet_rx_enabled(struct enet *enet); +int enet_get_mask(struct enet *enet); + void enet_set_mdcclk(struct enet *enet, uint32_t fout); uint32_t enet_get_mdcclk(struct enet *imx_eth); diff --git a/libethdrivers/src/plat/imx6/imx6.c b/libethdrivers/src/plat/imx6/imx6.c index 9cd257fe4..88d5353db 100644 --- a/libethdrivers/src/plat/imx6/imx6.c +++ b/libethdrivers/src/plat/imx6/imx6.c @@ -23,6 +23,9 @@ #include "uboot/micrel.h" #include "unimplemented.h" +// Temporary fix: set to imx8mq mac +#define DEFAULT_MAC "\x00\x04\x9f\x05\x93\xdf" + #define IRQ_MASK (NETIRQ_RXF | NETIRQ_TXF | NETIRQ_EBERR) #define BUF_SIZE MAX_PKT_SIZE #define DMA_ALIGN 32 @@ -185,6 +188,7 @@ static void fill_rx_bufs(imx6_eth_driver_t *dev) * small because CONFIG_LIB_ETHDRIVER_NUM_PREALLOCATED_BUFFERS * is less than CONFIG_LIB_ETHDRIVER_RX_DESC_COUNT. */ + ZF_LOGF("There are no buffers left."); break; } uint16_t stat = RXD_EMPTY; @@ -388,7 +392,6 @@ static void complete_tx(imx6_eth_driver_t *dev) unsigned int cnt = 0; while (head != ring->tail) { - if (0 == cnt) { cnt = dev->tx_lengths[head]; if ((0 == cnt) || (cnt > dev->tx.cnt)) { @@ -409,10 +412,11 @@ static void complete_tx(imx6_eth_driver_t *dev) /* If this buffer was not sent, we can't release any buffer. */ if (d->stat & TXD_READY) { assert(dev->enet); + /* give it another chance */ if (!enet_tx_enabled(dev->enet)) { enet_tx_enable(dev->enet); } - return; + if (d->stat & TXD_READY) return; } /* Go to next buffer, handle roll-over. */ @@ -427,7 +431,6 @@ static void complete_tx(imx6_eth_driver_t *dev) /* give the buffer back */ cb_complete(cb_cookie, cookie); } - } /* The only reason to arrive here is when head equals tails. If cnt is not @@ -461,18 +464,21 @@ static void handle_irq(struct eth_driver *driver, int irq) assert(enet); uint32_t e = enet_clr_events(enet, IRQ_MASK); - if (e & NETIRQ_TXF) { - complete_tx(dev); - } - if (e & NETIRQ_RXF) { - complete_rx(dev); - fill_rx_bufs(dev); - } - if (e & NETIRQ_EBERR) { - ZF_LOGE("Error: System bus/uDMA"); - // ethif_print_state(netif_get_eth_driver(netif)); - assert(0); - while (1); + while (e & IRQ_MASK) { + if (e & NETIRQ_TXF) { + complete_tx(dev); + } + if (e & NETIRQ_RXF) { + complete_rx(dev); + fill_rx_bufs(dev); + } + if (e & NETIRQ_EBERR) { + ZF_LOGE("Error: System bus/uDMA"); + //ethif_print_state(netif_get_eth_driver(netif)); + assert(0); + while (1); + } + e = enet_clr_events(enet, IRQ_MASK); } } @@ -554,6 +560,7 @@ static int raw_tx(struct eth_driver *driver, unsigned int num, uintptr_t *phys, tail_new = 0; stat |= TXD_WRAP; } + ZF_LOGW("Inserting buffer %p of length %d into ring", *phys, *len); update_ring_slot(ring, idx, *phys++, *len++, stat); } @@ -636,6 +643,18 @@ static int init_device(imx6_eth_driver_t *dev, const nic_config_t *nic_config) int ret; +#if defined(CONFIG_PLAT_IMX8MQ_EVK) + /* Don't attempt to obtain the MAC address for iMX8MQ. + * + * The code to obtain the MAC address assumes an iMX6 compatible + * OCOTP which the iMX8 does not have. + * + * Instead, we assume that the bootloader has already configured the + * hardware MAC address. */ + uint64_t mac = 0; + ZF_LOGI("using MAC configured by bootloader"); +#else + /* this works for imx8mm however */ uint64_t mac = obtain_mac(nic_config, &(dev->eth_drv.io_ops.io_mapper)); if (0 == mac) { ZF_LOGE("Failed to obtain a MAC"); @@ -649,6 +668,7 @@ static int init_device(imx6_eth_driver_t *dev, const nic_config_t *nic_config) (uint8_t)(mac >> 16), (uint8_t)(mac >> 8), (uint8_t)(mac)); +#endif ret = setup_desc_ring(dev, &(dev->rx)); if (ret) { @@ -736,9 +756,9 @@ static int init_device(imx6_eth_driver_t *dev, const nic_config_t *nic_config) /* Initialise the phy library */ miiphy_init(); /* Initialise the phy */ -#if defined(CONFIG_PLAT_SABRE) || defined(CONFIG_PLAT_WANDQ) +#if defined(CONFIG_PLAT_SABRE) || defined(CONFIG_PLAT_WANDQ) || defined(CONFIG_PLAT_IMX8MQ_EVK) phy_micrel_init(); -#elif defined(CONFIG_PLAT_NITROGEN6SX) +#elif defined(CONFIG_PLAT_NITROGEN6SX) || defined(CONFIG_PLAT_IMX8MM_EVK) phy_atheros_init(); #else #error "unsupported board" @@ -824,12 +844,6 @@ static int allocate_irq_callback(ps_irq_t irq, unsigned curr_num, assert(token); imx6_eth_driver_t *dev = (imx6_eth_driver_t *)token; - unsigned target_num = config_set(CONFIG_PLAT_IMX8MQ_EVK) ? 2 : 0; - if (curr_num != target_num) { - ZF_LOGW("Ignoring interrupt #%d with value %d", curr_num, irq); - return 0; - } - dev->irq_id = ps_irq_register( &(dev->eth_drv.io_ops.irq_ops), irq, @@ -951,7 +965,6 @@ int ethif_imx_init_module(ps_io_ops_t *io_ops, const char *device_path) ret = -ENODEV; goto error; } - return 0; error: @@ -975,6 +988,7 @@ static const char *compatible_strings[] = { "fsl,imx6q-fec", "fsl,imx6sx-fec", "fsl,imx8mq-fec", + "fsl,imx8mm-fec", NULL }; diff --git a/libethdrivers/src/plat/imx6/ocotp_ctrl.c b/libethdrivers/src/plat/imx6/ocotp_ctrl.c index 9f4d46e23..7a5e2c226 100644 --- a/libethdrivers/src/plat/imx6/ocotp_ctrl.c +++ b/libethdrivers/src/plat/imx6/ocotp_ctrl.c @@ -22,8 +22,7 @@ #define IMX6_OCOTP_PADDR 0x021BC000 #define IMX6_OCOTP_SIZE 0x00004000 -#elif defined(CONFIG_PLAT_IMX8MQ_EVK) - +#elif defined(CONFIG_PLAT_IMX8MQ_EVK) || defined(CONFIG_PLAT_IMX8MM_EVK) #define IMX6_OCOTP_PADDR 0x30350000 #define IMX6_OCOTP_SIZE 0x00010000 @@ -211,10 +210,16 @@ uint64_t ocotp_get_mac(struct ocotp *ocotp, unsigned int id) uint64_t mac = 0; switch (id) { +#if defined(CONFIG_PLAT_IMX8MM_EVK) || defined(CONFIG_IMX8MQ_EVK) + case 0: + mac = ((uint64_t)((uint16_t)regs->res37[4]) << 32) | regs->res37[0]; + break; +#else case 0: /* 0x0000
*/ mac = ((uint64_t)((uint16_t)regs->mac1) << 32) | regs->mac0; break; +#endif #ifdef CONFIG_PLAT_IMX6SX @@ -237,7 +242,7 @@ uint64_t ocotp_get_mac(struct ocotp *ocotp, unsigned int id) return 0; } - ZF_LOGI("OCOTP MAC #%u: %02x:%02x:%02x:%02x:%02x:%02x", + ZF_LOGW("OCOTP MAC #%u: %02x:%02x:%02x:%02x:%02x:%02x", id, (uint8_t)(mac >> 40), (uint8_t)(mac >> 32), (uint8_t)(mac >> 24), (uint8_t)(mac >> 16), (uint8_t)(mac >> 8), (uint8_t)mac); diff --git a/libethdrivers/src/plat/imx6/uboot/fec_mxc.c b/libethdrivers/src/plat/imx6/uboot/fec_mxc.c index fe724bbb9..f7dfcf4a0 100644 --- a/libethdrivers/src/plat/imx6/uboot/fec_mxc.c +++ b/libethdrivers/src/plat/imx6/uboot/fec_mxc.c @@ -176,9 +176,11 @@ struct phy_device *fec_init(unsigned int phy_mask, struct enet *enet, ZF_LOGW("SABRE: unexpected PHY with ID 0x%x", phydev->phy_id); } -#elif defined(CONFIG_PLAT_NITROGEN6SX) - - if (0x004dd072 == phydev->phy_id) { +#elif defined(CONFIG_PLAT_NITROGEN6SX) || defined(CONFIG_PLAT_IMX8MM_EVK) + /* imx6sx and imx8mm seem to use a very similar phy device. + The AR8031 (used in imx8mm) also has the SmartEEE feature but not sure if + this is necessary. */ + if (0x004dd072 == phydev->phy_id || 0x004dd074 == phydev->phy_id) { /* Disable Ar803x PHY SmartEEE feature, it causes link status glitches * that result in the ethernet link going down and up. */ diff --git a/libethdrivers/src/plat/imx6/uboot/imx-regs.h b/libethdrivers/src/plat/imx6/uboot/imx-regs.h index e395cdcef..3effd8225 100644 --- a/libethdrivers/src/plat/imx6/uboot/imx-regs.h +++ b/libethdrivers/src/plat/imx6/uboot/imx-regs.h @@ -30,200 +30,10 @@ #define CONFIG_SYS_CACHELINE_SIZE 32 -#define ROMCP_ARB_BASE_ADDR 0x00000000 -#define ROMCP_ARB_END_ADDR 0x000FFFFF - - -#if defined(CONFIG_PLAT_IMX6DQ) - -#define CAAM_ARB_BASE_ADDR 0x00100000 -#define CAAM_ARB_END_ADDR 0x00103FFF -#define APBH_DMA_ARB_BASE_ADDR 0x00110000 -#define APBH_DMA_ARB_END_ADDR 0x00117FFF -#define HDMI_ARB_BASE_ADDR 0x00120000 -#define HDMI_ARB_END_ADDR 0x00128FFF -#define GPU_3D_ARB_BASE_ADDR 0x00130000 -#define GPU_3D_ARB_END_ADDR 0x00133FFF -#define GPU_2D_ARB_BASE_ADDR 0x00134000 -#define GPU_2D_ARB_END_ADDR 0x00137FFF -#define DTCP_ARB_BASE_ADDR 0x00138000 -#define DTCP_ARB_END_ADDR 0x0013BFFF - -#elif defined(CONFIG_PLAT_IMX6SX) - -#define CAAM_ARB_BASE_ADDR 0x00100000 -#define CAAM_ARB_END_ADDR 0x00107FFF -#define GPU_ARB_BASE_ADDR 0x01800000 -#define GPU_ARB_END_ADDR 0x01803FFF -#define APBH_DMA_ARB_BASE_ADDR 0x01804000 -#define APBH_DMA_ARB_END_ADDR 0x0180BFFF -#define M4_BOOTROM_BASE_ADDR 0x007F8000 - -#else -#error "unknown i.MX6 SOC" -#endif - - -#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR -#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000) -#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000) - -/* GPV - PL301 configuration ports */ - -#if defined(CONFIG_PLAT_IMX6DQ) - -#define GPV2_BASE_ADDR 0x00200000 -#define GPV3_BASE_ADDR 0x00300000 -#define GPV4_BASE_ADDR 0x00800000 - -#elif defined(CONFIG_PLAT_IMX6SX) - -#define GPV2_BASE_ADDR 0x00D00000 -#define GPV3_BASE_ADDR 0x00E00000 -#define GPV4_BASE_ADDR 0x00F00000 -#define GPV5_BASE_ADDR 0x01000000 -#define GPV6_BASE_ADDR 0x01100000 - -#else -#error "unknown i.MX6 SOC" -#endif - - -#define IRAM_BASE_ADDR 0x00900000 - -#if defined(CONFIG_PLAT_IMX6DQ) -#define IRAM_SIZE 0x00020000 -#elif defined(CONFIG_PLAT_IMX6SX) -#define IRAM_SIZE 0x00040000 -#else -#error "unknown i.MX6 SOC" -#endif - - -#define SCU_BASE_ADDR 0x00A00000 -#define IC_INTERFACES_BASE_ADDR 0x00A00100 -#define GLOBAL_TIMER_BASE_ADDR 0x00A00200 -#define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600 -#define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000 -#define L2_PL310_BASE 0x00A02000 -#define GPV0_BASE_ADDR 0x00B00000 -#define GPV1_BASE_ADDR 0x00C00000 - - -#if defined(CONFIG_PLAT_IMX6DQ) - -#define PCIE_ARB_BASE_ADDR 0x01000000 -#define PCIE_ARB_END_ADDR 0x01FFFFFF - -#elif defined(CONFIG_PLAT_IMX6SX) - -#define PCIE_ARB_BASE_ADDR 0x08000000 -#define PCIE_ARB_END_ADDR 0x08FFFFFF - -#else -#error "unknown i.MX6 SOC" -#endif - - -#define AIPS1_ARB_BASE_ADDR 0x02000000 -#define AIPS1_ARB_END_ADDR 0x020FFFFF -#define AIPS2_ARB_BASE_ADDR 0x02100000 -#define AIPS2_ARB_END_ADDR 0x021FFFFF - -#if defined(CONFIG_PLAT_IMX6SX) -/* AIPS3 exists on i.MX6SX */ -#define AIPS3_ARB_BASE_ADDR 0x02200000 -#define AIPS3_ARB_END_ADDR 0x022FFFFF -#endif - - -#if defined(CONFIG_PLAT_IMX6DQ) - -#define SATA_ARB_BASE_ADDR 0x02200000 -#define SATA_ARB_END_ADDR 0x02203FFF -#define OPENVG_ARB_BASE_ADDR 0x02204000 -#define OPENVG_ARB_END_ADDR 0x02207FFF -#define HSI_ARB_BASE_ADDR 0x02208000 -#define HSI_ARB_END_ADDR 0x0220BFFF -#define IPU1_ARB_BASE_ADDR 0x02400000 -#define IPU1_ARB_END_ADDR 0x027FFFFF -#define IPU2_ARB_BASE_ADDR 0x02800000 -#define IPU2_ARB_END_ADDR 0x02BFFFFF -#define WEIM_ARB_BASE_ADDR 0x08000000 -#define WEIM_ARB_END_ADDR 0x0FFFFFFF - -#define MMDC0_ARB_BASE_ADDR 0x10000000 -#define MMDC0_ARB_END_ADDR 0x7FFFFFFF -#define MMDC1_ARB_BASE_ADDR 0x80000000 -#define MMDC1_ARB_END_ADDR 0xFFFFFFFF - -#define IPU_SOC_BASE_ADDR IPU1_ARB_BASE_ADDR -#define IPU_SOC_OFFSET 0x00200000 - -#elif defined(CONFIG_PLAT_IMX6SX) - -#define WEIM_ARB_BASE_ADDR 0x50000000 -#define WEIM_ARB_END_ADDR 0x57FFFFFF -#define QSPI0_AMBA_BASE 0x60000000 -#define QSPI0_AMBA_END 0x6FFFFFFF -#define QSPI1_AMBA_BASE 0x70000000 -#define QSPI1_AMBA_END 0x7FFFFFFF -#define MMDC0_ARB_BASE_ADDR 0x80000000 -#define MMDC0_ARB_END_ADDR 0xBFFFFFFF -#define MMDC1_ARB_BASE_ADDR 0xC0000000 -#define MMDC1_ARB_END_ADDR 0xFFFFFFFF - -#else -#error "unknown i.MX6 SOC" -#endif - -/* Defines for Blocks connected via AIPS (SkyBlue) */ +#define AIPS1_ARB_BASE_ADDR 0x02000000 #define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR -#define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR -#if defined(CONFIG_PLAT_IMX6SX) -/* ATZ3/AIPS3 exists on i.MX6SX */ -#define ATZ3_BASE_ADDR AIPS3_ARB_BASE_ADDR -#endif - -#define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR -#define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR -#if defined(CONFIG_PLAT_IMX6SX) -/* AIPS3 exists on i.MX6SX */ -#define AIPS3_BASE_ADDR AIPS3_ON_BASE_ADDR -#endif - -#define SPDIF_BASE_ADDR (ATZ1_BASE_ADDR + 0x04000) -#define ECSPI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x08000) -#define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000) -#define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000) -#define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000) - -#if defined(CONFIG_PLAT_IMX6DQ) -#define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) -#endif - -#define UART1_BASE (ATZ1_BASE_ADDR + 0x20000) -#define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) -#define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000) -#define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000) -#define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000) -#define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) - -#if defined(CONFIG_PLAT_IMX6DQ) -#define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000) -#define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000) -#endif - -#define AIPS1_ON_BASE_ADDR (ATZ1_BASE_ADDR + 0x7C000) #define AIPS1_OFF_BASE_ADDR (ATZ1_BASE_ADDR + 0x80000) -#define PWM1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0000) -#define PWM2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4000) -#define PWM3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x8000) -#define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000) -#define CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000) -#define CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000) -#define GPT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000) #define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000) #define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x20000) #define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x24000) @@ -231,589 +41,3 @@ #define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000) #define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000) #define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000) -#define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000) -#define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000) -#define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000) -#define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000) -#define USB_PHY0_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x49000) -#define USB_PHY1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4a000) -#define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000) -#define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4C000) -#define EPIT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x50000) -#define EPIT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x54000) -#define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000) -#define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000) -#define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000) - - -#if defined(CONFIG_PLAT_IMX6DQ) - -#define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) -#define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) -#define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) - -#elif defined(CONFIG_PLAT_IMX6SX) - -#define CANFD1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) -#define SDMA_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) -#define CANFD2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000) -#define SEMAPHORE1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000) -#define SEMAPHORE2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000) -#define RDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000) - -#else -#error "unknown i.MX6 SOC" -#endif - - -#define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000) -#define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) -#define CAAM_BASE_ADDR (ATZ2_BASE_ADDR) -#define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000) - -#define CONFIG_SYS_FSL_SEC_ADDR CAAM_BASE_ADDR -#define CONFIG_SYS_FSL_JR0_ADDR (CAAM_BASE_ADDR + 0x1000) - -#define USBOH3_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000) -#define USBOH3_USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000) -#define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000) -#define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000) -#define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000) -#define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000) -#define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000) -#define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000) -#define I2C1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x20000) -#define I2C2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x24000) -#define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000) -#define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000) -#define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000) - -#ifdef CONFIG_PLAT_IMX6SX -#define ENET2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) -#endif - -#define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) -#define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000) -#define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000) -#define IMX_IIM_BASE OCOTP_BASE_ADDR -#define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000) -#define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000) -#define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) - - -#if defined(CONFIG_PLAT_IMX6DQ) - -#define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000) -#define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000) -#define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000) -#define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000) -#define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) -#define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) -#define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000) - -#elif defined(CONFIG_PLAT_IMX6SX) - -#define DEBUG_MONITOR_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000) -#define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000) -#define SAI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000) -#define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000) -#define SAI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) -#define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) -#define QSPI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000) - -#else -#error "unknown i.MX6 SOC" -#endif - - -#define UART2_BASE (AIPS2_OFF_BASE_ADDR + 0x68000) -#define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000) -#define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000) -#define UART5_BASE (AIPS2_OFF_BASE_ADDR + 0x74000) -#define I2C4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000) -#define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000) -#define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) - -#if defined(CONFIG_PLAT_IMX6SX) -/* ATZ3/AIPS3 exists on i.MX6SX */ - -#define AIPS3_ON_BASE_ADDR (ATZ3_BASE_ADDR + 0x7C000) -#define AIPS3_OFF_BASE_ADDR (ATZ3_BASE_ADDR + 0x80000) - -#define GIS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x04000) -#define DCIC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x0C000) -#define DCIC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x10000) -#define CSI1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x14000) -#define PXP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x18000) -#define CSI2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x1C000) -#define LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000) -#define LCDIF2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x24000) -#define VADC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x28000) -#define VDEC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x2C000) -#define SPBA_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x3C000) -#define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000) -#define ADC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000) -#define ADC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000) -#define WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000) -#define ECSPI5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000) -#define HS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000) -#define MU_MCU_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000) -#define CANFD_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x98000) -#define MU_DSP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x9C000) -#define UART6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA0000) -#define PWM5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA4000) -#define PWM6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA8000) -#define PWM7_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xAC000) -#define PWM8_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xB0000) - -#endif /* defined(CONFIG_PLAT_IMX6SX) */ - - -#define CHIP_REV_1_0 0x10 - -#define FEC_QUIRK_ENET_MAC - - -#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) - -/* System Reset Controller (SRC) */ -struct src { - uint32_t scr; - uint32_t sbmr1; - uint32_t srsr; - uint32_t reserved1[2]; - uint32_t sisr; - uint32_t simr; - uint32_t sbmr2; - uint32_t gpr1; - uint32_t gpr2; - uint32_t gpr3; - uint32_t gpr4; - uint32_t gpr5; - uint32_t gpr6; - uint32_t gpr7; - uint32_t gpr8; - uint32_t gpr9; - uint32_t gpr10; -}; - -/* OCOTP Registers */ -struct ocotp_regs { - uint32_t reserved[0x198]; - uint32_t gp1; /* 0x660 */ -}; - -/* GPR3 bitfields */ -#define IOMUXC_GPR3_GPU_DBG_OFFSET 29 -#define IOMUXC_GPR3_GPU_DBG_MASK (3<name, addr);