From d497ba9ad0d48dc86723f35997a03997c1e3001a Mon Sep 17 00:00:00 2001
From: Tim Newsome <tim@sifive.com>
Date: Fri, 3 Nov 2023 14:33:01 -0700
Subject: [PATCH] Clarify matching on invalid virtual addresses behavior

See:
* https://lists.riscv.org/g/tech-debug/message/1407
* https://lists.riscv.org/g/tech-debug/files/meetings%202023/2023-01-10%20Debug%20Task%20Group%20Call%20Notes.pdf
* https://lists.riscv.org/g/tech-debug/files/meetings%202023/2023-01-10%20Debug%20Task%20Group%20Call%20Slides.pdf
---
 Sdtrig.tex             | 19 +++++++++++++++++++
 xml/hwbp_registers.xml | 12 ------------
 2 files changed, 19 insertions(+), 12 deletions(-)

diff --git a/Sdtrig.tex b/Sdtrig.tex
index 8355de73..5d751821 100644
--- a/Sdtrig.tex
+++ b/Sdtrig.tex
@@ -319,6 +319,25 @@ \subsection{Cache Operations}
     \end{steps}
 \end{commentary}
 
+\subsection{Invalid Virtual Addresses}
+
+For virtual address matches without a mask, \RcsrTdataTwo must be able to hold
+all valid virtual addresses but it need not be capable of holding other values.
+Implementations may convert an invalid virtual address to a different invalid
+virtual address before comparing the address to \RcsrTdataTwo.
+
+\begin{commentary}
+    A straightforward trigger implementation would compare the effective address
+    to the contents of \RcsrTdataTwo. This is most intuitive to a user setting
+    triggers. However, the Privileged Spec makes various accommodations that
+    allow a shorter representation of invalid virtual addresses, and the Debug
+    Spec should do the same.  If an implementation converts some invalid
+    addresses to other invalid addresses, then it is impossible to compare
+    against the original effective address.  To simplify the spec and allow for
+    more implementations, we don't specify which version is compared for an
+    invalid virtual address.
+\end{commentary}
+
 \section{Multiple State Change Instructions} \label{sec:multistate}
 
 An instruction that performs multiple architectural state changes (e.g.,
diff --git a/xml/hwbp_registers.xml b/xml/hwbp_registers.xml
index fc5b6467..ebc0cfaf 100755
--- a/xml/hwbp_registers.xml
+++ b/xml/hwbp_registers.xml
@@ -310,12 +310,6 @@
         Table~\ref{tab:hwbp_timing}, both timings should be supported on load
         address triggers.
 
-        This trigger type may be limited to address comparisons (\FcsrMcontrolSelect is
-        always 0) only. If that is the case and masking is not supported (match
-        values 4, 5, 12, 13), then \RcsrTdataTwo must be able to
-        hold all valid virtual addresses but it need not be capable of holding
-        other values.
-
         The Privileged Spec says that breakpoint exceptions that occur on
         instruction fetches, loads, or stores update the {\tt tval} CSR
         with either zero or the faulting virtual address.  The faulting
@@ -667,12 +661,6 @@
         A chain of triggers must only fire if every trigger in the chain was
         matched by the same instruction.
 
-        This trigger type may be limited to address comparisons (\FcsrMcontrolSixSelect is
-        always 0) only. If that is the case and masking is not supported (match
-        values 4, 5, 12, 13), then \RcsrTdataTwo must be able to
-        hold all valid virtual addresses but it need not be capable of holding
-        other values.
-
         The Privileged Spec says that breakpoint exceptions that occur on
         instruction fetches, loads, or stores update the {\tt tval} CSR
         with either zero or the faulting virtual address.  The faulting