From b138dee77b1991b656c7c69336be0c0050004b4d Mon Sep 17 00:00:00 2001
From: Tim Newsome <tim@sifive.com>
Date: Mon, 20 Nov 2023 10:19:57 -0800
Subject: [PATCH] Allow invalid virtual addresses not to match at all

---
 Sdtrig.tex | 38 +++++++++++++++++++++++++-------------
 1 file changed, 25 insertions(+), 13 deletions(-)

diff --git a/Sdtrig.tex b/Sdtrig.tex
index 5d751821..46d30801 100644
--- a/Sdtrig.tex
+++ b/Sdtrig.tex
@@ -321,23 +321,35 @@ \subsection{Cache Operations}
 
 \subsection{Invalid Virtual Addresses}
 
-For virtual address matches without a mask, \RcsrTdataTwo must be able to hold
-all valid virtual addresses but it need not be capable of holding other values.
-Implementations may convert an invalid virtual address to a different invalid
-virtual address before comparing the address to \RcsrTdataTwo.
+For address matches without a mask, \RcsrTdataTwo must be able to hold all valid
+addresses in all supported translation modes. That means that after writing any
+of these valid addresses, the exact same value is read back, including any high
+bits.
 
 \begin{commentary}
-    A straightforward trigger implementation would compare the effective address
-    to the contents of \RcsrTdataTwo. This is most intuitive to a user setting
-    triggers. However, the Privileged Spec makes various accommodations that
-    allow a shorter representation of invalid virtual addresses, and the Debug
-    Spec should do the same.  If an implementation converts some invalid
-    addresses to other invalid addresses, then it is impossible to compare
-    against the original effective address.  To simplify the spec and allow for
-    more implementations, we don't specify which version is compared for an
-    invalid virtual address.
+    If physical addresses are less than XLEN bits wide, they are zero-extended.
+    If virtual addresses are less than XLEN bits wide, they are sign-extended.
+    Be sure to have enough flops in \RcsrTdataTwo to hold all XLEN bits of the
+    full range of both physical and virtual addresses.
 \end{commentary}
 
+If \RcsrTdataTwo can hold any invalid addresses, then writes of an
+invalid address that can not be represented as-is should be converted to
+a different invalid address that can be represented.
+
+For invalid instruction fetch and load and store effective addresses,
+the compare value may be changed to a different invalid address.
+
+\begin{commentary}
+    A straightforward trigger implementation would compare the instruction fetch
+    and load and store effective addresses to the contents of \RcsrTdataTwo.
+    This is most intuitive to a user setting triggers. Here we accommodate
+    implementations that internally shorten invalid addresses.
+\end{commentary}
+
+In addition, an implementation may choose to inhibit all trigger matching
+against invalid addresses.
+
 \section{Multiple State Change Instructions} \label{sec:multistate}
 
 An instruction that performs multiple architectural state changes (e.g.,