From a9081aa4b152379e114c181a8cad4f51923e8034 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Wed, 21 Aug 2024 13:53:16 -0700 Subject: [PATCH] Clarify Memory Access acts like data access. I'm not sure if this is necessary. Does RISC-V allow data loads to differ from instruction fetches? For a long time any mention of caches was avoided in all specs. Inspired by #1062. --- xml/abstract_commands.xml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/xml/abstract_commands.xml b/xml/abstract_commands.xml index 0833aea0..06215f75 100644 --- a/xml/abstract_commands.xml +++ b/xml/abstract_commands.xml @@ -181,7 +181,10 @@ same project unless stated otherwise. This command lets the debugger perform memory accesses, with the exact same memory view and permissions as the selected hart has. This includes access to hart-local memory-mapped - registers, etc. The command performs the following sequence of + registers, etc. + If the hart treats instruction fetches different from data loads, + then Access Memory gets the data load behavior. + The command performs the following sequence of operations: . Copy data from the memory location specified in `arg1` into the