From 9a1d6971a1c8f6b9d2b7be93eb6afbcca4f03d43 Mon Sep 17 00:00:00 2001 From: Thong Phan Date: Tue, 5 Mar 2024 21:33:55 +0700 Subject: [PATCH] Add The RISC-V Reader: An Open Architecture Atlas --- README.md | 1 + 1 file changed, 1 insertion(+) diff --git a/README.md b/README.md index b3f078f..b8d8dba 100644 --- a/README.md +++ b/README.md @@ -59,6 +59,7 @@ For those with little or no knowledge of digital logic design. After studying th | Resource | Author(s) | Description | Access | Date added | |---|---|---|---|---| | **Digital Design and Computer Architecture RISC-V edition** (good starting point) | Sarah L. Harris, David M. Harris | Covers the foundational knowledge of digital logic design and segues smoothly into RISC-V Processor implementation.

Topics: Number systems and digital representation, Semiconductors and transistors, Logic gates and Digital design, C Programming, RISC-V architecture, RISC-V assembly, Memory systems, Embedded I/O systems | [Amazon book link]| 2024-01-10 | +| **The RISC-V Reader: An Open Architecture Atlas** | David Patterson, Andrew Waterman| A beginner-friendly introduction to the RISC-V instruction set architecture as readers can start programming after the 2nd chapter.

Topics: Computer architecture, RISC-V Instruction Set Architecture (ISA) | [Available in Chineses, Japanese, Spanish, Portuguese and Korean]| 2024-03-05 | | **Nand2Tetris** (optional) | Noam Nisan, Shimon Schocken | A free hands-on tutorial on building a general-purpose computer from logic gates using a hardware simulator.

Topics: Logic gates|[webpage] | 2024-01-10 | |**learn-FPGA episode I: from blinky to RISC-V**|[BrunoLevy](https://github.com/BrunoLevy)|A beginner's introduction to the digital design of a RISC-V softcore on FPGAs. Episode I gently starts from a very basic blinker in Verilog and morphs it step by step into a basic yet fully functional RISC-V SoC. It also explains how to write programs in C and assembly for the SoC.

Topics: Digital design, FPGA, C Programming, RISC-V assembly
Requirement: Basic knowledge of Verilog|[GitHub]| 2024-01-10 | |**Hands-on RISC-V Processor Design**|[Rahul Behl](https://github.com/raulbehl)|This practical tutorial offers a deep dive into the world of computer architecture and processor design, with a specific focus on the RISC-V Instruction Set Architecture (ISA).

Topics: Computer architecture, Processor design, RISC-V Instruction Set Architecture (ISA), SystemVerilog, RISC-V assembly
Requirements: SystemVerilog but not necessary|[webpage] | 2024-01-10 |