From 784ea210da869c0487a0d2fde728f190d9d54ef0 Mon Sep 17 00:00:00 2001 From: Chaoqun Liang Date: Wed, 10 Apr 2024 00:34:43 +0200 Subject: [PATCH] cleanup --- Bender.lock | 15 ++- Bender.yml | 2 +- Makefile | 2 +- cheshire.mk | 8 +- hw/cheshire_soc.sv | 12 +- sw/tests/ethernet.c | 18 +-- target/sim/src/fixture_cheshire_soc.sv | 48 ++++---- target/sim/src/vip_cheshire_soc.sv | 143 ++++++++++------------- target/xilinx/scripts/impl_ip.tcl | 12 +- target/xilinx/src/cheshire_top_xilinx.sv | 66 +++++++++-- target/xilinx/src/phy_definitions.svh | 1 + 11 files changed, 177 insertions(+), 150 deletions(-) diff --git a/Bender.lock b/Bender.lock index 3fcd922b..5e5449d3 100644 --- a/Bender.lock +++ b/Bender.lock @@ -15,8 +15,8 @@ packages: - apb - register_interface axi: - revision: fccffb5953ec8564218ba05e20adbedec845e014 - version: 0.39.1 + revision: ac5deb3ff086aa34b168f392c051e92603d6c0e2 + version: 0.39.2 source: Git: https://github.com/pulp-platform/axi dependencies: @@ -67,8 +67,8 @@ packages: dependencies: - common_cells axi_vga: - revision: 07be187d1e954d8090031b32d236ad76dc62ce45 - version: 0.1.1 + revision: 3718b9930f94a9eaad8ee50b4bccc71df0403084 + version: 0.1.3 source: Git: https://github.com/pulp-platform/axi_vga.git dependencies: @@ -117,7 +117,7 @@ packages: - redundancy_cells - tech_cells_generic ethernet: - revision: ab333c946fbfea18132904f8de0dc6702d67e741 + revision: d7d14161b8f129bccfcf9717f33760cb0a027856 version: null source: Git: git@github.com:pulp-platform/pulp-ethernet.git @@ -190,8 +190,13 @@ packages: - register_interface - tech_cells_generic register_interface: +<<<<<<< HEAD revision: e25b36670ff7aab3402f40efcc2b11ee0f31cf19 version: 0.4.3 +======= + revision: ae616e5a1ec2b41e72d200e5ab09c65e94aebd3d + version: 0.4.4 +>>>>>>> 0465402 (cleanup) source: Git: https://github.com/pulp-platform/register_interface.git dependencies: diff --git a/Bender.yml b/Bender.yml index 9fcf1438..374b436f 100644 --- a/Bender.yml +++ b/Bender.yml @@ -32,7 +32,7 @@ dependencies: serial_link: { git: "https://github.com/pulp-platform/serial_link.git", version: 1.1.1 } tagger: { git: "https://github.com/pulp-platform/transaction-tagger.git", rev: b288376 } unbent: { git: "https://github.com/pulp-platform/unbent.git", version: 0.1.6 } - ethernet: { git: "git@github.com:pulp-platform/pulp-ethernet.git", rev: "ab333c9" } + ethernet: { git: "git@github.com:pulp-platform/pulp-ethernet.git", rev: "d7d1416" } export_include_dirs: - hw/include diff --git a/Makefile b/Makefile index 963d40c3..149dc05c 100644 --- a/Makefile +++ b/Makefile @@ -13,7 +13,7 @@ include cheshire.mk # Inside the repo, forward (prefixed) all, nonfree, and clean targets all: - @$(MAKE) chs-all + @$(MAKE) chs-all %-all: @$(MAKE) chs-$*-all diff --git a/cheshire.mk b/cheshire.mk index 098b7437..f6738ce0 100644 --- a/cheshire.mk +++ b/cheshire.mk @@ -28,6 +28,7 @@ CLINTROOT := $(shell $(BENDER) path clint) AXIRTROOT := $(shell $(BENDER) path axi_rt) AXI_VGA_ROOT := $(shell $(BENDER) path axi_vga) IDMA_ROOT := $(shell $(BENDER) path idma) +ETH_ROOT := $(shell $(BENDER) path ethernet) REGTOOL ?= $(CHS_REG_DIR)/vendor/lowrisc_opentitan/util/regtool.py @@ -48,6 +49,11 @@ ifeq ($(shell test -f $(BENDER_ROOT)/.chs_deps && echo 1),) -include $(BENDER_ROOT)/.chs_deps endif +idma-gen: + make -C $(IDMA_ROOT) idma_hw_all + make -C $(IDMA_ROOT) target/rtl/idma_reg64_2d.hjson + make -C $(ETH_ROOT) eth-gen + # Running this target will reset dependencies (without updating the checked-in Bender.lock) chs-clean-deps: rm -rf .bender @@ -186,7 +192,7 @@ include target/xilinx/xilinx.mk CHS_ALL += $(CHS_SW_ALL) $(CHS_HW_ALL) $(CHS_SIM_ALL) -chs-all: $(CHS_ALL) +chs-all: $(CHS_ALL) idma-gen chs-sw-all: $(CHS_SW_ALL) chs-hw-all: $(CHS_HW_ALL) chs-bootrom-all: $(CHS_BOOTROM_ALL) diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv index f514c79a..6f6a4b06 100644 --- a/hw/cheshire_soc.sv +++ b/hw/cheshire_soc.sv @@ -28,6 +28,8 @@ module cheshire_soc import cheshire_pkg::*; #( input logic test_mode_i, input logic [1:0] boot_mode_i, input logic rtc_i, + input logic eth_clk_125, + input logic eth_clk_90, // External AXI LLC (DRAM) port output axi_ext_llc_req_t axi_llc_mst_req_o, input axi_ext_llc_rsp_t axi_llc_mst_rsp_i, @@ -81,9 +83,7 @@ module cheshire_soc import cheshire_pkg::*; #( output logic eth_txck_o, output logic [3:0] eth_txd_o, output logic eth_txctl_o, - output logic eth_rstn_o, - input logic eth_intn_i, - input logic eth_pme_i, + output logic eth_rstn_o, input logic eth_mdio_i, output logic eth_mdio_o, output logic eth_mdio_oe, @@ -1376,7 +1376,9 @@ module cheshire_soc import cheshire_pkg::*; #( .reg_rsp_t ( reg_rsp_t ) ) i_tx_eth_idma_wrap ( .clk_i, - .rst_ni, + .rst_ni, + .eth_clk_i ( eth_clk_125 ), + .eth_clk90_i ( eth_clk_90 ), .phy_rx_clk_i ( eth_rxck_i ), .phy_rxd_i ( eth_rxd_i ), .phy_rx_ctl_i ( eth_rxctl_i ), @@ -1386,7 +1388,7 @@ module cheshire_soc import cheshire_pkg::*; #( .phy_resetn_o ( eth_rstn_o ), .phy_intn_i ( 1'b1 ), .phy_pme_i ( 1'b1 ), - .phy_mdio_i ( 1'b0 ), + .phy_mdio_i ( eth_mdio_i ), .phy_mdio_o ( eth_mdio_o ), .phy_mdio_oe ( eth_mdio_oe ), .phy_mdc_o ( eth_mdc_o ), diff --git a/sw/tests/ethernet.c b/sw/tests/ethernet.c index 6850eb10..dd8a1cd3 100644 --- a/sw/tests/ethernet.c +++ b/sw/tests/ethernet.c @@ -38,7 +38,6 @@ int main(void) { *tx_addr = data_to_write[i]; } - *reg32(ETH_BASE, MACLO_OFFSET) = 0x98001032; *reg32(ETH_BASE, MACHI_OFFSET) = 0x00012070; @@ -52,21 +51,8 @@ int main(void) { *reg32(ETH_BASE, IDMA_REQ_VALID_OFFSET) = 0x1; *reg32(ETH_BASE, IDMA_REQ_VALID_OFFSET) = 0x0; *reg32(ETH_BASE, IDMA_RSP_READY_OFFSET) = 0x1; - - // pulp_write32( ETH_BASE + IDMA_REQ_VALID_OFFSET , 0x1); - - // pulp_write32( ETH_BASE + IDMA_REQ_VALID_OFFSET , 0x0); - - - // // data - // pulp_write32( ETH_BASE + IDMA_RSP_READY_OFFSET , 0x1); - // to-do deassert rsp_ready when rx transaction is complete - - - - while(1); - - //return 0; + // can leave rsp_ready high + return 0; } diff --git a/target/sim/src/fixture_cheshire_soc.sv b/target/sim/src/fixture_cheshire_soc.sv index 332e024d..cc6b1854 100644 --- a/target/sim/src/fixture_cheshire_soc.sv +++ b/target/sim/src/fixture_cheshire_soc.sv @@ -49,19 +49,19 @@ module fixture_cheshire_soc #( logic i2c_scl_i; logic i2c_scl_en; - logic eth_rxck_i; - logic [3:0] eth_rxd_i; - logic eth_rxctl_i; - logic eth_txck_o; - logic [3:0] eth_txd_o; - logic eth_txctl_o; - logic eth_rstn_o; - logic eth_intn_i; - logic eth_pme_i; + logic eth_clk_125; + logic eth_clk_90; + logic eth_rxck; + logic [3:0] eth_rxd; + logic eth_rxctl; + logic eth_txck; + logic [3:0] eth_txd; + logic eth_txctl; + logic eth_rstn; logic eth_mdio_i; logic eth_mdio_o; logic eth_mdio_en; - logic eth_mdc_o; + logic eth_mdc; logic spih_sck_o; logic spih_sck_en; @@ -129,19 +129,19 @@ module fixture_cheshire_soc #( .i2c_scl_o ( i2c_scl_o ), .i2c_scl_i ( i2c_scl_i ), .i2c_scl_en_o ( i2c_scl_en ), - .eth_rxck_i ( eth_rxck_i ), - .eth_rxd_i ( eth_rxd_i ), - .eth_rxctl_i ( eth_rxctl_i ), - .eth_txck_o ( eth_txck_o ), - .eth_txd_o ( eth_txd_o ), - .eth_txctl_o ( eth_txctl_o ), - .eth_rstn_o ( eth_rstn_o ), - .eth_intn_i ( eth_intn_i ), - .eth_pme_i ( eth_pme_i ), + .eth_clk_125 ( eth_clk_125 ), + .eth_clk_90 ( eth_clk_90 ), + .eth_rxck_i ( eth_rxck ), + .eth_rxd_i ( eth_rxd ), + .eth_rxctl_i ( eth_rxctl ), + .eth_txck_o ( eth_txck ), + .eth_txd_o ( eth_txd ), + .eth_txctl_o ( eth_txctl ), + .eth_rstn_o ( eth_rstn ), .eth_mdio_i ( eth_mdio_i ), .eth_mdio_o ( eth_mdio_o ), .eth_mdio_oe ( eth_mdio_en ), - .eth_mdc_o ( eth_mdc_o ), + .eth_mdc_o ( eth_mdc ), .spih_sck_o ( spih_sck_o ), .spih_sck_en_o ( spih_sck_en ), .spih_csb_o ( spih_csb_o ), @@ -174,15 +174,7 @@ module fixture_cheshire_soc #( wire [SpihNumCs-1:0] spih_csb; wire [ 3:0] spih_sd; - wire [ 3:0] eth_txd; - wire [ 3:0] eth_rxd; - wire eth_txck; - wire eth_rxck; - wire eth_txctl; - wire eth_rxctl; - wire eth_rstn; wire eth_mdio; - wire eth_mdc; vip_cheshire_soc_tristate vip_tristate (.*); diff --git a/target/sim/src/vip_cheshire_soc.sv b/target/sim/src/vip_cheshire_soc.sv index 317a224e..d7d8efab 100644 --- a/target/sim/src/vip_cheshire_soc.sv +++ b/target/sim/src/vip_cheshire_soc.sv @@ -21,6 +21,7 @@ module vip_cheshire_soc import cheshire_pkg::*; #( parameter time ClkPeriodSys = 5ns, parameter time ClkPeriodJtag = 20ns, parameter time ClkPeriodRtc = 30518ns, + parameter time ClkPeriodEth125 = 8ns, parameter int unsigned RstCycles = 5, parameter real TAppl = 0.1, parameter real TTest = 0.9, @@ -69,15 +70,17 @@ module vip_cheshire_soc import cheshire_pkg::*; #( inout wire [SpihNumCs-1:0] spih_csb, inout wire [ 3:0] spih_sd, // Ethernet interface - inout wire [ 3:0] eth_txd, - inout wire [ 3:0] eth_rxd, - inout wire eth_txck, - inout wire eth_rxck, - inout wire eth_txctl, - inout wire eth_rxctl, - inout wire eth_rstn, - inout wire eth_mdio, - inout wire eth_mdc, + output logic eth_clk_125, + output logic eth_clk_90, + input logic [ 3:0] eth_txd, + output logic [ 3:0] eth_rxd, + input logic eth_txck, + output logic eth_rxck, + input logic eth_txctl, + output logic eth_rxctl, + input logic eth_rstn, + inout logic eth_mdio, + input logic eth_mdc, // Serial link interface output logic [SlinkNumChan-1:0] slink_rcv_clk_i, input logic [SlinkNumChan-1:0] slink_rcv_clk_o, @@ -649,21 +652,23 @@ module vip_cheshire_soc import cheshire_pkg::*; #( .reg_req_t ( reg_req_t ), .reg_rsp_t ( reg_rsp_t ) ) i_rx_eth_idma_wrap ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .phy_rx_clk_i ( eth_txck ), - .phy_rxd_i ( eth_txd ), - .phy_rx_ctl_i ( eth_txctl ), - .phy_tx_clk_o ( eth_rxck ), - .phy_txd_o ( eth_rxd ), - .phy_tx_ctl_o ( eth_rxctl ), - .phy_resetn_o ( eth_rstn ), + .clk_i ( clk ), + .rst_ni ( rst_n ), + .eth_clk_i ( eth_clk_125 ), + .eth_clk90_i ( eth_clk_90 ), + .phy_rx_clk_i ( eth_txck ), + .phy_rxd_i ( eth_txd ), + .phy_rx_ctl_i ( eth_txctl ), + .phy_tx_clk_o ( eth_rxck ), + .phy_txd_o ( eth_rxd ), + .phy_tx_ctl_o ( eth_rxctl ), + .phy_resetn_o ( eth_rstn ), .phy_intn_i ( 1'b1 ), .phy_pme_i ( 1'b1 ), - .phy_mdio_i ( 1'b0 ), - .phy_mdio_o ( ), - .phy_mdio_oe ( ), - .phy_mdc_o ( ), + .phy_mdio_i ( eth_mdio_i ), + .phy_mdio_o ( eth_mdio_o ), + .phy_mdio_oe ( eth_mdio_oe ), + .phy_mdc_o ( eth_mdc ), .reg_req_i ( reg_bus_rx_req ), .reg_rsp_o ( reg_bus_rx_rsp ), .testmode_i ( 1'b0 ), @@ -703,12 +708,30 @@ module vip_cheshire_soc import cheshire_pkg::*; #( .mon_w_addr_o ( /* NOT CONNECTED */ ), .mon_w_valid_o ( /* NOT CONNECTED */ ) ); - + initial begin + forever begin + eth_clk_125 <= 0; + #(ClkPeriodEth125/2); + eth_clk_125 <= 1; + #(ClkPeriodEth125/2); + end + end - @(posedge clk); + initial begin + forever begin + eth_clk_90 <= 0; + #(ClkPeriodEth125/4); + eth_clk_90 <= 1; + #(ClkPeriodEth125/2); + eth_clk_90 <= 0; + #(ClkPeriodEth125/4); + end + end - $readmemh("/scratch/chaol/cheshire/target/sim/src/rx_mem_init.vmem", i_rx_axi_sim_mem.mem); + initial begin + @(posedge clk); + $readmemh("rx_mem_init.vmem", i_rx_axi_sim_mem.mem); @(posedge clk); reg_drv_rx.send_write( 'h0300c000, 32'h98001032, 'hf, reg_error); //lower 32bits of MAC address @@ -732,37 +755,21 @@ module vip_cheshire_soc import cheshire_pkg::*; #( reg_drv_rx.send_write( 'h0300c020, 32'h0,'hf , reg_error); // dst protocol @(posedge clk); - // @(posedge data_ready); + reg_drv_rx.send_write( 'h0300c038, 'h1, 'hf , reg_error); // req valid + @(posedge clk); - //#9000ns; + reg_drv_rx.send_write( 'h0300c040, 'h1, 'hf, reg_error); - // while(1) begin - // reg_drv_rx.send_read( 'h3000003c, rx_req_ready, reg_error); - // if(rx_req_ready) begin - reg_drv_rx.send_write( 'h0300c038, 'h1, 'hf , reg_error); // req valid + while(1) begin + reg_drv_rx.send_read( 'h0300c044, rx_rsp_valid, reg_error); + if(rx_rsp_valid) begin + reg_drv_rx.send_write( 'h0300c040, 32'h0, 'hf , reg_error); + @(posedge clk); + break; + end @(posedge clk); -// break; -// end -// @(posedge clk_i); -// end - -@(posedge clk); - - -reg_drv_rx.send_write( 'h0300c040, 'h1, 'hf, reg_error); //rsp ready -//repeat(25)@(posedge clk_i); -//reg_drv_rx.send_write( 'h30000038, 'h0, 'hf , reg_error); // req valid - -while(1) begin -reg_drv_rx.send_read( 'h0300c044, rx_rsp_valid, reg_error); - if(rx_rsp_valid) begin -reg_drv_rx.send_write( 'h0300c040, 32'h0, 'hf , reg_error); -@(posedge clk); -break; -end -@(posedge clk); -end - end + end +end /////////////////// // Serial Link // @@ -1103,18 +1110,9 @@ module vip_cheshire_soc_tristate import cheshire_pkg::*; ( input logic [ 3:0] spih_sd_o, input logic [ 3:0] spih_sd_en, // Ethernet pad IO - output logic [3:0] eth_rxd_i, - input logic [3:0] eth_txd_o, - output logic eth_rxck_i, - input logic eth_txck_o, - output logic eth_rxctl_i, - input logic eth_txctl_o, - input logic eth_rstn_o, input logic eth_mdio_o, output logic eth_mdio_i, - input logic eth_mdio_en, - input logic eth_mdc_o, - + input logic eth_mdio_en, // I2C wires inout wire i2c_sda, inout wire i2c_scl, @@ -1123,15 +1121,7 @@ module vip_cheshire_soc_tristate import cheshire_pkg::*; ( inout wire [SpihNumCs-1:0] spih_csb, inout wire [ 3:0] spih_sd, // Ethernet wires - inout wire [ 3:0] eth_txd, - inout wire [ 3:0] eth_rxd, - inout wire eth_txck, - inout wire eth_rxck, - inout wire eth_txctl, - inout wire eth_rxctl, - inout wire eth_rstn, - inout wire eth_mdio, - inout wire eth_mdc + input wire eth_mdio ); // I2C @@ -1158,15 +1148,6 @@ module vip_cheshire_soc_tristate import cheshire_pkg::*; ( end // Ethernet - assign eth_txd = eth_txd_o; - assign eth_txck = eth_txck_o; - assign eth_txctl = eth_txctl_o; - assign eth_mdc = eth_mdc_o; - assign eth_rxd_i = eth_rxd; - assign eth_rxck_i = eth_rxck; - assign eth_rxctl_i = eth_rxctl; - - bufif1 (eth_mdio_i, eth_mdio, ~eth_mdio_en); bufif1 (eth_mdio, eth_mdio_o, eth_mdio_en); diff --git a/target/xilinx/scripts/impl_ip.tcl b/target/xilinx/scripts/impl_ip.tcl index 474787fe..1dc82bec 100644 --- a/target/xilinx/scripts/impl_ip.tcl +++ b/target/xilinx/scripts/impl_ip.tcl @@ -24,13 +24,15 @@ switch $proj { CONFIG.CLKOUT2_USED {true} \ CONFIG.CLKOUT3_USED {true} \ CONFIG.CLKOUT4_USED {true} \ - CONFIG.CLK_OUT1_PORT {clk_100} \ + CONFIG.CLK_OUT1_PORT {clk_200} \ CONFIG.CLK_OUT2_PORT {clk_50} \ - CONFIG.CLK_OUT3_PORT {clk_20} \ - CONFIG.CLK_OUT4_PORT {clk_10} \ + CONFIG.CLK_OUT3_PORT {clk_125} \ + CONFIG.CLK_OUT4_PORT {clk_125_90} \ + CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {200.000} \ CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {50.000} \ - CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {20.000} \ - CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {10.000} \ + CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {125.000} \ + CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {125.000} \ + CONFIG.CLKOUT4_REQUESTED_PHASE {90.000} \ CONFIG.CLKIN1_JITTER_PS {50.0} \ CONFIG.MMCM_CLKFBOUT_MULT_F {5.000} \ CONFIG.MMCM_CLKIN1_PERIOD {5.000} \ diff --git a/target/xilinx/src/cheshire_top_xilinx.sv b/target/xilinx/src/cheshire_top_xilinx.sv index bddac283..63a0932b 100644 --- a/target/xilinx/src/cheshire_top_xilinx.sv +++ b/target/xilinx/src/cheshire_top_xilinx.sv @@ -48,6 +48,18 @@ module cheshire_top_xilinx ( inout wire i2c_sda_io, `endif +`ifdef USE_ETHERNET + input wire eth_rxck, + input wire [3:0] eth_rxd, + input wire eth_rxctl, + output wire eth_txck, + output wire [3:0] eth_txd, + output wire eth_txctl, + output wire eth_rst_n, + output wire eth_mdc, + inout wire eth_mdio, +`endif + `ifdef USE_SD input logic sd_cd_i, output logic sd_cmd_o, @@ -101,6 +113,7 @@ module cheshire_top_xilinx ( endfunction // Configure cheshire for FPGA mapping + localparam cheshire_cfg_t FPGACfg = gen_cheshire_xilinx_cfg(); `CHESHIRE_TYPEDEF_ALL(, FPGACfg) @@ -110,6 +123,8 @@ module cheshire_top_xilinx ( wire sys_clk; wire soc_clk; + logic eth_clk_125; + logic eth_clk_90; IBUFDS #( .IBUF_LOW_PWR ("FALSE") @@ -120,13 +135,13 @@ module cheshire_top_xilinx ( ); clkwiz i_clkwiz ( - .clk_in1 ( sys_clk ), - .reset ( '0 ), - .locked ( ), - .clk_100 ( ), - .clk_50 ( soc_clk ), - .clk_20 ( ), - .clk_10 ( ) + .clk_in1 ( sys_clk ), + .reset ( '0 ), + .locked ( ), + .clk_200 ( ), + .clk_50 ( soc_clk ), + .clk_125 ( eth_clk_125 ), + .clk_125_90 ( eth_clk_90 ) ); ///////////////////// @@ -236,8 +251,32 @@ module cheshire_top_xilinx ( .I ( i2c_sda_soc_out ), .T ( ~i2c_sda_en ) ); + `endif + + /////////////////////// + // Ethernet Adaption // + ////////////////////// +`ifdef USE_ETHERNET + + logic eth_mdio_i; + logic eth_mdio_o; + logic eth_mdio_oe; + + IOBUF #( + .DRIVE ( 12 ), // Specify the output drive strength + .IBUF_LOW_PWR ( "FALSE" ), // Low Power - "TRUE", High Performance = "FALSE" + .IOSTANDARD ( "DEFAULT" ), // Specify the I/O standard + .SLEW ( "FAST" ) // Specify the output slew rate + ) i_md_iobuf ( + .O ( eth_mdio_i ), // Buffer output + .IO ( eth_mdio ), // Buffer inout port (connect directly to top-level port) + .I ( eth_mdio_o ), // Buffer input + .T ( ~eth_mdio_oe ) // 3-state enable input, high=input, low=output + ); + `endif + /////////////// // SPI to SD // /////////////// @@ -446,6 +485,19 @@ module cheshire_top_xilinx ( .i2c_scl_o ( i2c_scl_soc_out ), .i2c_scl_i ( i2c_scl_soc_in ), .i2c_scl_en_o ( i2c_scl_en ), + .eth_clk_125 ( eth_clk_125 ), + .eth_clk_90 ( eth_clk_90 ), + .eth_rxck_i ( eth_rxck ), + .eth_rxd_i ( eth_rxd ), + .eth_rxctl_i ( eth_rxctl ), + .eth_txck_o ( eth_txck ), + .eth_txd_o ( eth_txd ), + .eth_txctl_o ( eth_txctl ), + .eth_rstn_o ( eth_rstn ), + .eth_mdio_i ( eth_mdio_i ), + .eth_mdio_o ( eth_mdio_o ), + .eth_mdio_oe ( eth_mdio_en ), + .eth_mdc_o ( eth_mdc ), .spih_sck_o ( spi_sck_soc ), .spih_sck_en_o ( spi_sck_en ), .spih_csb_o ( spi_cs_soc ), diff --git a/target/xilinx/src/phy_definitions.svh b/target/xilinx/src/phy_definitions.svh index a4d7798d..bd14caf3 100644 --- a/target/xilinx/src/phy_definitions.svh +++ b/target/xilinx/src/phy_definitions.svh @@ -25,6 +25,7 @@ `define USE_VIO `define USE_I2C `define USE_VGA + `define USE_ETHERNET `endif `ifdef TARGET_ZCU102