diff --git a/Bender.lock b/Bender.lock index 5233e008..5500852f 100644 --- a/Bender.lock +++ b/Bender.lock @@ -60,8 +60,8 @@ packages: dependencies: - common_cells axi_vga: - revision: 3718b9930f94a9eaad8ee50b4bccc71df0403084 - version: 0.1.3 + revision: 4d3e70d4f47bb74edc1ab68d99ffc02382e0fb9e + version: 0.1.4 source: Git: https://github.com/pulp-platform/axi_vga.git dependencies: @@ -162,7 +162,7 @@ packages: - register_interface - tech_cells_generic pulp-ethernet: - revision: a8e69091528d5e8d2a7091082643e5a7c81d2ffd + revision: 8d16844b50178105f388c0fe2f585571c4780351 version: null source: Git: https://github.com/pulp-platform/pulp-ethernet.git @@ -174,8 +174,8 @@ packages: - idma - register_interface register_interface: - revision: ae616e5a1ec2b41e72d200e5ab09c65e94aebd3d - version: 0.4.4 + revision: 5daa85d164cf6b54ad061ea1e4c6f3624556e467 + version: 0.4.5 source: Git: https://github.com/pulp-platform/register_interface.git dependencies: diff --git a/Bender.yml b/Bender.yml index fb465c6a..e01636c8 100644 --- a/Bender.yml +++ b/Bender.yml @@ -30,7 +30,7 @@ dependencies: riscv-dbg: { git: "https://github.com/pulp-platform/riscv-dbg.git", version: 0.8.1 } serial_link: { git: "https://github.com/pulp-platform/serial_link.git", version: 1.1.1 } unbent: { git: "https://github.com/pulp-platform/unbent.git", version: 0.1.6 } - pulp-ethernet: { git: "https://github.com/pulp-platform/pulp-ethernet.git", rev: "a8e6909" } # branch: chs-hs + pulp-ethernet: { git: "https://github.com/pulp-platform/pulp-ethernet.git", rev: "8d16844" } # branch: chs-hs export_include_dirs: - hw/include diff --git a/sw/tests/ethernet.c b/sw/tests/ethernet.c index 7c9ff92a..f63e29cc 100644 --- a/sw/tests/ethernet.c +++ b/sw/tests/ethernet.c @@ -50,14 +50,14 @@ int main(void) { *reg32(PLIC_BASE, RV_PLIC_IE0_0_REG_OFFSET) |= (1 << (RV_PLIC_IE0_0_E_19_BIT)); // Enable interrupt number ; volatile uint64_t data_to_write[DATA_CHUNK] = { - 0x0207230100890702, + 0x1032230100890702, 0x3210400020709800, - 0x1716151413121110, - 0x2726252423222120, - 0x3736353433323130, - 0x4746454443424140, - 0x5756555453525150, - 0x6766656463626160 + 0x35ED077D93FC89BA, + 0x56BE7F8D79A46B8C, + 0xAEB3F2D1446FE19E, + 0x7D21C83EFF976DB8, + 0x940D2024EB89AC07, + 0x2B9EBCDC4561DA5C }; // load data into mem @@ -66,9 +66,9 @@ int main(void) { *tx_addr = data_to_write[i]; } - *reg32(ETH_BASE, MACLO_OFFSET) = 0x00890702; - // High 16 bit Mac Address - *reg32(ETH_BASE, MACHI_OFFSET) = 0x00802301; + *reg32(ETH_BASE, MACLO_OFFSET) = 0x89000123; + // High 16 bit Mac Address and irq_en + *reg32(ETH_BASE, MACHI_OFFSET) = 0x00800207; // DMA Source Address *reg32(ETH_BASE, IDMA_SRC_ADDR_OFFSET) = TX_BASE; // DMA Destination Address @@ -83,17 +83,17 @@ int main(void) { // Validate Request to DMA *reg32(ETH_BASE, IDMA_REQ_VALID_OFFSET) = 0x1; - // uint32_t *mdio; - // // mdio = reg32(ETH_BASE, ETH_MDIO_OFFSET); - // mdio = 0x0300c008; - // printf("MDIO value: 0x%08X\n", *mdio); + uint32_t *mdio; + // mdio = reg32(ETH_BASE, ETH_MDIO_OFFSET); + mdio = 0x0300c008; + printf("MDIO value: 0x%08X\n", *mdio); // configure ethernet - *reg32(ETH_BASE, MACLO_OFFSET) = 0x00890702; - *reg32(ETH_BASE, MACHI_OFFSET) = 0x00802301; + *reg32(ETH_BASE, MACLO_OFFSET) = 0x89000123; + *reg32(ETH_BASE, MACHI_OFFSET) = 0x00800207; // rx irq while (!(*reg32(PLIC_BASE, RV_PLIC_IP_0_OFFSET)) & (1 << 19) ); - + // dma length ready, dma can be configured now while (!(*reg32(ETH_BASE,IDMA_RX_EN_OFFSET))); @@ -104,6 +104,10 @@ int main(void) { *reg32(ETH_BASE, IDMA_DST_PROTO_OFFSET) = 0x0; *reg32(ETH_BASE, IDMA_REQ_VALID_OFFSET) = 0x1; + uint32_t *rx_fcs; + rx_fcs = 0x0300c014; + printf("rfcs value: 0x%08X\n", *rx_fcs); + // wait until DMA moves all data while (!(*reg32(ETH_BASE, IDMA_RSP_VALID_OFFSET))); diff --git a/target/sim/src/fixture_cheshire_soc.sv b/target/sim/src/fixture_cheshire_soc.sv index a5e6de45..e0fa0a93 100644 --- a/target/sim/src/fixture_cheshire_soc.sv +++ b/target/sim/src/fixture_cheshire_soc.sv @@ -138,7 +138,7 @@ module fixture_cheshire_soc #( .eth_txd_o ( eth_txd ), .eth_txctl_o ( eth_txctl ), .eth_rstn_o ( eth_rstn ), - .eth_mdio_i ( 1'b1 ),// eth_mdio_i + .eth_mdio_i ( 1'b0 ),// eth_mdio_i .eth_mdio_o ( eth_mdio_o ), .eth_mdio_oe ( eth_mdio_en ), .eth_mdc_o ( eth_mdc ), diff --git a/target/sim/src/vip_cheshire_soc.sv b/target/sim/src/vip_cheshire_soc.sv index d47767e3..57828058 100644 --- a/target/sim/src/vip_cheshire_soc.sv +++ b/target/sim/src/vip_cheshire_soc.sv @@ -728,10 +728,10 @@ module vip_cheshire_soc import cheshire_pkg::*; #( @(posedge clk) - reg_drv_rx.send_write( 'h0300c000, 32'h00890702, 'hf, reg_error); //lower 32bits of MAC address + reg_drv_rx.send_write( 'h0300c000, 32'h89000123, 'hf, reg_error); //lower 32bits of MAC address @(posedge clk); - reg_drv_rx.send_write( 'h0300c004, 'h802301, 'hf, reg_error); //upper 16bits of MAC address + other configuration set to false/0 + reg_drv_rx.send_write( 'h0300c004, 32'h00800207, 'hf, reg_error); //upper 16bits of MAC address + other configuration set to false/0 @(posedge clk); @(posedge eth_rx_irq); @@ -768,10 +768,10 @@ module vip_cheshire_soc import cheshire_pkg::*; #( end // Tx test starts here: external back to core - reg_drv_rx.send_write( 'h0300c000, 32'h00890702, 'hf, reg_error); //lower 32bits of MAC address + reg_drv_rx.send_write( 'h0300c000, 32'h89000123, 'hf, reg_error); //lower 32bits of MAC address @(posedge clk); - reg_drv_rx.send_write( 'h0300c004, 32'h00802301, 'hf, reg_error); //upper 16bits of MAC address + other configuration set to false/0 + reg_drv_rx.send_write( 'h0300c004, 32'h00800207, 'hf, reg_error); //upper 16bits of MAC address + other configuration set to false/0 @(posedge clk); reg_drv_rx.send_write( 'h0300c01c, 32'h0, 'hf, reg_error ); // SRC_ADDR