diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 6298467a83..5b18be59f8 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -63,12 +63,15 @@ jobs: strategy: matrix: testcase: [ cv64a6_imafdc_tests ] - config: [ cv64a6_imafdc_sv39_hpdcache, cv64a6_imafdc_sv39_wb, cv64a6_imafdc_sv39 ] + config: [ cv64a6_imafdc_sv39_hpdcache, cv64a6_imafdc_sv39_hpdcache_wb, cv64a6_imafdc_sv39_wb, cv64a6_imafdc_sv39 ] simulator: [ veri-testharness ] include: - testcase: dv-riscv-arch-test config: cv64a6_imafdc_sv39_hpdcache simulator: veri-testharness + - testcase: dv-riscv-arch-test + config: cv64a6_imafdc_sv39_hpdcache_wb + simulator: veri-testharness needs: build-riscv-tests steps: diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index c3f0a6a391..cc62fda9cd 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -170,6 +170,7 @@ smoke-gen: SPIKE_TANDEM: 1 script: - bash verif/regress/smoke-gen_tests.sh + - cp verif/sim/seedlist.yaml artifacts/logs/ - !reference [.simu_after_script] smoke-bench: diff --git a/.gitlab-ci/expected_synth.yml b/.gitlab-ci/expected_synth.yml index 2a2590234d..c485076580 100644 --- a/.gitlab-ci/expected_synth.yml +++ b/.gitlab-ci/expected_synth.yml @@ -1,2 +1,2 @@ cv32a65x: - gates: 188652 + gates: 184701 diff --git a/.readthedocs.yaml b/.readthedocs.yaml index 355531d453..d9241c3843 100644 --- a/.readthedocs.yaml +++ b/.readthedocs.yaml @@ -7,6 +7,7 @@ version: 2 submodules: include: - docs/riscv-isa/riscv-isa-manual + recursive: true build: os: "ubuntu-20.04" @@ -26,7 +27,7 @@ build: - npm install docs/riscv-isa/riscv-isa-manual/dependencies - gem install -g docs/riscv-isa/riscv-isa-manual/dependencies/Gemfile pre_build: - - make -C docs prepare + - PATH=$PWD/node_modules/.bin:$PATH make -C docs prepare # Build from the docs directory with Sphinx sphinx: diff --git a/Makefile b/Makefile index 9731d901b0..915b2df775 100644 --- a/Makefile +++ b/Makefile @@ -40,7 +40,10 @@ torture-logs := elf_file ?= tmp/riscv-tests/build/benchmarks/dhrystone.riscv # board name for bitstream generation. Currently supported: kc705, genesys2, nexys_video BOARD ?= genesys2 - +ALTERA_BOARD ?= DK-DEV-AGF014E3ES +ALTERA_FAMILY ?= "AGILEX" +ALTERA_PART ?= AGFB014R24B2E2V +PLATFORM = "PLAT_XILINX" # root path mkfile_path := $(abspath $(lastword $(MAKEFILE_LIST))) root-dir := $(dir $(mkfile_path)) @@ -166,17 +169,11 @@ src := $(if $(spike-tandem),verif/tb/core/uvma_core_cntrl_pkg.sv) $(wildcard corev_apu/fpga/src/axi_slice/src/*.sv) \ $(wildcard corev_apu/src/axi_riscv_atomics/src/*.sv) \ $(wildcard corev_apu/axi_mem_if/src/*.sv) \ + $(wildcard corev_apu/riscv-dbg/src/*.sv) \ corev_apu/rv_plic/rtl/rv_plic_target.sv \ corev_apu/rv_plic/rtl/rv_plic_gateway.sv \ corev_apu/rv_plic/rtl/plic_regmap.sv \ corev_apu/rv_plic/rtl/plic_top.sv \ - corev_apu/riscv-dbg/src/dmi_cdc.sv \ - corev_apu/riscv-dbg/src/dmi_jtag.sv \ - corev_apu/riscv-dbg/src/dmi_jtag_tap.sv \ - corev_apu/riscv-dbg/src/dm_csrs.sv \ - corev_apu/riscv-dbg/src/dm_mem.sv \ - corev_apu/riscv-dbg/src/dm_sba.sv \ - corev_apu/riscv-dbg/src/dm_top.sv \ corev_apu/riscv-dbg/debug_rom/debug_rom.sv \ corev_apu/register_interface/src/apb_to_reg.sv \ vendor/pulp-platform/axi/src/axi_multicut.sv \ @@ -236,6 +233,52 @@ uart_src_sv:= corev_apu/fpga/src/apb_uart/src/slib_clock_div.sv \ uart_src_sv := $(addprefix $(root-dir), $(uart_src_sv)) fpga_src := $(wildcard corev_apu/fpga/src/*.sv) $(wildcard corev_apu/fpga/src/ariane-ethernet/*.sv) common/local/util/tc_sram_fpga_wrapper.sv common/local/util/hpdcache_sram_1rw.sv common/local/util/hpdcache_sram_wbyteenable_1rw.sv vendor/pulp-platform/fpga-support/rtl/SyncSpRamBeNx64.sv vendor/pulp-platform/fpga-support/rtl/SyncSpRamBeNx32.sv vendor/pulp-platform/fpga-support/rtl/SyncSpRam.sv + +altera_src := $(shell find $(root-dir)/corev_apu/altera/src -type f \( -name "*.v" -o -name "*.sv" -o -name "*.svh" \) -print | sed 's|//|/|g') +altera_src += $(src) +altera_src += $(shell find $(root-dir)/corev_apu/fpga/src -type f \( -name "*.v" -o -name "*.sv" \) -print | sed 's|//|/|g') +altera_src += $(shell find $(root-dir)core/cvfpu/src/common_cells/src/ -maxdepth 1 -type f \( -name "*.v" -o -name "*.sv" -o -name "*.vhd" -o -name "*.svh" \) -print) +altera_axi_src := $(shell find $(root-dir)/vendor/pulp-platform/axi/src -type f \( -name "*.v" -o -name "*.sv" \) -print | sed 's|//|/|g') + +altera_src += $(root-dir)corev_apu/rv_plic/rtl/top_pkg.sv \ + $(root-dir)corev_apu/rv_plic/rtl/tlul_pkg.sv \ + $(root-dir)corev_apu/rv_plic/rtl/rv_plic_reg_top.sv \ + $(root-dir)corev_apu/rv_plic/rtl/rv_plic_reg_pkg.sv \ + $(root-dir)corev_apu/rv_plic/rtl/rv_plic.sv \ + $(root-dir)corev_apu/rv_plic/rtl/prim_subreg_ext.sv \ + $(root-dir)corev_apu/rv_plic/rtl/prim_subreg.sv \ + $(root-dir)vendor/pulp-platform/common_cells/src/cdc_fifo_gray.sv \ + $(root-dir)riscv-dbg/src/dm_obi_top.sv \ + $(root-dir)core/include/instr_tracer_pkg.sv \ + $(root-dir)core/cvfpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_mvp_wrapper.sv \ + $(root-dir)core/cache_subsystem/amo_alu.sv + +altera_filter := corev_apu/tb/ariane_testharness.sv \ + corev_apu/tb/ariane_peripherals.sv \ + corev_apu/tb/rvfi_tracer.sv \ + corev_apu/tb/common/uart.sv \ + corev_apu/tb/common/SimDTM.sv \ + corev_apu/tb/common/SimJTAG.sv \ + corev_apu/fpga/src/apb/src/apb_test.sv \ + corev_apu/fpga/src/ariane_xilinx.sv \ + corev_apu/fpga/ariane_peripherals_xilinx.sv \ + corev_apu/fpga/src/apb/test/tb_apb_cdc.sv \ + corev_apu/fpga/src/apb/test/tb_apb_regs.sv \ + corev_apu/fpga/src/apb/test/tb_apb_demux.sv \ + corev_apu/fpga/src/gpio/test/tb_gpio.sv \ + vendor/pulp-platform/axi/src/axi_test.sv \ + corev_apu/riscv-dbg/src/dm_pkg.sv \ + corev_apu/riscv-dbg/src/dmi_jtag_tap.sv \ + corev_apu/riscv-dbg/src/dmi_jtag.sv \ + corev_apu/fpga/src/apb_uart/src/reg_uart_wrap.sv + +altera_filter := $(addprefix $(root-dir), $(altera_filter)) +xil_debug_filter = $(addprefix $(root-dir), corev_apu/riscv-dbg/src/dm_obi_top.sv) +xil_debug_filter += $(addprefix $(root-dir), corev_apu/riscv-dbg/src/dm_pkg.sv) +xil_debug_filter += $(addprefix $(root-dir), corev_apu/riscv-dbg/src/dmi_vjtag_tap.sv) +xil_debug_filter += $(addprefix $(root-dir), corev_apu/riscv-dbg/src/dmi_vjtag.sv) +src := $(filter-out $(xil_debug_filter), $(src)) + fpga_src := $(addprefix $(root-dir), $(fpga_src)) src/bootrom/bootrom_$(XLEN).sv # look for testbenches @@ -738,7 +781,7 @@ fpga_filter += $(addprefix $(root-dir), core/cache_subsystem/hpdcache/rtl/src/co fpga_filter += $(addprefix $(root-dir), core/cache_subsystem/hpdcache/rtl/src/common/macros/behav/hpdcache_sram_wmask_1rw.sv) src/bootrom/bootrom_$(XLEN).sv: - $(MAKE) -C corev_apu/fpga/src/bootrom BOARD=$(BOARD) XLEN=$(XLEN) bootrom_$(XLEN).sv + $(MAKE) -C corev_apu/fpga/src/bootrom BOARD=$(BOARD) XLEN=$(XLEN) PLATFORM=$(PLATFORM) bootrom_$(XLEN).sv fpga: $(ariane_pkg) $(src) $(fpga_src) $(uart_src) $(src_flist) @echo "[FPGA] Generate sources" @@ -750,6 +793,19 @@ fpga: $(ariane_pkg) $(src) $(fpga_src) $(uart_src) $(src_flist) @echo "[FPGA] Generate Bitstream" $(MAKE) -C corev_apu/fpga BOARD=$(BOARD) XILINX_PART=$(XILINX_PART) XILINX_BOARD=$(XILINX_BOARD) CLK_PERIOD_NS=$(CLK_PERIOD_NS) +altera: PLATFORM := "PLAT_AGILEX" + +altera: $(ariane_pkg) $(src) $(fpga_src) $(src_flist) + @echo "[FPGA] Generate sources" + @echo $(ariane_pkg) > corev_apu/altera/sourcelist.txt + @echo $(filter-out $(fpga_filter), $(src_flist)) >> corev_apu/altera/sourcelist.txt + @echo $(filter-out $(fpga_filter) $(altera_filter), $(src)) >> corev_apu/altera/sourcelist.txt + @echo $(filter-out $(altera_filter), $(fpga_src)) >> corev_apu/altera/sourcelist.txt + @echo $(filter-out $(fpga_filter) $(altera_filter) $(uart_src_sv), $(altera_src)) >> corev_apu/altera/sourcelist.txt + @echo $(filter-out $(fpga_filter) $(altera_filter), $(altera_axi_src)) >> corev_apu/altera/sourcelist.txt + @echo "[FPGA] Generate Bitstream" + $(MAKE) -C corev_apu/altera ALTERA_PART=$(ALTERA_PART) ALTERA_BOARD=$(ALTERA_BOARD) CLK_PERIOD_NS=$(CLK_PERIOD_NS) + .PHONY: fpga build-spike: @@ -762,6 +818,9 @@ clean: $(MAKE) -C corev_apu/fpga clean $(MAKE) -C corev_apu/fpga/src/bootrom BOARD=$(BOARD) XLEN=$(XLEN) clean +clean-altera: clean + $(MAKE) -C corev_apu/altera clean + .PHONY: build sim sim-verilate clean \ $(riscv-asm-tests) $(addsuffix _verilator,$(riscv-asm-tests)) \ diff --git a/README.md b/README.md index faf2fc9a77..e54c4d387a 100644 --- a/README.md +++ b/README.md @@ -205,29 +205,67 @@ python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv64a6_imafdc_sv39-p.ya # COREV-APU FPGA Emulation -We currently only provide support for the [Genesys 2 board](https://reference.digilentinc.com/reference/programmable-logic/genesys-2/reference-manual). We provide pre-build bitstream and memory configuration files for the Genesys 2 [here](https://github.com/openhwgroup/cva6/releases). +We currently provide support for the [Genesys 2 board](https://reference.digilentinc.com/reference/programmable-logic/genesys-2/reference-manual) and the [Agilex 7 Development Kit](https://www.intel.la/content/www/xl/es/products/details/fpga/development-kits/agilex/agf014.html). -Tested on Vivado 2018.2. The FPGA currently contains the following peripherals: +- **Genesys 2** + + We provide pre-build bitstream and memory configuration files for the Genesys 2 [here](https://github.com/openhwgroup/cva6/releases). -- DDR3 memory controller -- SPI controller to conncet to an SDCard -- Ethernet controller -- JTAG port (see debugging section below) -- Bootrom containing zero stage bootloader and device tree. + Tested on Vivado 2018.2. The FPGA currently contains the following peripherals: + + - DDR3 memory controller + - SPI controller to conncet to an SDCard + - Ethernet controller + - JTAG port (see debugging section below) + - Bootrom containing zero stage bootloader and device tree. + - UART + - GPIOs connected to LEDs > The ethernet controller and the corresponding network connection is still work in progress and not functional at the moment. Expect some updates soon-ish. +- **Agilex 7** + + Tested on Quartus Prime Version 24.1.0 Pro Edition. The FPGA currently contains the following peripherals: + + - DDR4 memory controller + - JTAG port (see debugging section below) + - Bootrom containing zero stage bootloader + - UART + - GPIOs connected to LEDs + +> The ethernet controller and the corresponding network connection, as well as the SD Card connection and the capability to boot linux are still work in progress and not functional at the moment. Expect some updates soon-ish. + + +## Programming the Memory Configuration File or bitstream + +- **Genesys 2** -## Programming the Memory Configuration File + - Open Vivado + - Open the hardware manager and open the target board (Genesys II - `xc7k325t`) + - Tools - Add Configuration Memory Device + - Select the following Spansion SPI flash `s25fl256xxxxxx0` + - Add `ariane_xilinx.mcs` + - Press Ok. Flashing will take a couple of minutes. + - Right click on the FPGA device - Boot from Configuration Memory Device (or press the program button on the FPGA) -- Open Vivado -- Open the hardware manager and open the target board (Genesys II - `xc7k325t`) -- Tools - Add Configuration Memory Device -- Select the following Spansion SPI flash `s25fl256xxxxxx0` -- Add `ariane_xilinx.mcs` -- Press Ok. Flashing will take a couple of minutes. -- Right click on the FPGA device - Boot from Configuration Memory Device (or press the program button on the FPGA) +- **Agilex 7** + - Open Quartus programmer + - Configure HW Setup by selecting the AGF FPGA Development Kit + - Click Auto-Detect to scan the JTAG chain + - In the device list, right click over device AGFB014R24B and add file (.sof) + - Click on Start button to program the FPGA + - Right now only baremetal is supported, so right after programming you can connect to the UART and see your CVA6 alive on Agilex! + - For this you need to use the JTAG UART provided with Quartus installation + +``` +.$quartus_installation_path/qprogrammer/quartus/bin/juart-terminal +juart-terminal: connected to hardware target using JTAG UART on cable +juart-terminal: "AGF FPGA Development Kit [1-3]", device 1, instance 0 +juart-terminal: (Use the IDE stop button or Ctrl-C to terminate) + +Hello World! +``` ## Preparing the SD Card @@ -245,6 +283,8 @@ After you've inserted the SD Card and programmed the FPGA you can connect to the ## Generating a Bitstream +- **Genesys 2** + To generate the FPGA bitstream (and memory configuration) yourself for the Genesys II board run: ``` @@ -253,9 +293,27 @@ make fpga This will produce a bitstream file and memory configuration file (in `fpga/work-fpga`) which you can permanently flash by running the above commands. +- **Agilex 7** + +To generate the FPGA bitstream yourself for the Agilex 7 board run: + +``` +make altera +``` + +We recommend to set the parameter FpgaAlteraEn (and also FpgaEn) to benefit from the FPGA optimizations. + +This will produce a bitstream file (in `altera/output_files`) which you can program following the previous instructions. **Note: Bear in mind that you need a Quartus Pro Licence to be able to generate this bitstream** + +To clean the project after generating the bitstream, use + +``` +make clean-altera +``` ## Debugging +- **Genesys 2** You can debug (and program) the FPGA using [OpenOCD](http://openocd.org/doc/html/Architecture-and-Core-Commands.html). We provide two example scripts for OpenOCD below. To get started, connect the micro USB port that is labeled with JTAG to your machine. This port is attached to the FTDI 2232 USB-to-serial chip on the Genesys 2 board, and is usually used to access the native JTAG interface of the Kintex-7 FPGA (e.g. to program the device using Vivado). However, the FTDI chip also exposes a second serial link that is routed to GPIO pins on the FPGA, and we leverage this to wire up the JTAG from the RISC-V debug module. @@ -293,6 +351,54 @@ Info : Listening on port 6666 for tcl connections Info : Listening on port 4444 for telnet connections Info : accepting 'gdb' connection on tcp/3333 ``` +- **Agilex 7** + +You can debug (and program) the FPGA using a modified version of OpenOCD included with Quartus installation ($quartus_installation_path/qprogrammer/quartus/bin/openocd). + +To get started, connect the micro USB port that is labeled with J13 to your machine. It is the same port that is used for the UART. Both use the JTAG interface and connect to the System Level Debugging (SLD) Hub instantiated inside the FPGA. Then the debugger connection goes to the virtual JTAG IP (vJTAG) which can be accessed with the modified version of OpenOCD. + +You can start openocd with the `altera/cva6.cfg` configuration file: + +``` +./$quartus_installation_path/qprogrammer/quartus/bin/openocd -f altera/cva6.cfg +Open On-Chip Debugger 0.11.0-R22.4 +Licensed under GNU GPL v2 +For bug reports, read + http://openocd.org/doc/doxygen/bugs.html +Info : only one transport option; autoselect 'jtag' +Info : Application name is OpenOCD.20241016093010 +Info : No cable specified, so will be searching for cables + +Info : At present, The first hardware cable will be used [1 cable(s) detected] +Info : Cable 1: device_name=(null), hw_name=AGF FPGA Development Kit, server=(null), port=1-3, chain_id=0x559319c8cde0, persistent_id=1, chain_type=1, features=34816, server_version_info=Version 24.1.0 Build 115 03/21/2024 SC Pro Edition +Info : TAP position 0 (C341A0DD) has 3 SLD nodes +Info : node 0 idcode=00406E00 position_n=0 +Info : node 1 idcode=30006E00 position_n=0 +Info : node 2 idcode=0C006E00 position_n=0 +Info : TAP position 1 (20D10DD) has 1 SLD nodes +Info : node 0 idcode=0C206E00 position_n=0 +Info : Discovered 2 TAP devices +Info : Detected device (tap_position=0) device_id=c341a0dd, instruction_length=10, features=12, device_name=AGFB014R24A(.|R1|R2)/.. +Info : Found an Intel device at tap_position 0.Currently assuming it is SLD Hub +Info : Detected device (tap_position=1) device_id=020d10dd, instruction_length=10, features=4, device_name=VTAP10 +Info : Found an Intel device at tap_position 1.Currently assuming it is SLD Hub +Info : This adapter doesn't support configurable speed +Info : JTAG tap: agilex7.fpga.tap tap/device found: 0xc341a0dd (mfg: 0x06e (Altera), part: 0x341a, ver: 0xc) +Info : JTAG tap: auto0.tap tap/device found: 0x020d10dd (mfg: 0x06e (Altera), part: 0x20d1, ver: 0x0) +Info : JTAG tap: agilex7.fpga.tap Parent Tap found: 0xc341a0dd (mfg: 0x06e (Altera), part: 0x341a, ver: 0xc) +Info : Virtual Tap/SLD node 0x00406E00 found at tap position 0 vtap position 0 +Warn : AUTO auto0.tap - use "jtag newtap auto0 tap -irlen 10 -expected-id 0x020d10dd" +Info : datacount=2 progbufsize=8 +Info : Examined RISC-V core; found 1 harts +Info : hart 0: XLEN=32, misa=0x40141107 +Info : starting gdb server for agilex7.cva6.0 on 3333 +Info : Listening on port 3333 for gdb connections +Ready for Remote Connections +Info : Listening on port 6666 for tcl connections +Info : Listening on port 4444 for telnet connections +``` + +- **Common for both boards** Then you will be able to either connect through `telnet` or with `gdb`: diff --git a/RESOURCES.md b/RESOURCES.md index 2f44b631d8..659c7c48c9 100644 --- a/RESOURCES.md +++ b/RESOURCES.md @@ -11,59 +11,94 @@ Please help improve this page, by filing an [issue](https://github.com/openhwgro > [!WARNING] > The CVA6 team is not liable for the other repositories. -> Assess their content and make sure they fit your needs and are mature enough for design. +> Assess their content and make sure they fit your needs and are mature enough for your design. > Plese direct your issues or pull requests to these external repositories. ## Our legacy -CVA6 was designed by the [PULP Platform team](https://www.pulp-platform.org/). You can integrate it with many other PULP designs from [github.com/pulp-platform](https://github.com/pulp-platform). +CVA6 was designed by the **[PULP Platform team](https://www.pulp-platform.org/)**. You can integrate it with many other PULP designs from [github.com/pulp-platform](https://github.com/pulp-platform). ## Technical resources ### SW Tools and OSes -RISC-V tools for CVA6 and Buildroot Linux support are available [here](https://github.com/openhwgroup/cva6-sdk). +**RISC-V tools** for CVA6 and **Buildroot Linux** support are available [here](https://github.com/openhwgroup/cva6-sdk). -Yocto Linux support for CVA6 is available [here](https://github.com/openhwgroup/meta-cva6-yocto). +**Yocto Linux** support for CVA6 is available [here](https://github.com/openhwgroup/meta-cva6-yocto). -FreeRTOS support for CVA6 is available [here](https://github.com/FreeRTOS/FreeRTOS-Partner-Supported-Demos/tree/main/RISC-V_cva6). +**FreeRTOS** support for CVA6 is available [here](https://github.com/FreeRTOS/FreeRTOS-Partner-Supported-Demos/tree/main/RISC-V_cva6). -Zephyr support for CV64A6 will soon be available. +**Zephyr** support for CV64A6 will soon be available. -This [tutorial](https://github.com/ThalesGroup/cva6-eclipse-demo) offers resources to debug CVA6 under Eclipse IDE. +**Bao** ([repository](https://github.com/bao-project/bao-hypervisor), [documentation](https://github.com/bao-project/bao-docs)) is an embedded hypervisor targetting strong isolation and real-time guarantees, leveraging CV64A6 optional hypervisor support. -The OS ports below are on Digilent Genesys 2 board. +**seL4**, secure, formally verified microkernel supports CVA6 (still by its old ARIANE name) [here](https://docs.sel4.systems/Hardware/ariane.html). + +This [tutorial](https://github.com/ThalesGroup/cva6-eclipse-demo) offers resources to debug CVA6 under **Eclipse IDE**. + +The OS ports above are usually on Digilent Genesys 2 board. ### Related building blocks These building blocks fit very nicely with CVA6: -- [OpenPiton](https://github.com/PrincetonUniversity/openpiton) is a many-core framework that supports CVA6. -- [Culsans/CV-TCCC](https://github.com/pulp-platform/culsans) is a multi-core infrastructure for a few CVA6 cores. -- [ARA/CV-VEC](https://github.com/pulp-platform/ara) is a vector unit for CVA6. -- [HPDcache](https://github.com/openhwgroup/cv-hpdcache) is a flexible (highly configurable) and high-throughput L1 cache. +**[OpenPiton](https://github.com/PrincetonUniversity/openpiton)** is a many-core framework that supports CVA6. + +**[Culsans/CV-TCCC](https://github.com/pulp-platform/culsans)** is a multi-core infrastructure for a few CVA6 cores. + +**[ARA/CV-VEC](https://github.com/pulp-platform/ara)** is a vector unit for CVA6. + +**[HPDcache](https://github.com/openhwgroup/cv-hpdcache)** is a flexible (highly configurable) and high-throughput L1 cache. + +**[IOMMU](https://github.com/zero-day-labs/riscv-iommu)** supports the RISC-V Input/Output Memory Management Unit (IOMMU) Specification, including the hypervisor privilege. + +**[IOPMP](https://github.com/zero-day-labs/riscv-iopmp)** supports the RISC-V Input/Output Physical Memory Protection (IOPMP) Specification. + +**[AIA](https://github.com/zero-day-labs/riscv-aia)** supports the RISC-V Advanced Interrupt Architecture (AIA) specification. ### Design examples (FPGA) The CVA6 repository contains the CVA6 core and a basic CPU design, the "APU" and its implementation on a Digilent Genesys 2 FPGA board. Here is a list of other CVA6-based FPGA designs: -The [technical kits](https://github.com/thalesgroup/cva6-softcore-contest) of a student contest organized in France can be used as educational resources or as an easy way to get CVA6 up and running with a cheaper Digilent Zybo Z7-20 board. You will find in it: +The [technical kits](https://github.com/thalesgroup/cva6-softcore-contest) of a **student contest** organized in France can be used as educational resources or as an easy way to get CVA6 up and running with a cheaper Digilent Zybo Z7-20 board. You will find in it: - The 2020-2021 contest, focusing on PPA optimization; - The 2021-2022 contest, focusing on energy optimization; - The 2022-2023 contest, focusing on cybersecurity, including a port of Zephyr OS; - The 2023-2024 contest, focusing on the acceleration of the MNIST digit recognition with custom extensions; -- The 2024-2025 contest, focusing on the frequency increase (_not released yet_); +- The 2024-2025 contest, focusing on the frequency increase; - A treat with the support of Linux and a VGA output. -[CVA6 with Xilinx Ethernet](https://github.com/cispa/CVA6-Vivado-Project-with-Xilinx-AXI-Ethernet/) is an alternative design which implements Xilinx 1G/2.5G Ethernet Subsystem on the Digilent Genesys 2 FPGA board. It has been tested with TFTP boot in u-boot and SSH in Linux. +**[CVA6 with Xilinx Ethernet](https://github.com/cispa/CVA6-Vivado-Project-with-Xilinx-AXI-Ethernet/)** is an alternative design which implements Xilinx 1G/2.5G Ethernet Subsystem on the Digilent Genesys 2 FPGA board. It has been tested with TFTP boot in u-boot and SSH in Linux. + +### Platforms, subsystems and systems + +These are large subsystems and systems that are more complex than the "APU". They can be a starting point for your design: + +**Cheshire** ([repository](https://github.com/pulp-platform/cheshire), [documentation](https://pulp-platform.github.io/cheshire/)) +is a light-weight, open-source (including peripherals), linux-capable RISC-V system built around CVA6. +It can be integrated as Linux-capable host in larger, heterogeneous systems. + +**Carfield** ([repository](https://github.com/pulp-platform/carfield), [documentation](https://pulp-platform.github.io/carfield/)) +is a mixed-criticality platform targeting automotive applications with several safety, security, +and predictability features built around Cheshire and CVA6. + +**AlSaqr** ([repository](https://github.com/AlSaqr-platform/he-soc/tree/master)) +is as secure system for Nano-UAV navigation based on CVA6 and Culsans. + +### Designs (ASIC) and chiplets -### Designs (ASIC) +Here are open-source ASIC designs based on CVA6, that have been prototyped on silicon: -Here are open-source ASIC designs based on CVA6: +**[Polara APU](https://github.com/openhwgroup/core-v-polara-apu)** +is a 4-core processor made with OpenPiton, ARA and CVA6. -[Polara APU](https://github.com/openhwgroup/core-v-polara-apu) is a 4-core processor made with OpenPiton, ARA and CVA6. +**[Basilisk](https://github.com/pulp-platform/cheshire-ihp130-o)** +is an end-to-end open-source, Linux-capable chip based on Cheshire, CVA6, Yosys and OpenRoad. -To be completed +**Occamy** ([repository](https://github.com/pulp-platform/occamy), +[article](https://pulp-platform.org/occamy/), +[paper](https://doi.org/10.1109/VLSITechnologyandCir46783.2024.10631529)) +is a 432-core, 2.5D chiplet RISC-V system with CVA6 as manager core. ## Business resources @@ -88,7 +123,7 @@ and verification efforts within the OpenHW ecosystem. Our work on CVA6 includes and implementation of multiple RISC-V extensions, such as Bitmanip, Zicond, Zcb, and Zcmp. Our expert team assists companies in integrating, customizing, and optimizing CVA6 to meet their unique requirements. - _(To be completed based on companies's requests. Max 1 URL and 60 words per company)_ + _(To be completed based on companies's requests. Max 1 URL and 70 words per company)_ ### Product ICs diff --git a/config/gen_from_riscv_config/cv32a65x/spike/spike.yaml b/config/gen_from_riscv_config/cv32a65x/spike/spike.yaml index 521e53e734..540b68e5ee 100644 --- a/config/gen_from_riscv_config/cv32a65x/spike/spike.yaml +++ b/config/gen_from_riscv_config/cv32a65x/spike/spike.yaml @@ -52,6 +52,7 @@ spike_param_tree: pmpaddr5_write_mask: 0xFFFFFFFE pmpaddr6_write_mask: 0xFFFFFFFE pmpaddr7_write_mask: 0xFFFFFFFE + mtvec_write_mask: 0xFFFFFFFE mhartid: 0 mvendorid_override_mask : 0xFFFFFFFF mvendorid_override_value: 1538 diff --git a/core/Flist.cva6 b/core/Flist.cva6 index cac849e2b7..966238e3e0 100644 --- a/core/Flist.cva6 +++ b/core/Flist.cva6 @@ -29,6 +29,8 @@ ${CVA6_REPO_DIR}/vendor/pulp-platform/fpga-support/rtl/SyncDpRam.sv ${CVA6_REPO_DIR}/vendor/pulp-platform/fpga-support/rtl/AsyncDpRam.sv ${CVA6_REPO_DIR}/vendor/pulp-platform/fpga-support/rtl/AsyncThreePortRam.sv +${CVA6_REPO_DIR}/vendor/pulp-platform/fpga-support/rtl/SyncThreePortRam.sv +${CVA6_REPO_DIR}/vendor/pulp-platform/fpga-support/rtl/SyncDpRam_ind_r_w.sv +incdir+${CVA6_REPO_DIR}/core/include/ +incdir+${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/include/ diff --git a/core/branch_unit.sv b/core/branch_unit.sv index 0688836639..074eb502fb 100644 --- a/core/branch_unit.sv +++ b/core/branch_unit.sv @@ -58,7 +58,6 @@ module branch_unit #( // TODO(zarubaf): The ALU can be used to calculate the branch target jump_base = (fu_data_i.operation == ariane_pkg::JALR) ? fu_data_i.operand_a[CVA6Cfg.VLEN-1:0] : pc_i; - target_address = {CVA6Cfg.VLEN{1'b0}}; resolve_branch_o = 1'b0; resolved_branch_o.target_address = {CVA6Cfg.VLEN{1'b0}}; resolved_branch_o.is_taken = 1'b0; diff --git a/core/cache_subsystem/cva6_hpdcache_if_adapter.sv b/core/cache_subsystem/cva6_hpdcache_if_adapter.sv index eb6f217ec8..d9e9f23316 100644 --- a/core/cache_subsystem/cva6_hpdcache_if_adapter.sv +++ b/core/cache_subsystem/cva6_hpdcache_if_adapter.sv @@ -22,7 +22,8 @@ module cva6_hpdcache_if_adapter parameter type hpdcache_rsp_t = logic, parameter type dcache_req_i_t = logic, parameter type dcache_req_o_t = logic, - parameter bit is_load_port = 1'b1 + parameter bit InvalidateOnFlush = 1'b0, + parameter bit IsLoadPort = 1'b1 ) // }}} @@ -42,6 +43,10 @@ module cva6_hpdcache_if_adapter input ariane_pkg::amo_req_t cva6_amo_req_i, output ariane_pkg::amo_resp_t cva6_amo_resp_o, + // Dcache flush signal + input logic cva6_dcache_flush_i, + output logic cva6_dcache_flush_ack_o, + // Request port to the L1 Dcache output logic hpdcache_req_valid_o, input logic hpdcache_req_ready_i, @@ -58,8 +63,13 @@ module cva6_hpdcache_if_adapter // Internal nets and registers // {{{ - logic forward_store, forward_amo; + typedef enum { + FLUSH_IDLE, + FLUSH_PEND + } flush_fsm_t; + logic hpdcache_req_is_uncacheable; + hpdcache_req_t hpdcache_req; // }}} // Request forwarding @@ -67,7 +77,7 @@ module cva6_hpdcache_if_adapter generate // LOAD request // {{{ - if (is_load_port == 1'b1) begin : load_port_gen + if (IsLoadPort == 1'b1) begin : load_port_gen assign hpdcache_req_is_uncacheable = !config_pkg::is_inside_cacheable_regions( CVA6Cfg, { @@ -79,19 +89,19 @@ module cva6_hpdcache_if_adapter // Request forwarding assign hpdcache_req_valid_o = cva6_req_i.data_req; - assign hpdcache_req_o.addr_offset = cva6_req_i.address_index; - assign hpdcache_req_o.wdata = '0; - assign hpdcache_req_o.op = hpdcache_pkg::HPDCACHE_REQ_LOAD; - assign hpdcache_req_o.be = cva6_req_i.data_be; - assign hpdcache_req_o.size = cva6_req_i.data_size; - assign hpdcache_req_o.sid = hpdcache_req_sid_i; - assign hpdcache_req_o.tid = cva6_req_i.data_id; - assign hpdcache_req_o.need_rsp = 1'b1; - assign hpdcache_req_o.phys_indexed = 1'b0; - assign hpdcache_req_o.addr_tag = '0; // unused on virtually indexed request - assign hpdcache_req_o.pma.uncacheable = 1'b0; - assign hpdcache_req_o.pma.io = 1'b0; - assign hpdcache_req_o.pma.wr_policy_hint = hpdcache_pkg::HPDCACHE_WR_POLICY_AUTO; + assign hpdcache_req.addr_offset = cva6_req_i.address_index; + assign hpdcache_req.wdata = '0; + assign hpdcache_req.op = hpdcache_pkg::HPDCACHE_REQ_LOAD; + assign hpdcache_req.be = cva6_req_i.data_be; + assign hpdcache_req.size = cva6_req_i.data_size; + assign hpdcache_req.sid = hpdcache_req_sid_i; + assign hpdcache_req.tid = cva6_req_i.data_id; + assign hpdcache_req.need_rsp = 1'b1; + assign hpdcache_req.phys_indexed = 1'b0; + assign hpdcache_req.addr_tag = '0; // unused on virtually indexed request + assign hpdcache_req.pma.uncacheable = 1'b0; + assign hpdcache_req.pma.io = 1'b0; + assign hpdcache_req.pma.wr_policy_hint = hpdcache_pkg::HPDCACHE_WR_POLICY_AUTO; assign hpdcache_req_abort_o = cva6_req_i.kill_req; assign hpdcache_req_tag_o = cva6_req_i.address_tag; @@ -104,6 +114,15 @@ module cva6_hpdcache_if_adapter assign cva6_req_o.data_rdata = hpdcache_rsp_i.rdata; assign cva6_req_o.data_rid = hpdcache_rsp_i.tid; assign cva6_req_o.data_gnt = hpdcache_req_ready_i; + + // Assertions + // {{{ + // pragma translate_off + flush_on_load_port_assert : + assert property (@(posedge clk_i) disable iff (rst_ni !== 1'b1) (cva6_dcache_flush_i == 1'b0)) + else $error("Flush unsupported on load adapters"); + // pragma translate_on + // }}} end // }}} // {{{ @@ -119,6 +138,53 @@ module cva6_hpdcache_if_adapter logic [31:0] amo_resp_word; logic amo_pending_q; + hpdcache_req_t hpdcache_req_amo; + hpdcache_req_t hpdcache_req_store; + hpdcache_req_t hpdcache_req_flush; + + flush_fsm_t flush_fsm_q, flush_fsm_d; + + logic forward_store, forward_amo, forward_flush; + + // DCACHE flush request + // {{{ + always_ff @(posedge clk_i or negedge rst_ni) begin : flush_ff + if (!rst_ni) begin + flush_fsm_q <= FLUSH_IDLE; + end else begin + flush_fsm_q <= flush_fsm_d; + end + end + + always_comb begin : flush_comb + forward_flush = 1'b0; + cva6_dcache_flush_ack_o = 1'b0; + + flush_fsm_d = flush_fsm_q; + + case (flush_fsm_q) + FLUSH_IDLE: begin + if (cva6_dcache_flush_i) begin + forward_flush = 1'b1; + if (hpdcache_req_ready_i) begin + flush_fsm_d = FLUSH_PEND; + end + end + end + FLUSH_PEND: begin + if (hpdcache_rsp_valid_i) begin + if (hpdcache_rsp_i.tid == '0) begin + cva6_dcache_flush_ack_o = 1'b1; + flush_fsm_d = FLUSH_IDLE; + end + end + end + default: begin + end + endcase + end + // }}} + // AMO logic // {{{ always_comb begin : amo_op_comb @@ -148,7 +214,7 @@ module cva6_hpdcache_if_adapter CVA6Cfg, { {64 - CVA6Cfg.DCACHE_TAG_WIDTH{1'b0}} - , hpdcache_req_o.addr_tag, + , hpdcache_req.addr_tag, {CVA6Cfg.DCACHE_INDEX_WIDTH{1'b0}} } ); @@ -163,23 +229,73 @@ module cva6_hpdcache_if_adapter assign amo_data_be = 8'h0f; end + assign hpdcache_req_amo = '{ + addr_offset: amo_addr_offset, + wdata: amo_data, + op: amo_op, + be: amo_data_be, + size: cva6_amo_req_i.size, + sid: hpdcache_req_sid_i, + tid: '1, + need_rsp: 1'b1, + phys_indexed: 1'b1, + addr_tag: amo_tag, + pma: '{ + uncacheable: hpdcache_req_is_uncacheable, + io: 1'b0, + wr_policy_hint: hpdcache_pkg::HPDCACHE_WR_POLICY_AUTO + } + }; + + assign hpdcache_req_store = '{ + addr_offset: cva6_req_i.address_index, + wdata: cva6_req_i.data_wdata, + op: hpdcache_pkg::HPDCACHE_REQ_STORE, + be: cva6_req_i.data_be, + size: cva6_req_i.data_size, + sid: hpdcache_req_sid_i, + tid: '0, + need_rsp: 1'b0, + phys_indexed: 1'b1, + addr_tag: cva6_req_i.address_tag, + pma: '{ + uncacheable: hpdcache_req_is_uncacheable, + io: 1'b0, + wr_policy_hint: hpdcache_pkg::HPDCACHE_WR_POLICY_AUTO + } + }; + + assign hpdcache_req_flush = '{ + addr_offset: '0, + addr_tag: '0, + wdata: '0, + op: + InvalidateOnFlush + ? + hpdcache_pkg::HPDCACHE_REQ_CMO_FLUSH_INVAL_ALL + : + hpdcache_pkg::HPDCACHE_REQ_CMO_FLUSH_ALL, + be: '0, + size: '0, + sid: hpdcache_req_sid_i, + tid: '0, + need_rsp: 1'b1, + phys_indexed: 1'b0, + pma: '{ + uncacheable: 1'b0, + io: 1'b0, + wr_policy_hint: hpdcache_pkg::HPDCACHE_WR_POLICY_AUTO + } + }; + assign forward_store = cva6_req_i.data_req; assign forward_amo = cva6_amo_req_i.req; - assign hpdcache_req_valid_o = forward_store | (forward_amo & ~amo_pending_q); - assign hpdcache_req_o.addr_offset = forward_amo ? amo_addr_offset : cva6_req_i.address_index; - assign hpdcache_req_o.wdata = forward_amo ? amo_data : cva6_req_i.data_wdata; - assign hpdcache_req_o.op = forward_amo ? amo_op : hpdcache_pkg::HPDCACHE_REQ_STORE; - assign hpdcache_req_o.be = forward_amo ? amo_data_be : cva6_req_i.data_be; - assign hpdcache_req_o.size = forward_amo ? cva6_amo_req_i.size : cva6_req_i.data_size; - assign hpdcache_req_o.sid = hpdcache_req_sid_i; - assign hpdcache_req_o.tid = forward_amo ? '1 : '0; - assign hpdcache_req_o.need_rsp = forward_amo; - assign hpdcache_req_o.phys_indexed = 1'b1; - assign hpdcache_req_o.addr_tag = forward_amo ? amo_tag : cva6_req_i.address_tag; - assign hpdcache_req_o.pma.uncacheable = hpdcache_req_is_uncacheable; - assign hpdcache_req_o.pma.io = 1'b0; - assign hpdcache_req_o.pma.wr_policy_hint = hpdcache_pkg::HPDCACHE_WR_POLICY_AUTO; + assign hpdcache_req_valid_o = (forward_amo & ~amo_pending_q) | forward_store | forward_flush; + + assign hpdcache_req = forward_amo ? hpdcache_req_amo : + forward_store ? hpdcache_req_store : hpdcache_req_flush; + assign hpdcache_req_abort_o = 1'b0; // unused on physically indexed requests assign hpdcache_req_tag_o = '0; // unused on physically indexed requests assign hpdcache_req_pma_o.uncacheable = 1'b0; @@ -216,17 +332,21 @@ module cva6_hpdcache_if_adapter (~cva6_amo_resp_o.ack & amo_pending_q); end end + + // Assertions + // {{{ + // pragma translate_off + forward_one_request_assert : + assert property (@(posedge clk_i) disable iff (rst_ni !== 1'b1) ($onehot0( + {forward_store, forward_amo, forward_flush} + ))) + else $error("Only one request shall be forwarded"); + // pragma translate_on + // }}} end // }}} endgenerate - // }}} - // Assertions - // {{{ - // pragma translate_off - forward_one_request_assert : - assert property (@(posedge clk_i) ($onehot0({forward_store, forward_amo}))) - else $error("Only one request shall be forwarded"); - // pragma translate_on + assign hpdcache_req_o = hpdcache_req; // }}} endmodule diff --git a/core/cache_subsystem/cva6_hpdcache_subsystem.sv b/core/cache_subsystem/cva6_hpdcache_subsystem.sv index 9cc5234385..6d13f6517c 100644 --- a/core/cache_subsystem/cva6_hpdcache_subsystem.sv +++ b/core/cache_subsystem/cva6_hpdcache_subsystem.sv @@ -189,43 +189,52 @@ module cva6_hpdcache_subsystem // NumPorts + 1: Hardware Memory Prefetcher (hwpf) localparam int HPDCACHE_NREQUESTERS = NumPorts + 2; - localparam hpdcache_pkg::hpdcache_user_cfg_t HPDcacheUserCfg = '{ - nRequesters: HPDCACHE_NREQUESTERS, - paWidth: CVA6Cfg.PLEN, - wordWidth: CVA6Cfg.XLEN, - sets: CVA6Cfg.DCACHE_NUM_WORDS, - ways: CVA6Cfg.DCACHE_SET_ASSOC, - clWords: CVA6Cfg.DCACHE_LINE_WIDTH / CVA6Cfg.XLEN, - reqWords: 1, - reqTransIdWidth: CVA6Cfg.DcacheIdWidth, - reqSrcIdWidth: 3, // Up to 8 requesters - victimSel: hpdcache_pkg::HPDCACHE_VICTIM_RANDOM, - dataWaysPerRamWord: __minu(CVA6Cfg.DCACHE_SET_ASSOC, 128 / CVA6Cfg.XLEN), - dataSetsPerRam: CVA6Cfg.DCACHE_NUM_WORDS, - dataRamByteEnable: 1'b1, - accessWords: __maxu(CVA6Cfg.DCACHE_LINE_WIDTH / (2 * CVA6Cfg.XLEN), 1), - mshrSets: CVA6Cfg.NrLoadBufEntries < 16 ? 1 : CVA6Cfg.NrLoadBufEntries / 2, - mshrWays: CVA6Cfg.NrLoadBufEntries < 16 ? CVA6Cfg.NrLoadBufEntries : 2, - mshrWaysPerRamWord: CVA6Cfg.NrLoadBufEntries < 16 ? CVA6Cfg.NrLoadBufEntries : 2, - mshrSetsPerRam: CVA6Cfg.NrLoadBufEntries < 16 ? 1 : CVA6Cfg.NrLoadBufEntries / 2, - mshrRamByteEnable: 1'b1, - mshrUseRegbank: (CVA6Cfg.NrLoadBufEntries < 16), - refillCoreRspFeedthrough: 1'b1, - refillFifoDepth: 2, - wbufDirEntries: CVA6Cfg.WtDcacheWbufDepth, - wbufDataEntries: CVA6Cfg.WtDcacheWbufDepth, - wbufWords: 1, - wbufTimecntWidth: 3, - rtabEntries: 4, - flushEntries: 0, - flushFifoDepth: 0, - memAddrWidth: CVA6Cfg.AxiAddrWidth, - memIdWidth: CVA6Cfg.MEM_TID_WIDTH, - memDataWidth: CVA6Cfg.AxiDataWidth, - wtEn: 1'b1, - wbEn: 1'b0 - }; + function automatic hpdcache_pkg::hpdcache_user_cfg_t hpdcacheSetConfig(); + hpdcache_pkg::hpdcache_user_cfg_t userCfg; + userCfg.nRequesters = HPDCACHE_NREQUESTERS; + userCfg.paWidth = CVA6Cfg.PLEN; + userCfg.wordWidth = CVA6Cfg.XLEN; + userCfg.sets = CVA6Cfg.DCACHE_NUM_WORDS; + userCfg.ways = CVA6Cfg.DCACHE_SET_ASSOC; + userCfg.clWords = CVA6Cfg.DCACHE_LINE_WIDTH / CVA6Cfg.XLEN; + userCfg.reqWords = 1; + userCfg.reqTransIdWidth = CVA6Cfg.DcacheIdWidth; + userCfg.reqSrcIdWidth = 3; // Up to 8 requesters + userCfg.victimSel = hpdcache_pkg::HPDCACHE_VICTIM_RANDOM; + userCfg.dataWaysPerRamWord = __minu(CVA6Cfg.DCACHE_SET_ASSOC, 128 / CVA6Cfg.XLEN); + userCfg.dataSetsPerRam = CVA6Cfg.DCACHE_NUM_WORDS; + userCfg.dataRamByteEnable = 1'b1; + userCfg.accessWords = __maxu(CVA6Cfg.AxiDataWidth / CVA6Cfg.XLEN, 1 /*reqWords*/); + userCfg.mshrSets = CVA6Cfg.NrLoadBufEntries < 16 ? 1 : CVA6Cfg.NrLoadBufEntries / 2; + userCfg.mshrWays = CVA6Cfg.NrLoadBufEntries < 16 ? CVA6Cfg.NrLoadBufEntries : 2; + userCfg.mshrWaysPerRamWord = CVA6Cfg.NrLoadBufEntries < 16 ? CVA6Cfg.NrLoadBufEntries : 2; + userCfg.mshrSetsPerRam = CVA6Cfg.NrLoadBufEntries < 16 ? 1 : CVA6Cfg.NrLoadBufEntries / 2; + userCfg.mshrRamByteEnable = 1'b1; + userCfg.mshrUseRegbank = (CVA6Cfg.NrLoadBufEntries < 16); + userCfg.refillCoreRspFeedthrough = 1'b1; + userCfg.refillFifoDepth = 2; + userCfg.wbufDirEntries = CVA6Cfg.WtDcacheWbufDepth; + userCfg.wbufDataEntries = CVA6Cfg.WtDcacheWbufDepth; + userCfg.wbufWords = 1; + userCfg.wbufTimecntWidth = 3; + userCfg.rtabEntries = 4; + /*FIXME we should add additional CVA6 config parameters (flushEntries)*/ + userCfg.flushEntries = CVA6Cfg.WtDcacheWbufDepth; + /*FIXME we should add additional CVA6 config parameters (flushFifoDepth)*/ + userCfg.flushFifoDepth = CVA6Cfg.WtDcacheWbufDepth; + userCfg.memAddrWidth = CVA6Cfg.AxiAddrWidth; + userCfg.memIdWidth = CVA6Cfg.MEM_TID_WIDTH; + userCfg.memDataWidth = CVA6Cfg.AxiDataWidth; + userCfg.wtEn = + (CVA6Cfg.DCacheType == config_pkg::HPDCACHE_WT) || + (CVA6Cfg.DCacheType == config_pkg::HPDCACHE_WT_WB); + userCfg.wbEn = + (CVA6Cfg.DCacheType == config_pkg::HPDCACHE_WB) || + (CVA6Cfg.DCacheType == config_pkg::HPDCACHE_WT_WB); + return userCfg; + endfunction + localparam hpdcache_pkg::hpdcache_user_cfg_t HPDcacheUserCfg = hpdcacheSetConfig(); localparam hpdcache_pkg::hpdcache_cfg_t HPDcacheCfg = hpdcache_pkg::hpdcacheBuildConfig( HPDcacheUserCfg ); @@ -407,7 +416,7 @@ module cva6_hpdcache_subsystem // {{{ // pragma translate_off initial begin : initial_assertions - assert (HPDcacheCfg.u.reqSrcIdWidth >= $clog2(HPDCACHE_NREQUESTERS)) + assert (HPDcacheCfg.u.reqSrcIdWidth >= $clog2(HPDcacheCfg.u.nRequesters)) else $fatal(1, "HPDCACHE_REQ_SRC_ID_WIDTH is not wide enough"); assert (CVA6Cfg.MEM_TID_WIDTH <= CVA6Cfg.AxiIdWidth) else $fatal(1, "MEM_TID_WIDTH shall be less or equal to the AxiIdWidth"); diff --git a/core/cache_subsystem/cva6_hpdcache_wrapper.sv b/core/cache_subsystem/cva6_hpdcache_wrapper.sv index daa084bbcc..7727dc703d 100644 --- a/core/cache_subsystem/cva6_hpdcache_wrapper.sv +++ b/core/cache_subsystem/cva6_hpdcache_wrapper.sv @@ -155,7 +155,8 @@ module cva6_hpdcache_wrapper .hpdcache_rsp_t (hpdcache_rsp_t), .dcache_req_i_t (dcache_req_i_t), .dcache_req_o_t (dcache_req_o_t), - .is_load_port (1'b1) + .InvalidateOnFlush (1'b0), + .IsLoadPort (1'b1) ) i_cva6_hpdcache_load_if_adapter ( .clk_i, .rst_ni, @@ -167,6 +168,9 @@ module cva6_hpdcache_wrapper .cva6_amo_req_i ('0), .cva6_amo_resp_o( /* unused */), + .cva6_dcache_flush_i (1'b0), + .cva6_dcache_flush_ack_o( /* unused */), + .hpdcache_req_valid_o(dcache_req_valid[r]), .hpdcache_req_ready_i(dcache_req_ready[r]), .hpdcache_req_o (dcache_req[r]), @@ -189,7 +193,8 @@ module cva6_hpdcache_wrapper .hpdcache_rsp_t (hpdcache_rsp_t), .dcache_req_i_t (dcache_req_i_t), .dcache_req_o_t (dcache_req_o_t), - .is_load_port (1'b0) + .InvalidateOnFlush (CVA6Cfg.DcacheInvalidateOnFlush), + .IsLoadPort (1'b0) ) i_cva6_hpdcache_store_if_adapter ( .clk_i, .rst_ni, @@ -201,6 +206,9 @@ module cva6_hpdcache_wrapper .cva6_amo_req_i (dcache_amo_req_i), .cva6_amo_resp_o(dcache_amo_resp_o), + .cva6_dcache_flush_i (dcache_flush_i), + .cva6_dcache_flush_ack_o(dcache_flush_ack_o), + .hpdcache_req_valid_o(dcache_req_valid[NumPorts-1]), .hpdcache_req_ready_i(dcache_req_ready[NumPorts-1]), .hpdcache_req_o (dcache_req[NumPorts-1]), @@ -413,12 +421,6 @@ module cva6_hpdcache_wrapper ); assign dcache_miss_o = dcache_read_miss, wbuffer_not_ni_o = wbuffer_empty_o; - - always_ff @(posedge clk_i or negedge rst_ni) begin : dcache_flush_ff - if (!rst_ni) dcache_flush_ack_o <= 1'b0; - else dcache_flush_ack_o <= ~dcache_flush_ack_o & dcache_flush_i; - end - // }}} endmodule : cva6_hpdcache_wrapper diff --git a/core/cache_subsystem/hpdcache b/core/cache_subsystem/hpdcache index edd501cc74..04de808969 160000 --- a/core/cache_subsystem/hpdcache +++ b/core/cache_subsystem/hpdcache @@ -1 +1 @@ -Subproject commit edd501cc7424ad63d2187feacadc942650ec14af +Subproject commit 04de80896981527c34fbbd35d7b1ef787a082d7c diff --git a/core/cache_subsystem/wt_axi_adapter.sv b/core/cache_subsystem/wt_axi_adapter.sv index 9408fb8802..22cc5c075c 100644 --- a/core/cache_subsystem/wt_axi_adapter.sv +++ b/core/cache_subsystem/wt_axi_adapter.sv @@ -142,7 +142,7 @@ module wt_axi_adapter axi_wr_data[0] = {(CVA6Cfg.AxiDataWidth/CVA6Cfg.XLEN){dcache_data.data}}; axi_wr_user[0] = dcache_data.user; // Cast to AXI address width - axi_wr_addr = {{CVA6Cfg.AxiAddrWidth-CVA6Cfg.PLEN{1'b0}}, dcache_data.paddr}; + axi_wr_addr = CVA6Cfg.AxiAddrWidth'(dcache_data.paddr); axi_wr_size = dcache_data.size; axi_wr_req = 1'b0; axi_wr_blen = '0;// single word writes @@ -167,7 +167,7 @@ module wt_axi_adapter // arbiter mux if (arb_idx) begin // Cast to AXI address width - axi_rd_addr = {{CVA6Cfg.AxiAddrWidth - CVA6Cfg.PLEN{1'b0}}, dcache_data.paddr}; + axi_rd_addr = CVA6Cfg.AxiAddrWidth'(dcache_data.paddr); // If dcache_data.size MSB is set, we want to read as much as possible axi_rd_size = dcache_data.size[2] ? MaxNumWords[2:0] : dcache_data.size; if (dcache_data.size[2]) begin @@ -175,10 +175,10 @@ module wt_axi_adapter end end else begin // Cast to AXI address width - axi_rd_addr = {{CVA6Cfg.AxiAddrWidth - CVA6Cfg.PLEN{1'b0}}, icache_data.paddr}; + axi_rd_addr = CVA6Cfg.AxiAddrWidth'(icache_data.paddr); axi_rd_size = MaxNumWords[2:0]; // always request max number of words in case of ifill if (!icache_data.nc) begin - axi_rd_blen = AxiRdBlenDcache[AxiBlenWidth-1:0]; + axi_rd_blen = AxiRdBlenIcache[AxiBlenWidth-1:0]; end end diff --git a/core/cache_subsystem/wt_dcache_wbuffer.sv b/core/cache_subsystem/wt_dcache_wbuffer.sv index be2029952c..ef3a62ef33 100644 --- a/core/cache_subsystem/wt_dcache_wbuffer.sv +++ b/core/cache_subsystem/wt_dcache_wbuffer.sv @@ -594,8 +594,6 @@ module wt_dcache_wbuffer wbuffer_d[wr_ptr].data[k*8+:8] = req_port_i.data_wdata[k*8+:8]; if (CVA6Cfg.DATA_USER_EN) begin wbuffer_d[wr_ptr].user[k*8+:8] = req_port_i.data_wuser[k*8+:8]; - end else begin - wbuffer_d[wr_ptr].user[k*8+:8] = '0; end end end diff --git a/core/commit_stage.sv b/core/commit_stage.sv index 8984b7d626..b717f785aa 100644 --- a/core/commit_stage.sv +++ b/core/commit_stage.sv @@ -115,9 +115,8 @@ module commit_stage for (int i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin dirty_fp_state_o |= commit_ack_o[i] & (commit_instr_i[i].fu inside {FPU, FPU_VEC} || (CVA6Cfg.FpPresent && ariane_pkg::is_rd_fpr( commit_instr_i[i].op - ))); - // Check if we issued a vector floating-point instruction to the accellerator - dirty_fp_state_o |= commit_instr_i[i].fu == ACCEL && commit_instr_i[i].vfp; + // Check if we issued a vector floating-point instruction to the accellerator + ))) | commit_instr_i[i].fu == ACCEL && commit_instr_i[i].vfp; end end diff --git a/core/controller.sv b/core/controller.sv index ebd0e0c75d..8016869ec3 100644 --- a/core/controller.sv +++ b/core/controller.sv @@ -124,7 +124,7 @@ module controller flush_ex_o = 1'b1; // this is not needed in the case since we // have a write-through cache in this case - if (CVA6Cfg.DCacheType == config_pkg::WB) begin + if (CVA6Cfg.DcacheFlushOnFence) begin flush_dcache = 1'b1; fence_active_d = 1'b1; end @@ -142,7 +142,7 @@ module controller flush_icache_o = 1'b1; // this is not needed in the case since we // have a write-through cache in this case - if (CVA6Cfg.DCacheType == config_pkg::WB) begin + if (CVA6Cfg.DcacheFlushOnFence) begin flush_dcache = 1'b1; fence_active_d = 1'b1; end @@ -150,7 +150,7 @@ module controller // this is not needed in the case since we // have a write-through cache in this case - if (CVA6Cfg.DCacheType == config_pkg::WB) begin + if (CVA6Cfg.DcacheFlushOnFence) begin // wait for the acknowledge here if (flush_dcache_ack_i && fence_active_q) begin fence_active_d = 1'b0; @@ -242,7 +242,7 @@ module controller // ---------------------- always_comb begin // halt the core if the fence is active - halt_o = halt_csr_i || halt_acc_i || (CVA6Cfg.DCacheType == config_pkg::WB && fence_active_q); + halt_o = halt_csr_i || halt_acc_i || (CVA6Cfg.DcacheFlushOnFence && fence_active_q); end // ---------------------- diff --git a/core/csr_regfile.sv b/core/csr_regfile.sv index e5cf84dcf3..0e8f851c88 100644 --- a/core/csr_regfile.sv +++ b/core/csr_regfile.sv @@ -886,7 +886,7 @@ module csr_regfile // -------------------- cycle_d = cycle_q; instret_d = instret_q; - if (!debug_mode_q) begin + if (!(CVA6Cfg.DebugEn && debug_mode_q)) begin // increase instruction retired counter for (int i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin if (commit_ack_i[i] && !ex_i.valid && (!CVA6Cfg.PerfCounterEn || (CVA6Cfg.PerfCounterEn && !mcountinhibit_q[2]))) @@ -949,7 +949,7 @@ module csr_regfile mcause_d = mcause_q; mcounteren_d = mcounteren_q; mscratch_d = mscratch_q; - mtval_d = mtval_q; + if (CVA6Cfg.TvalEn) mtval_d = mtval_q; if (CVA6Cfg.RVH) begin mtinst_d = mtinst_q; mtval2_d = mtval2_q; @@ -1435,9 +1435,14 @@ module csr_regfile | CVA6Cfg.XLEN'(riscv::MIP_MTIP) | CVA6Cfg.XLEN'(riscv::MIP_MEIP); end else begin - mask = CVA6Cfg.XLEN'(riscv::MIP_MSIP) - | CVA6Cfg.XLEN'(riscv::MIP_MTIP) - | CVA6Cfg.XLEN'(riscv::MIP_MEIP); + if (CVA6Cfg.SoftwareInterruptEn) begin + mask = CVA6Cfg.XLEN'(riscv::MIP_MSIP) // same shift as MSIE + | CVA6Cfg.XLEN'(riscv::MIP_MTIP) // same shift as MTIE + | CVA6Cfg.XLEN'(riscv::MIP_MEIP); // same shift as MEIE + end else begin + mask = CVA6Cfg.XLEN'(riscv::MIP_MTIP) // same shift as MTIE + | CVA6Cfg.XLEN'(riscv::MIP_MEIP); // same shift as MEIE + end end end mie_d = (mie_q & ~mask) | (csr_wdata & mask); // we only support supervisor and M-mode interrupts @@ -1715,9 +1720,10 @@ module csr_regfile default: update_access_exception = 1'b1; endcase end - - mstatus_d.sxl = riscv::XLEN_64; - mstatus_d.uxl = riscv::XLEN_64; + if (CVA6Cfg.IS_XLEN64) begin + mstatus_d.sxl = riscv::XLEN_64; + mstatus_d.uxl = riscv::XLEN_64; + end if (!CVA6Cfg.RVU) begin mstatus_d.mpp = riscv::PRIV_LVL_M; end @@ -1771,7 +1777,7 @@ module csr_regfile // Machine Mode External Interrupt Pending mip_d[riscv::IRQ_M_EXT] = irq_i[0]; // Machine software interrupt - mip_d[riscv::IRQ_M_SOFT] = ipi_i; + mip_d[riscv::IRQ_M_SOFT] = CVA6Cfg.SoftwareInterruptEn && ipi_i; // Timer interrupt pending, coming from platform timer mip_d[riscv::IRQ_M_TIMER] = time_irq_i; @@ -1791,38 +1797,24 @@ module csr_regfile // a m-mode trap might be delegated if we are taking it in S mode // first figure out if this was an exception or an interrupt e.g.: look at bit (XLEN-1) // the cause register can only be $clog2(CVA6Cfg.XLEN) bits long (as we only support XLEN exceptions) - if (CVA6Cfg.RVH) begin + if (CVA6Cfg.RVS) begin if ((ex_i.cause[CVA6Cfg.XLEN-1] && mideleg_q[ex_i.cause[$clog2( CVA6Cfg.XLEN - )-1:0]] && ~hideleg_q[ex_i.cause[$clog2( - CVA6Cfg.XLEN )-1:0]]) || (~ex_i.cause[CVA6Cfg.XLEN-1] && medeleg_q[ex_i.cause[$clog2( CVA6Cfg.XLEN - )-1:0]] && ~hedeleg_q[ex_i.cause[$clog2( - CVA6Cfg.XLEN )-1:0]])) begin // traps never transition from a more-privileged mode to a less privileged mode // so if we are already in M mode, stay there trap_to_priv_lvl = (priv_lvl_o == riscv::PRIV_LVL_M) ? riscv::PRIV_LVL_M : riscv::PRIV_LVL_S; - end else if ((ex_i.cause[CVA6Cfg.XLEN-1] && hideleg_q[ex_i.cause[$clog2( - CVA6Cfg.XLEN - )-1:0]]) || (~ex_i.cause[CVA6Cfg.XLEN-1] && hedeleg_q[ex_i.cause[$clog2( - CVA6Cfg.XLEN - )-1:0]])) begin - trap_to_priv_lvl = (priv_lvl_o == riscv::PRIV_LVL_M) ? riscv::PRIV_LVL_M : riscv::PRIV_LVL_S; - // trap to VS only if it is the currently active mode - trap_to_v = v_q; - end - end else begin - if (CVA6Cfg.RVS) begin - if ((ex_i.cause[CVA6Cfg.XLEN-1] && mideleg_q[ex_i.cause[$clog2( - CVA6Cfg.XLEN - )-1:0]]) || (~ex_i.cause[CVA6Cfg.XLEN-1] && medeleg_q[ex_i.cause[$clog2( - CVA6Cfg.XLEN - )-1:0]])) begin - // traps never transition from a more-privileged mode to a less privileged mode - // so if we are already in M mode, stay there - trap_to_priv_lvl = (priv_lvl_o == riscv::PRIV_LVL_M) ? riscv::PRIV_LVL_M : riscv::PRIV_LVL_S; + if (CVA6Cfg.RVH) begin + if ((ex_i.cause[CVA6Cfg.XLEN-1] && hideleg_q[ex_i.cause[$clog2( + CVA6Cfg.XLEN + )-1:0]]) || (~ex_i.cause[CVA6Cfg.XLEN-1] && hedeleg_q[ex_i.cause[$clog2( + CVA6Cfg.XLEN + )-1:0]])) begin + // trap to VS only if it is the currently active mode + trap_to_v = v_q; + end end end end @@ -2433,7 +2425,7 @@ module csr_regfile unique case (conv_csr_addr.address) riscv::CSR_MIP: - csr_rdata_o = csr_rdata | ({{CVA6Cfg.XLEN - 1{1'b0}}, irq_i[1]} << riscv::IRQ_S_EXT); + csr_rdata_o = csr_rdata | ({{CVA6Cfg.XLEN - 1{1'b0}}, CVA6Cfg.RVS && irq_i[1]} << riscv::IRQ_S_EXT); // in supervisor mode we also need to check whether we delegated this bit riscv::CSR_SIP: begin if (CVA6Cfg.RVS) begin @@ -2515,18 +2507,16 @@ module csr_regfile // sequential process always_ff @(posedge clk_i or negedge rst_ni) begin if (~rst_ni) begin - priv_lvl_q <= riscv::PRIV_LVL_M; + priv_lvl_q <= riscv::PRIV_LVL_M; // floating-point registers - fcsr_q <= '0; + fcsr_q <= '0; // debug signals - debug_mode_q <= 1'b0; if (CVA6Cfg.DebugEn) begin - dcsr_q <= '0; - dcsr_q.prv <= riscv::PRIV_LVL_M; - dcsr_q.xdebugver <= 4'h4; - dpc_q <= '0; - dscratch0_q <= {CVA6Cfg.XLEN{1'b0}}; - dscratch1_q <= {CVA6Cfg.XLEN{1'b0}}; + debug_mode_q <= 1'b0; + dcsr_q <= '{xdebugver: 4'h4, prv: riscv::PRIV_LVL_M, default: '0}; + dpc_q <= '0; + dscratch0_q <= {CVA6Cfg.XLEN{1'b0}}; + dscratch1_q <= {CVA6Cfg.XLEN{1'b0}}; end // machine mode registers mstatus_q <= 64'b0; @@ -2539,12 +2529,12 @@ module csr_regfile mcause_q <= {CVA6Cfg.XLEN{1'b0}}; mcounteren_q <= {CVA6Cfg.XLEN{1'b0}}; mscratch_q <= {CVA6Cfg.XLEN{1'b0}}; - mtval_q <= {CVA6Cfg.XLEN{1'b0}}; - fiom_q <= '0; - dcache_q <= {{CVA6Cfg.XLEN - 1{1'b0}}, 1'b1}; - icache_q <= {{CVA6Cfg.XLEN - 1{1'b0}}, 1'b1}; - mcountinhibit_q <= '0; - acc_cons_q <= {{CVA6Cfg.XLEN - 1{1'b0}}, CVA6Cfg.EnableAccelerator}; + if (CVA6Cfg.TvalEn) mtval_q <= {CVA6Cfg.XLEN{1'b0}}; + fiom_q <= '0; + dcache_q <= {{CVA6Cfg.XLEN - 1{1'b0}}, 1'b1}; + icache_q <= {{CVA6Cfg.XLEN - 1{1'b0}}, 1'b1}; + mcountinhibit_q <= '0; + acc_cons_q <= {{CVA6Cfg.XLEN - 1{1'b0}}, CVA6Cfg.EnableAccelerator}; // supervisor mode registers if (CVA6Cfg.RVS) begin medeleg_q <= {CVA6Cfg.XLEN{1'b0}}; @@ -2680,8 +2670,8 @@ module csr_regfile if (!CVA6Cfg.PMPEntryReadOnly[i]) begin // PMP locked logic is handled in the CSR write process above pmpcfg_next[i] = pmpcfg_d[i]; - // We only support >=8-byte granularity, NA4 is disabled - if (pmpcfg_d[i].addr_mode == riscv::NA4) begin + // We only support >=8-byte granularity, NA4 is not supported + if ((!CVA6Cfg.PMPNapotEn && pmpcfg_d[i].addr_mode == riscv::NAPOT) ||pmpcfg_d[i].addr_mode == riscv::NA4) begin pmpcfg_next[i].addr_mode = pmpcfg_q[i].addr_mode; end // Follow collective WARL spec for RWX fields @@ -2743,7 +2733,7 @@ module csr_regfile assign rvfi_csr_o.mscratch_q = mscratch_q; assign rvfi_csr_o.mepc_q = mepc_q; assign rvfi_csr_o.mcause_q = mcause_q; - assign rvfi_csr_o.mtval_q = mtval_q; + assign rvfi_csr_o.mtval_q = CVA6Cfg.TvalEn ? mtval_q : '0; assign rvfi_csr_o.fiom_q = fiom_q; assign rvfi_csr_o.mcountinhibit_q = mcountinhibit_q; assign rvfi_csr_o.cycle_q = cycle_q; diff --git a/core/cva6.sv b/core/cva6.sv index b06ccd128d..e898f50108 100644 --- a/core/cva6.sv +++ b/core/cva6.sv @@ -560,8 +560,8 @@ module cva6 logic acc_cons_en_csr; logic debug_mode; logic single_step_csr_commit; - riscv::pmpcfg_t [CVA6Cfg.NrPMPEntries-1:0] pmpcfg; - logic [CVA6Cfg.NrPMPEntries-1:0][CVA6Cfg.PLEN-3:0] pmpaddr; + riscv::pmpcfg_t [(CVA6Cfg.NrPMPEntries > 0 ? CVA6Cfg.NrPMPEntries-1 : 0):0] pmpcfg; + logic [(CVA6Cfg.NrPMPEntries > 0 ? CVA6Cfg.NrPMPEntries-1 : 0):0][CVA6Cfg.PLEN-3:0] pmpaddr; logic [31:0] mcountinhibit_csr_perf; // ---------------------------- // Performance Counters <-> * @@ -1326,7 +1326,11 @@ module cva6 .inval_valid_i (inval_valid), .inval_ready_o (inval_ready) ); - end else if (CVA6Cfg.DCacheType == config_pkg::HPDCACHE) begin : gen_cache_hpd + end else if (CVA6Cfg.DCacheType inside { + config_pkg::HPDCACHE_WT, + config_pkg::HPDCACHE_WB, + config_pkg::HPDCACHE_WT_WB}) + begin : gen_cache_hpd cva6_hpdcache_subsystem #( .CVA6Cfg (CVA6Cfg), .icache_areq_t(icache_areq_t), @@ -1533,9 +1537,7 @@ module cva6 // Parameter Check // ------------------- // pragma translate_off -`ifndef VERILATOR initial config_pkg::check_cfg(CVA6Cfg); -`endif // pragma translate_on // ------------------- @@ -1729,6 +1731,7 @@ module cva6 .wdata_i (wdata_commit_id), .csr_i(rvfi_csr), + .irq_i(irq_i), .rvfi_probes_o(rvfi_probes_o) diff --git a/core/cva6_fifo_v3.sv b/core/cva6_fifo_v3.sv index 4a9a560864..d1faa01b3a 100644 --- a/core/cva6_fifo_v3.sv +++ b/core/cva6_fifo_v3.sv @@ -77,13 +77,18 @@ module cva6_fifo_v3 #( read_pointer_n = read_pointer_q; write_pointer_n = write_pointer_q; status_cnt_n = status_cnt_q; - data_ft_n = data_ft_q; - first_word_n = first_word_q; + if (FPGA_EN && FPGA_ALTERA) data_ft_n = data_ft_q; + if (FPGA_EN && FPGA_ALTERA) first_word_n = first_word_q; if (FPGA_EN) begin fifo_ram_we = '0; fifo_ram_write_address = '0; fifo_ram_wdata = '0; - data_o = (DEPTH == 0) ? data_i : (first_word_q ? data_ft_q : fifo_ram_rdata); + if (DEPTH == 0) begin + data_o = data_i; + end else begin + if (FPGA_ALTERA) data_o = first_word_q ? data_ft_q : fifo_ram_rdata; + else data_o = fifo_ram_rdata; + end end else begin data_o = (DEPTH == 0) ? data_i : mem_q[read_pointer_q]; mem_n = mem_q; @@ -96,7 +101,7 @@ module cva6_fifo_v3 #( fifo_ram_we = 1'b1; fifo_ram_write_address = write_pointer_q; fifo_ram_wdata = data_i; - first_word_n = FPGA_ALTERA && first_word_q && pop_i; + if (FPGA_ALTERA) first_word_n = first_word_q && pop_i; end else begin // push the data onto the queue mem_n[write_pointer_q] = data_i; @@ -113,7 +118,7 @@ module cva6_fifo_v3 #( if (pop_i && ~empty_o) begin data_ft_n = data_i; - first_word_n = FPGA_EN && FPGA_ALTERA && first_word_q && push_i; + if (FPGA_EN && FPGA_ALTERA) first_word_n = first_word_q && push_i; // read from the queue is a default assignment // but increment the read pointer... if (read_pointer_n == FifoDepth[ADDR_DEPTH-1:0] - 1) read_pointer_n = '0; @@ -151,8 +156,8 @@ module cva6_fifo_v3 #( read_pointer_q <= '0; write_pointer_q <= '0; status_cnt_q <= '0; - first_word_q <= '0; - data_ft_q <= '0; + if (FPGA_ALTERA) first_word_q <= '0; + if (FPGA_ALTERA) data_ft_q <= '0; end else begin if (flush_i) begin read_pointer_q <= '0; @@ -209,7 +214,6 @@ module cva6_fifo_v3 #( end // pragma translate_off -`ifndef VERILATOR initial begin assert (DEPTH > 0) else $error("DEPTH must be greater than 0."); @@ -222,7 +226,6 @@ module cva6_fifo_v3 #( empty_read : assert property (@(posedge clk_i) disable iff (~rst_ni) (empty_o |-> ~pop_i)) else $fatal(1, "Trying to pop data although the FIFO is empty."); -`endif // pragma translate_on endmodule // fifo_v3 diff --git a/core/cva6_mmu/cva6_mmu.sv b/core/cva6_mmu/cva6_mmu.sv index 8c1791bbf0..5382279938 100644 --- a/core/cva6_mmu/cva6_mmu.sv +++ b/core/cva6_mmu/cva6_mmu.sv @@ -100,8 +100,8 @@ module cva6_mmu // PMP - input riscv::pmpcfg_t [CVA6Cfg.NrPMPEntries-1:0] pmpcfg_i, - input logic [CVA6Cfg.NrPMPEntries-1:0][CVA6Cfg.PLEN-3:0] pmpaddr_i + input riscv::pmpcfg_t [(CVA6Cfg.NrPMPEntries > 0 ? CVA6Cfg.NrPMPEntries-1 : 0):0] pmpcfg_i, + input logic [(CVA6Cfg.NrPMPEntries > 0 ? CVA6Cfg.NrPMPEntries-1 : 0):0][CVA6Cfg.PLEN-3:0] pmpaddr_i ); // memory management, pte for cva6 diff --git a/core/cva6_mmu/cva6_ptw.sv b/core/cva6_mmu/cva6_ptw.sv index c4713701dd..a5fef76fcc 100644 --- a/core/cva6_mmu/cva6_ptw.sv +++ b/core/cva6_mmu/cva6_ptw.sv @@ -83,8 +83,8 @@ module cva6_ptw output logic shared_tlb_miss_o, // PMP - input riscv::pmpcfg_t [CVA6Cfg.NrPMPEntries-1:0] pmpcfg_i, - input logic [CVA6Cfg.NrPMPEntries-1:0][CVA6Cfg.PLEN-3:0] pmpaddr_i, + input riscv::pmpcfg_t [(CVA6Cfg.NrPMPEntries > 0 ? CVA6Cfg.NrPMPEntries-1 : 0):0] pmpcfg_i, + input logic [(CVA6Cfg.NrPMPEntries > 0 ? CVA6Cfg.NrPMPEntries-1 : 0):0][CVA6Cfg.PLEN-3:0] pmpaddr_i, output logic [CVA6Cfg.PLEN-1:0] bad_paddr_o, output logic [CVA6Cfg.GPLEN-1:0] bad_gpaddr_o ); @@ -230,10 +230,7 @@ module cva6_ptw pmp #( - .CVA6Cfg (CVA6Cfg), - .PLEN (CVA6Cfg.PLEN), - .PMP_LEN (CVA6Cfg.PLEN - 2), - .NR_ENTRIES(CVA6Cfg.NrPMPEntries) + .CVA6Cfg(CVA6Cfg) ) i_pmp_ptw ( .addr_i (ptw_pptr_q), // PTW access are always checked as if in S-Mode... diff --git a/core/cva6_mmu/cva6_tlb.sv b/core/cva6_mmu/cva6_tlb.sv index 522004d3ea..68083f3e22 100644 --- a/core/cva6_mmu/cva6_tlb.sv +++ b/core/cva6_mmu/cva6_tlb.sv @@ -400,7 +400,6 @@ for ( //-------------- //pragma translate_off -`ifndef VERILATOR initial begin : p_assertions assert ((TLB_ENTRIES % 2 == 0) && (TLB_ENTRIES > 1)) @@ -435,7 +434,6 @@ for ( $stop(); end -`endif //pragma translate_on endmodule diff --git a/core/cva6_rvfi_probes.sv b/core/cva6_rvfi_probes.sv index 5e06e26295..cf23813c29 100644 --- a/core/cva6_rvfi_probes.sv +++ b/core/cva6_rvfi_probes.sv @@ -51,6 +51,7 @@ module cva6_rvfi_probes input logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.XLEN-1:0] wdata_i, input rvfi_probes_csr_t csr_i, + input logic [1:0] irq_i, output rvfi_probes_t rvfi_probes_o ); @@ -109,6 +110,7 @@ module cva6_rvfi_probes instr.wdata = wdata_i; csr = csr_i; + csr.mip_q = csr_i.mip_q | ({{CVA6Cfg.XLEN - 1{1'b0}}, CVA6Cfg.RVS && irq_i[1]} << riscv::IRQ_S_EXT); end diff --git a/core/cvxif_example/copro_alu.sv b/core/cvxif_example/copro_alu.sv index 672528454d..4e980ffea4 100644 --- a/core/cvxif_example/copro_alu.sv +++ b/core/cvxif_example/copro_alu.sv @@ -88,8 +88,32 @@ module copro_alu rd_n = rd_i; we_n = 1'b1; end - cvxif_instr_pkg::ADD_RS3_R4: begin - result_n = NrRgprPorts == 3 ? registers_i[2] + registers_i[1] + registers_i[0] : registers_i[1] + registers_i[0]; + cvxif_instr_pkg::MADD_RS3_R4: begin + result_n = NrRgprPorts == 3 ? (registers_i[0] + registers_i[1] + registers_i[2]) : (registers_i[0] + registers_i[1]); + hartid_n = hartid_i; + id_n = id_i; + valid_n = 1'b1; + rd_n = rd_i; + we_n = 1'b1; + end + cvxif_instr_pkg::MSUB_RS3_R4: begin + result_n = NrRgprPorts == 3 ? (registers_i[0] - registers_i[1] - registers_i[2]) : (registers_i[0] - registers_i[1]); + hartid_n = hartid_i; + id_n = id_i; + valid_n = 1'b1; + rd_n = rd_i; + we_n = 1'b1; + end + cvxif_instr_pkg::NMADD_RS3_R4: begin + result_n = NrRgprPorts == 3 ? ~(registers_i[0] + registers_i[1] + registers_i[2]) : ~(registers_i[0] + registers_i[1]); + hartid_n = hartid_i; + id_n = id_i; + valid_n = 1'b1; + rd_n = rd_i; + we_n = 1'b1; + end + cvxif_instr_pkg::NMSUB_RS3_R4: begin + result_n = NrRgprPorts == 3 ? ~(registers_i[0] - registers_i[1] - registers_i[2]) : ~(registers_i[0] - registers_i[1]); hartid_n = hartid_i; id_n = id_i; valid_n = 1'b1; diff --git a/core/cvxif_example/include/cvxif_instr_pkg.sv b/core/cvxif_example/include/cvxif_instr_pkg.sv index 2c0c8a34bd..496cddba8f 100644 --- a/core/cvxif_example/include/cvxif_instr_pkg.sv +++ b/core/cvxif_example/include/cvxif_instr_pkg.sv @@ -18,8 +18,11 @@ package cvxif_instr_pkg; DOUBLE_RS1 = 4'b0011, DOUBLE_RS2 = 4'b0100, ADD_MULTI = 4'b0101, - ADD_RS3_R4 = 4'b0110, - ADD_RS3_R = 4'b0111 + MADD_RS3_R4 = 4'b0110, + MSUB_RS3_R4 = 4'b0111, + NMADD_RS3_R4 = 4'b1000, + NMSUB_RS3_R4 = 4'b1001, + ADD_RS3_R = 4'b1111 } opcode_t; @@ -105,7 +108,7 @@ package cvxif_instr_pkg; 32'b00000_00_00000_00000_0_00_00000_1000011, // MADD opcode mask: 32'b00000_11_00000_00000_1_11_00000_1111111, resp : '{accept : 1'b1, writeback : 1'b1, register_read : {1'b1, 1'b1, 1'b1}}, - opcode : ADD_RS3_R4 + opcode : MADD_RS3_R4 }, '{ // Custom Add Multi rs1 : cus_add rd, rs1, rs1 @@ -113,7 +116,7 @@ package cvxif_instr_pkg; 32'b00000_00_00000_00000_0_00_00000_1000111, // MSUB opcode mask: 32'b00000_11_00000_00000_1_11_00000_1111111, resp : '{accept : 1'b1, writeback : 1'b1, register_read : {1'b1, 1'b1, 1'b1}}, - opcode : ADD_RS3_R4 + opcode : MSUB_RS3_R4 }, '{ // Custom Add Multi rs1 : cus_add rd, rs1, rs1 @@ -121,7 +124,7 @@ package cvxif_instr_pkg; 32'b00000_00_00000_00000_0_00_00000_1001011, // NMSUB opcode mask: 32'b00000_11_00000_00000_1_11_00000_1111111, resp : '{accept : 1'b1, writeback : 1'b1, register_read : {1'b1, 1'b1, 1'b1}}, - opcode : ADD_RS3_R4 + opcode : NMSUB_RS3_R4 }, '{ // Custom Add Multi rs1 : cus_add rd, rs1, rs1 @@ -129,7 +132,7 @@ package cvxif_instr_pkg; 32'b00000_00_00000_00000_0_00_00000_1001111, // NMADD opcode mask: 32'b00000_11_00000_00000_1_11_00000_1111111, resp : '{accept : 1'b1, writeback : 1'b1, register_read : {1'b1, 1'b1, 1'b1}}, - opcode : ADD_RS3_R4 + opcode : NMADD_RS3_R4 } }; diff --git a/core/cvxif_issue_register_commit_if_driver.sv b/core/cvxif_issue_register_commit_if_driver.sv index 16ebaa5bc7..88efc0002d 100644 --- a/core/cvxif_issue_register_commit_if_driver.sv +++ b/core/cvxif_issue_register_commit_if_driver.sv @@ -36,16 +36,14 @@ module cvxif_issue_register_commit_if_driver #( input logic [31:0] x_off_instr_i, input logic [CVA6Cfg.TRANS_ID_BITS-1:0] x_trans_id_i, input [(CVA6Cfg.NrRgprPorts/CVA6Cfg.NrIssuePorts)-1:0][CVA6Cfg.XLEN-1:0] register_i, - input logic [(CVA6Cfg.NrRgprPorts/CVA6Cfg.NrIssuePorts)-1:0] rs_valid_i, - output logic cvxif_busy_o + input logic [(CVA6Cfg.NrRgprPorts/CVA6Cfg.NrIssuePorts)-1:0] rs_valid_i ); // X_ISSUE_REGISTER_SPLIT = 0 : Issue and register transactions are synchrone // Mandatory assignement assign register_valid_o = issue_valid_o; assign register_o.hartid = issue_req_o.hartid; assign register_o.id = issue_req_o.id; - // cvxif can not take any more instruction if issue transaction is still up. - assign cvxif_busy_o = issue_valid_o && ~issue_ready_i; + always_comb begin issue_valid_o = valid_i && ~flush_i; issue_req_o.instr = x_off_instr_i; diff --git a/core/decoder.sv b/core/decoder.sv index 2d137648f0..40db72b5e3 100644 --- a/core/decoder.sv +++ b/core/decoder.sv @@ -812,10 +812,11 @@ module decoder unique case ({ CVA6Cfg.RVB, CVA6Cfg.RVZiCond }) - 2'b00: illegal_instr = illegal_instr_non_bm; - 2'b01: illegal_instr = illegal_instr_non_bm & illegal_instr_zic; - 2'b10: illegal_instr = illegal_instr_non_bm & illegal_instr_bm; - 2'b11: illegal_instr = illegal_instr_non_bm & illegal_instr_bm & illegal_instr_zic; + 2'b00: illegal_instr = illegal_instr_non_bm; + 2'b01: illegal_instr = illegal_instr_non_bm & illegal_instr_zic; + 2'b10: illegal_instr = illegal_instr_non_bm & illegal_instr_bm; + 2'b11: illegal_instr = illegal_instr_non_bm & illegal_instr_bm & illegal_instr_zic; + default: ; // TODO: Check that default case is not synthesized. endcase end end @@ -916,9 +917,18 @@ module decoder else if (instr.instr[24:20] == 5'b00000) instruction_o.op = ariane_pkg::CLZ; else if (instr.instr[24:20] == 5'b00001) instruction_o.op = ariane_pkg::CTZ; else illegal_instr_bm = 1'b1; - end else if (instr.instr[31:26] == 6'b010010) instruction_o.op = ariane_pkg::BCLRI; - else if (instr.instr[31:26] == 6'b011010) instruction_o.op = ariane_pkg::BINVI; - else if (instr.instr[31:26] == 6'b001010) instruction_o.op = ariane_pkg::BSETI; + end else if (CVA6Cfg.IS_XLEN64 && instr.instr[31:26] == 6'b010010) + instruction_o.op = ariane_pkg::BCLRI; + else if (CVA6Cfg.IS_XLEN32 && instr.instr[31:25] == 7'b0100100) + instruction_o.op = ariane_pkg::BCLRI; + else if (CVA6Cfg.IS_XLEN64 && instr.instr[31:26] == 6'b011010) + instruction_o.op = ariane_pkg::BINVI; + else if (CVA6Cfg.IS_XLEN32 && instr.instr[31:25] == 7'b0110100) + instruction_o.op = ariane_pkg::BINVI; + else if (CVA6Cfg.IS_XLEN64 && instr.instr[31:26] == 6'b001010) + instruction_o.op = ariane_pkg::BSETI; + else if (CVA6Cfg.IS_XLEN32 && instr.instr[31:25] == 7'b0010100) + instruction_o.op = ariane_pkg::BSETI; else if (CVA6Cfg.ZKN && instr.instr[31:20] == 12'b000010001111) instruction_o.op = ariane_pkg::ZIP; else illegal_instr_bm = 1'b1; @@ -929,8 +939,14 @@ module decoder instruction_o.op = ariane_pkg::REV8; else if (instr.instr[31:20] == 12'b011010011000) instruction_o.op = ariane_pkg::REV8; - else if (instr.instr[31:26] == 6'b010_010) instruction_o.op = ariane_pkg::BEXTI; - else if (instr.instr[31:26] == 6'b011_000) instruction_o.op = ariane_pkg::RORI; + else if (CVA6Cfg.IS_XLEN64 && instr.instr[31:26] == 6'b010_010) + instruction_o.op = ariane_pkg::BEXTI; + else if (CVA6Cfg.IS_XLEN32 && instr.instr[31:25] == 7'b010_0100) + instruction_o.op = ariane_pkg::BEXTI; + else if (CVA6Cfg.IS_XLEN64 && instr.instr[31:26] == 6'b011_000) + instruction_o.op = ariane_pkg::RORI; + else if (CVA6Cfg.IS_XLEN32 && instr.instr[31:25] == 7'b011_0000) + instruction_o.op = ariane_pkg::RORI; else if (CVA6Cfg.ZKN && instr.instr[31:20] == 12'b011010000111) instruction_o.op = ariane_pkg::BREV8; else if (CVA6Cfg.ZKN && instr.instr[31:20] == 12'b000010001111) diff --git a/core/ex_stage.sv b/core/ex_stage.sv index 115c17f1c5..3095a2c736 100644 --- a/core/ex_stage.sv +++ b/core/ex_stage.sv @@ -222,9 +222,9 @@ module ex_stage // To count the data TLB misses - PERF_COUNTERS output logic dtlb_miss_o, // Report the PMP configuration - CSR_REGFILE - input riscv::pmpcfg_t [CVA6Cfg.NrPMPEntries-1:0] pmpcfg_i, + input riscv::pmpcfg_t [(CVA6Cfg.NrPMPEntries > 0 ? CVA6Cfg.NrPMPEntries-1 : 0):0] pmpcfg_i, // Report the PMP addresses - CSR_REGFILE - input logic [CVA6Cfg.NrPMPEntries-1:0][CVA6Cfg.PLEN-3:0] pmpaddr_i, + input logic [(CVA6Cfg.NrPMPEntries > 0 ? CVA6Cfg.NrPMPEntries-1 : 0):0][CVA6Cfg.PLEN-3:0] pmpaddr_i, // Information dedicated to RVFI - RVFI output lsu_ctrl_t rvfi_lsu_ctrl_o, // Information dedicated to RVFI - RVFI diff --git a/core/frontend/frontend.sv b/core/frontend/frontend.sv index 3117e27654..1505140e8c 100644 --- a/core/frontend/frontend.sv +++ b/core/frontend/frontend.sv @@ -240,7 +240,7 @@ module frontend 4'b0001: begin ras_pop = 1'b0; ras_push = 1'b0; - if (CVA6Cfg.BTBEntries && btb_prediction_shifted[i].valid) begin + if (CVA6Cfg.BTBEntries != 0 && btb_prediction_shifted[i].valid) begin predict_address = btb_prediction_shifted[i].target_address; cf_type[i] = ariane_pkg::JumpR; end @@ -575,12 +575,4 @@ module frontend .fetch_entry_ready_i(fetch_entry_ready_i) // to back-end ); - // pragma translate_off -`ifndef VERILATOR - initial begin - assert (CVA6Cfg.FETCH_WIDTH == 32 || CVA6Cfg.FETCH_WIDTH == 64) - else $fatal(1, "[frontend] fetch width != not supported"); - end -`endif - // pragma translate_on endmodule diff --git a/core/frontend/instr_queue.sv b/core/frontend/instr_queue.sv index ceac06bbe2..28254e4708 100644 --- a/core/frontend/instr_queue.sv +++ b/core/frontend/instr_queue.sv @@ -551,7 +551,6 @@ module instr_queue end // pragma translate_off -`ifndef VERILATOR replay_address_fifo : assert property (@(posedge clk_i) disable iff (!rst_ni) replay_o |-> !i_fifo_address.push_i) else $fatal(1, "[instr_queue] Pushing address although replay asserted"); @@ -562,6 +561,5 @@ module instr_queue $error("Output select should be one-hot encoded"); $stop(); end -`endif // pragma translate_on endmodule diff --git a/core/id_stage.sv b/core/id_stage.sv index 6bed74bd4e..1ead6b9347 100644 --- a/core/id_stage.sv +++ b/core/id_stage.sv @@ -161,22 +161,22 @@ module id_stage #( .x_compressed_req_t(x_compressed_req_t), .x_compressed_resp_t(x_compressed_resp_t) ) i_cvxif_compressed_if_driver_i ( - .clk_i (clk_i), - .rst_ni (rst_ni), - .hart_id_i (hart_id_i), - .is_compressed_i (is_compressed_cvxif), - .is_illegal_i (is_illegal_cvxif), - .instruction_i (instruction_cvxif), - .instruction_valid_i (fetch_entry_valid_i), - .is_compressed_o (is_compressed_cmp), - .is_illegal_o (is_illegal_cmp), - .instruction_o (instruction), - .stall_i (stall_macro_deco), - .stall_o (stall_instr_fetch), - .compressed_ready_i(compressed_ready_i), - .compressed_resp_i (compressed_resp_i), - .compressed_valid_o(compressed_valid_o), - .compressed_req_o (compressed_req_o) + .clk_i (clk_i), + .rst_ni (rst_ni), + .hart_id_i (hart_id_i), + .is_compressed_i (is_compressed_cvxif), + .is_illegal_i (is_illegal_cvxif), + .instruction_i (instruction_cvxif), + .instruction_valid_i(fetch_entry_valid_i), + .is_compressed_o (is_compressed_cmp), + .is_illegal_o (is_illegal_cmp), + .instruction_o (instruction), + .stall_i (stall_macro_deco), + .stall_o (stall_instr_fetch), + .compressed_ready_i (compressed_ready_i), + .compressed_resp_i (compressed_resp_i), + .compressed_valid_o (compressed_valid_o), + .compressed_req_o (compressed_req_o) ); end else begin cvxif_compressed_if_driver #( @@ -184,22 +184,22 @@ module id_stage #( .x_compressed_req_t(x_compressed_req_t), .x_compressed_resp_t(x_compressed_resp_t) ) i_cvxif_compressed_if_driver_i ( - .clk_i (clk_i), - .rst_ni (rst_ni), - .hart_id_i (hart_id_i), - .is_compressed_i (is_compressed), - .is_illegal_i (is_illegal), - .instruction_valid_i (fetch_entry_valid_i), - .instruction_i (compressed_instr), - .is_compressed_o (is_compressed_cmp), - .is_illegal_o (is_illegal_cmp), - .instruction_o (instruction), - .stall_i (1'b0), - .stall_o (stall_instr_fetch), - .compressed_ready_i(compressed_ready_i), - .compressed_resp_i (compressed_resp_i), - .compressed_valid_o(compressed_valid_o), - .compressed_req_o (compressed_req_o) + .clk_i (clk_i), + .rst_ni (rst_ni), + .hart_id_i (hart_id_i), + .is_compressed_i (is_compressed), + .is_illegal_i (is_illegal), + .instruction_valid_i(fetch_entry_valid_i), + .instruction_i (compressed_instr), + .is_compressed_o (is_compressed_cmp), + .is_illegal_o (is_illegal_cmp), + .instruction_o (instruction), + .stall_i (1'b0), + .stall_o (stall_instr_fetch), + .compressed_ready_i (compressed_ready_i), + .compressed_resp_i (compressed_resp_i), + .compressed_valid_o (compressed_valid_o), + .compressed_req_o (compressed_req_o) ); assign is_last_macro_instr_o = '0; assign is_double_rd_macro_instr_o = '0; diff --git a/core/include/ariane_pkg.sv b/core/include/ariane_pkg.sv index 9e2e0aa80c..254721b200 100644 --- a/core/include/ariane_pkg.sv +++ b/core/include/ariane_pkg.sv @@ -31,8 +31,6 @@ package ariane_pkg; // TODO: Slowly move those parameters to the new system. localparam BITS_SATURATION_COUNTER = 2; - localparam ISSUE_WIDTH = 1; - // depth of store-buffers, this needs to be a power of two localparam logic [2:0] DEPTH_SPEC = 'd4; diff --git a/core/include/build_config_pkg.sv b/core/include/build_config_pkg.sv index 5c42e5f305..332a094356 100644 --- a/core/include/build_config_pkg.sv +++ b/core/include/build_config_pkg.sv @@ -95,6 +95,7 @@ package build_config_pkg; cfg.MmuPresent = CVA6Cfg.MmuPresent; cfg.RVS = CVA6Cfg.RVS; cfg.RVU = CVA6Cfg.RVU; + cfg.SoftwareInterruptEn = CVA6Cfg.SoftwareInterruptEn; cfg.HaltAddress = CVA6Cfg.HaltAddress; cfg.ExceptionAddress = CVA6Cfg.ExceptionAddress; @@ -108,6 +109,7 @@ package build_config_pkg; cfg.PMPCfgRstVal = CVA6Cfg.PMPCfgRstVal; cfg.PMPAddrRstVal = CVA6Cfg.PMPAddrRstVal; cfg.PMPEntryReadOnly = CVA6Cfg.PMPEntryReadOnly; + cfg.PMPNapotEn = CVA6Cfg.PMPNapotEn; cfg.NOCType = CVA6Cfg.NOCType; cfg.NrNonIdempotentRules = CVA6Cfg.NrNonIdempotentRules; cfg.NonIdempotentAddrBase = CVA6Cfg.NonIdempotentAddrBase; @@ -145,6 +147,9 @@ package build_config_pkg; cfg.DCACHE_MAX_TX = unsigned'(2 ** CVA6Cfg.MemTidWidth); + cfg.DcacheFlushOnFence = CVA6Cfg.DcacheFlushOnFence; + cfg.DcacheInvalidateOnFlush = CVA6Cfg.DcacheInvalidateOnFlush; + cfg.DATA_USER_EN = CVA6Cfg.DataUserEn; cfg.WtDcacheWbufDepth = CVA6Cfg.WtDcacheWbufDepth; cfg.FETCH_USER_WIDTH = CVA6Cfg.FetchUserWidth; diff --git a/core/include/config_pkg.sv b/core/include/config_pkg.sv index cd9c2bad96..002e45f785 100644 --- a/core/include/config_pkg.sv +++ b/core/include/config_pkg.sv @@ -27,10 +27,12 @@ package config_pkg; } noc_type_e; /// Cache type parameter - typedef enum logic [1:0] { + typedef enum logic [2:0] { WB = 0, WT = 1, - HPDCACHE = 2 + HPDCACHE_WT = 2, + HPDCACHE_WB = 3, + HPDCACHE_WT_WB = 4 } cache_type_t; /// Data and Address length @@ -92,6 +94,8 @@ package config_pkg; bit RVS; // User mode bit RVU; + // Software interrupts are enabled + bit SoftwareInterruptEn; // Debug support bit DebugEn; // Base address of the debug module @@ -112,6 +116,8 @@ package config_pkg; logic [63:0][63:0] PMPAddrRstVal; // PMP CSR read-only bits bit [63:0] PMPEntryReadOnly; + // PMP NA4 and NAPOT mode enable + bit PMPNapotEn; // PMA non idempotent rules number int unsigned NrNonIdempotentRules; // PMA NonIdempotent region base address @@ -162,6 +168,10 @@ package config_pkg; int unsigned DcacheSetAssoc; // Data cache line width int unsigned DcacheLineWidth; + // Data cache flush on fence + bit DcacheFlushOnFence; + // Data cache invalidate on flush + bit DcacheInvalidateOnFlush; // User field on data bus enable int unsigned DataUserEn; // Write-through data cache write buffer depth @@ -269,8 +279,9 @@ package config_pkg; bit EnableAccelerator; bit PerfCounterEn; bit MmuPresent; - bit RVS; //Supervisor mode - bit RVU; //User mode + bit RVS; //Supervisor mode + bit RVU; //User mode + bit SoftwareInterruptEn; logic [63:0] HaltAddress; logic [63:0] ExceptionAddress; @@ -291,6 +302,7 @@ package config_pkg; logic [63:0][63:0] PMPCfgRstVal; logic [63:0][63:0] PMPAddrRstVal; bit [63:0] PMPEntryReadOnly; + bit PMPNapotEn; noc_type_e NOCType; int unsigned NrNonIdempotentRules; logic [NrMaxRules-1:0][63:0] NonIdempotentAddrBase; @@ -326,6 +338,9 @@ package config_pkg; int unsigned DCACHE_MAX_TX; + bit DcacheFlushOnFence; + bit DcacheInvalidateOnFlush; + int unsigned DATA_USER_EN; int unsigned WtDcacheWbufDepth; int unsigned FETCH_USER_WIDTH; @@ -366,7 +381,6 @@ package config_pkg; /// sense for all parameters, here is the place to sanity check them. function automatic void check_cfg(cva6_cfg_t Cfg); // pragma translate_off -`ifndef VERILATOR assert (Cfg.RASDepth > 0); assert (Cfg.BTBEntries == 0 || (2 ** $clog2(Cfg.BTBEntries) == Cfg.BTBEntries)); assert (Cfg.BHTEntries == 0 || (2 ** $clog2(Cfg.BHTEntries) == Cfg.BHTEntries)); @@ -376,7 +390,12 @@ package config_pkg; assert (Cfg.NrPMPEntries <= 64); assert (!(Cfg.SuperscalarEn && Cfg.RVF)); assert (!(Cfg.SuperscalarEn && Cfg.RVZCMP)); -`endif + assert (Cfg.FETCH_WIDTH == 32 || Cfg.FETCH_WIDTH == 64) + else $fatal(1, "[frontend] fetch width != not supported"); + // Support for disabling MIP.MSIP and MIE.MSIE in Hypervisor and Supervisor mode is not supported + // Software Interrupt can be disabled when there is only M machine mode in CVA6. + assert (!(Cfg.RVS && !Cfg.SoftwareInterruptEn)); + assert (!(Cfg.RVH && !Cfg.SoftwareInterruptEn)); // pragma translate_on endfunction diff --git a/core/include/cv32a60x_config_pkg.sv b/core/include/cv32a60x_config_pkg.sv index f3f0a3982c..0337a8151b 100644 --- a/core/include/cv32a60x_config_pkg.sv +++ b/core/include/cv32a60x_config_pkg.sv @@ -55,6 +55,7 @@ package cva6_config_pkg; MmuPresent: bit'(0), RVS: bit'(0), RVU: bit'(0), + SoftwareInterruptEn: bit'(0), HaltAddress: 64'h800, ExceptionAddress: 64'h808, RASDepth: unsigned'(2), @@ -67,6 +68,7 @@ package cva6_config_pkg; PMPCfgRstVal: {64{64'h0}}, PMPAddrRstVal: {64{64'h0}}, PMPEntryReadOnly: 64'd0, + PMPNapotEn: bit'(0), NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, NrNonIdempotentRules: unsigned'(0), NonIdempotentAddrBase: 1024'({64'b0, 64'b0}), @@ -83,10 +85,12 @@ package cva6_config_pkg; IcacheByteSize: unsigned'(2048), IcacheSetAssoc: unsigned'(2), IcacheLineWidth: unsigned'(128), - DCacheType: config_pkg::HPDCACHE, + DCacheType: config_pkg::HPDCACHE_WT, DcacheByteSize: unsigned'(2028), DcacheSetAssoc: unsigned'(2), DcacheLineWidth: unsigned'(128), + DcacheFlushOnFence: bit'(0), + DcacheInvalidateOnFlush: bit'(0), DataUserEn: unsigned'(1), WtDcacheWbufDepth: int'(8), FetchUserWidth: unsigned'(32), diff --git a/core/include/cv32a65x_config_pkg.sv b/core/include/cv32a65x_config_pkg.sv index 788ae83e9b..d64670aab2 100644 --- a/core/include/cv32a65x_config_pkg.sv +++ b/core/include/cv32a65x_config_pkg.sv @@ -55,6 +55,7 @@ package cva6_config_pkg; MmuPresent: bit'(0), RVS: bit'(0), RVU: bit'(0), + SoftwareInterruptEn: bit'(0), HaltAddress: 64'h800, ExceptionAddress: 64'h808, RASDepth: unsigned'(2), @@ -67,6 +68,7 @@ package cva6_config_pkg; PMPCfgRstVal: {64{64'h0}}, PMPAddrRstVal: {64{64'h0}}, PMPEntryReadOnly: 64'd0, + PMPNapotEn: bit'(0), NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, NrNonIdempotentRules: unsigned'(0), NonIdempotentAddrBase: 1024'({64'b0, 64'b0}), @@ -83,10 +85,12 @@ package cva6_config_pkg; IcacheByteSize: unsigned'(2048), IcacheSetAssoc: unsigned'(2), IcacheLineWidth: unsigned'(128), - DCacheType: config_pkg::HPDCACHE, + DCacheType: config_pkg::HPDCACHE_WT, DcacheByteSize: unsigned'(2028), DcacheSetAssoc: unsigned'(2), DcacheLineWidth: unsigned'(128), + DcacheFlushOnFence: bit'(0), + DcacheInvalidateOnFlush: bit'(0), DataUserEn: unsigned'(1), WtDcacheWbufDepth: int'(8), FetchUserWidth: unsigned'(32), diff --git a/core/include/cv32a6_embedded_config_pkg_deprecated.sv b/core/include/cv32a6_embedded_config_pkg_deprecated.sv index 9168be9ed6..bcf2234819 100644 --- a/core/include/cv32a6_embedded_config_pkg_deprecated.sv +++ b/core/include/cv32a6_embedded_config_pkg_deprecated.sv @@ -42,6 +42,9 @@ package cva6_config_pkg; localparam CVA6ConfigDcacheSetAssoc = 8; localparam CVA6ConfigDcacheLineWidth = 128; + localparam CVA6ConfigDcacheFlushOnFence = 1'b0; + localparam CVA6ConfigDcacheInvalidateOnFlush = 1'b0; + localparam CVA6ConfigDcacheIdWidth = 1; localparam CVA6ConfigMemTidWidth = 2; @@ -106,6 +109,7 @@ package cva6_config_pkg; MmuPresent: bit'(CVA6ConfigMmuPresent), RVS: bit'(0), RVU: bit'(0), + SoftwareInterruptEn: bit'(1), HaltAddress: 64'h800, ExceptionAddress: 64'h808, RASDepth: unsigned'(CVA6ConfigRASDepth), @@ -118,6 +122,7 @@ package cva6_config_pkg; PMPCfgRstVal: {64{64'h0}}, PMPAddrRstVal: {64{64'h0}}, PMPEntryReadOnly: 64'd0, + PMPNapotEn: bit'(1), NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, NrNonIdempotentRules: unsigned'(2), NonIdempotentAddrBase: 1024'({64'b0, 64'b0}), @@ -138,6 +143,8 @@ package cva6_config_pkg; DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize), DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc), DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth), + DcacheFlushOnFence: bit'(CVA6ConfigDcacheFlushOnFence), + DcacheInvalidateOnFlush: bit'(CVA6ConfigDcacheInvalidateOnFlush), DataUserEn: unsigned'(CVA6ConfigDataUserEn), WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth), FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth), diff --git a/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv b/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv index b65b0a0add..199403c398 100644 --- a/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv +++ b/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv @@ -107,6 +107,7 @@ package cva6_config_pkg; MmuPresent: bit'(CVA6ConfigMmuPresent), RVS: bit'(1), RVU: bit'(1), + SoftwareInterruptEn: bit'(1), HaltAddress: 64'h800, ExceptionAddress: 64'h808, RASDepth: unsigned'(CVA6ConfigRASDepth), @@ -119,6 +120,7 @@ package cva6_config_pkg; PMPCfgRstVal: {64{64'h0}}, PMPAddrRstVal: {64{64'h0}}, PMPEntryReadOnly: 64'd0, + PMPNapotEn: bit'(1), NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, NrNonIdempotentRules: unsigned'(2), NonIdempotentAddrBase: 1024'({64'b0, 64'b0}), @@ -139,6 +141,8 @@ package cva6_config_pkg; DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize), DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc), DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth), + DcacheFlushOnFence: bit'(0), + DcacheInvalidateOnFlush: bit'(0), DataUserEn: unsigned'(CVA6ConfigDataUserEn), WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth), FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth), diff --git a/core/include/cv32a6_imac_sv0_config_pkg.sv b/core/include/cv32a6_imac_sv0_config_pkg.sv index 9d5edd3653..72ca224f4e 100644 --- a/core/include/cv32a6_imac_sv0_config_pkg.sv +++ b/core/include/cv32a6_imac_sv0_config_pkg.sv @@ -107,6 +107,7 @@ package cva6_config_pkg; MmuPresent: bit'(CVA6ConfigMmuPresent), RVS: bit'(1), RVU: bit'(1), + SoftwareInterruptEn: bit'(1), HaltAddress: 64'h800, ExceptionAddress: 64'h808, RASDepth: unsigned'(CVA6ConfigRASDepth), @@ -119,6 +120,7 @@ package cva6_config_pkg; PMPCfgRstVal: {64{64'h0}}, PMPAddrRstVal: {64{64'h0}}, PMPEntryReadOnly: 64'd0, + PMPNapotEn: bit'(1), NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, NrNonIdempotentRules: unsigned'(2), NonIdempotentAddrBase: 1024'({64'b0, 64'b0}), @@ -139,6 +141,8 @@ package cva6_config_pkg; DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize), DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc), DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth), + DcacheFlushOnFence: bit'(0), + DcacheInvalidateOnFlush: bit'(0), DataUserEn: unsigned'(CVA6ConfigDataUserEn), WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth), FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth), diff --git a/core/include/cv32a6_imac_sv32_config_pkg.sv b/core/include/cv32a6_imac_sv32_config_pkg.sv index f10df730ef..7bf6f5dc27 100644 --- a/core/include/cv32a6_imac_sv32_config_pkg.sv +++ b/core/include/cv32a6_imac_sv32_config_pkg.sv @@ -63,7 +63,7 @@ package cva6_config_pkg; localparam CVA6ConfigPerfCounterEn = 1; - localparam config_pkg::cache_type_t CVA6ConfigDcacheType = config_pkg::HPDCACHE; + localparam config_pkg::cache_type_t CVA6ConfigDcacheType = config_pkg::HPDCACHE_WT; localparam CVA6ConfigMmuPresent = 1; @@ -106,6 +106,7 @@ package cva6_config_pkg; MmuPresent: bit'(CVA6ConfigMmuPresent), RVS: bit'(1), RVU: bit'(1), + SoftwareInterruptEn: bit'(1), HaltAddress: 64'h800, ExceptionAddress: 64'h808, RASDepth: unsigned'(CVA6ConfigRASDepth), @@ -118,6 +119,7 @@ package cva6_config_pkg; PMPCfgRstVal: {64{64'h0}}, PMPAddrRstVal: {64{64'h0}}, PMPEntryReadOnly: 64'd0, + PMPNapotEn: bit'(1), NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, NrNonIdempotentRules: unsigned'(1), NonIdempotentAddrBase: 1024'({64'b0}), @@ -138,6 +140,8 @@ package cva6_config_pkg; DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize), DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc), DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth), + DcacheFlushOnFence: bit'(0), + DcacheInvalidateOnFlush: bit'(0), DataUserEn: unsigned'(CVA6ConfigDataUserEn), WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth), FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth), diff --git a/core/include/cv32a6_imafc_sv32_config_pkg.sv b/core/include/cv32a6_imafc_sv32_config_pkg.sv index c29dd93f60..0b6964ea7f 100644 --- a/core/include/cv32a6_imafc_sv32_config_pkg.sv +++ b/core/include/cv32a6_imafc_sv32_config_pkg.sv @@ -107,6 +107,7 @@ package cva6_config_pkg; MmuPresent: bit'(CVA6ConfigMmuPresent), RVS: bit'(1), RVU: bit'(1), + SoftwareInterruptEn: bit'(1), HaltAddress: 64'h800, ExceptionAddress: 64'h808, RASDepth: unsigned'(CVA6ConfigRASDepth), @@ -119,6 +120,7 @@ package cva6_config_pkg; PMPCfgRstVal: {64{64'h0}}, PMPAddrRstVal: {64{64'h0}}, PMPEntryReadOnly: 64'd0, + PMPNapotEn: bit'(1), NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, NrNonIdempotentRules: unsigned'(2), NonIdempotentAddrBase: 1024'({64'b0, 64'b0}), @@ -135,10 +137,12 @@ package cva6_config_pkg; IcacheByteSize: unsigned'(CVA6ConfigIcacheByteSize), IcacheSetAssoc: unsigned'(CVA6ConfigIcacheSetAssoc), IcacheLineWidth: unsigned'(CVA6ConfigIcacheLineWidth), + DCacheType: CVA6ConfigDcacheType, DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize), DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc), DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth), - DCacheType: CVA6ConfigDcacheType, + DcacheFlushOnFence: bit'(0), + DcacheInvalidateOnFlush: bit'(0), DataUserEn: unsigned'(CVA6ConfigDataUserEn), WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth), FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth), diff --git a/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv b/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv index 26d5819862..1af56f698d 100644 --- a/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv +++ b/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv @@ -43,6 +43,9 @@ package cva6_config_pkg; localparam CVA6ConfigDcacheSetAssoc = 8; localparam CVA6ConfigDcacheLineWidth = 128; + localparam CVA6ConfigDcacheFlushOnFence = 1'b0; + localparam CVA6ConfigDcacheInvalidateOnFlush = 1'b0; + localparam CVA6ConfigDcacheIdWidth = 1; localparam CVA6ConfigMemTidWidth = 2; @@ -107,6 +110,7 @@ package cva6_config_pkg; MmuPresent: bit'(CVA6ConfigMmuPresent), RVS: bit'(1), RVU: bit'(1), + SoftwareInterruptEn: bit'(1), HaltAddress: 64'h800, ExceptionAddress: 64'h808, RASDepth: unsigned'(CVA6ConfigRASDepth), @@ -119,6 +123,7 @@ package cva6_config_pkg; PMPCfgRstVal: {64{64'h0}}, PMPAddrRstVal: {64{64'h0}}, PMPEntryReadOnly: 64'd0, + PMPNapotEn: bit'(1), NOCType: config_pkg::NOC_TYPE_L15_BIG_ENDIAN, NrNonIdempotentRules: unsigned'(2), NonIdempotentAddrBase: 1024'({64'b0, 64'b0}), @@ -139,6 +144,8 @@ package cva6_config_pkg; DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize), DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc), DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth), + DcacheFlushOnFence: bit'(CVA6ConfigDcacheFlushOnFence), + DcacheInvalidateOnFlush: bit'(CVA6ConfigDcacheInvalidateOnFlush), DataUserEn: unsigned'(CVA6ConfigDataUserEn), WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth), FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth), diff --git a/core/include/cv64a6_imafdc_sv39_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_config_pkg.sv index c7a6cc5f85..d76b757c94 100644 --- a/core/include/cv64a6_imafdc_sv39_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_config_pkg.sv @@ -43,6 +43,9 @@ package cva6_config_pkg; localparam CVA6ConfigDcacheSetAssoc = 8; localparam CVA6ConfigDcacheLineWidth = 128; + localparam CVA6ConfigDcacheFlushOnFence = 1'b0; + localparam CVA6ConfigDcacheInvalidateOnFlush = 1'b0; + localparam CVA6ConfigDcacheIdWidth = 1; localparam CVA6ConfigMemTidWidth = 2; @@ -107,6 +110,7 @@ package cva6_config_pkg; MmuPresent: bit'(CVA6ConfigMmuPresent), RVS: bit'(1), RVU: bit'(1), + SoftwareInterruptEn: bit'(1), HaltAddress: 64'h800, ExceptionAddress: 64'h808, RASDepth: unsigned'(CVA6ConfigRASDepth), @@ -119,6 +123,7 @@ package cva6_config_pkg; PMPCfgRstVal: {64{64'h0}}, PMPAddrRstVal: {64{64'h0}}, PMPEntryReadOnly: 64'd0, + PMPNapotEn: bit'(1), NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, NrNonIdempotentRules: unsigned'(2), NonIdempotentAddrBase: 1024'({64'b0, 64'b0}), @@ -139,6 +144,8 @@ package cva6_config_pkg; DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize), DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc), DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth), + DcacheFlushOnFence: unsigned'(CVA6ConfigDcacheFlushOnFence), + DcacheInvalidateOnFlush: unsigned'(CVA6ConfigDcacheInvalidateOnFlush), DataUserEn: unsigned'(CVA6ConfigDataUserEn), WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth), FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth), diff --git a/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv index 8be842fa27..df092b7370 100644 --- a/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv @@ -50,6 +50,9 @@ package cva6_config_pkg; localparam CVA6ConfigDcacheSetAssoc = 8; localparam CVA6ConfigDcacheLineWidth = 128; + localparam CVA6ConfigDcacheFlushOnFence = 1'b0; + localparam CVA6ConfigDcacheInvalidateOnFlush = 1'b0; + localparam CVA6ConfigDcacheIdWidth = 3; localparam CVA6ConfigMemTidWidth = CVA6ConfigAxiIdWidth; @@ -71,7 +74,7 @@ package cva6_config_pkg; localparam CVA6ConfigPerfCounterEn = 1; - localparam config_pkg::cache_type_t CVA6ConfigDcacheType = config_pkg::HPDCACHE; + localparam config_pkg::cache_type_t CVA6ConfigDcacheType = config_pkg::HPDCACHE_WT; localparam CVA6ConfigMmuPresent = 1; @@ -114,6 +117,7 @@ package cva6_config_pkg; MmuPresent: bit'(CVA6ConfigMmuPresent), RVS: bit'(1), RVU: bit'(1), + SoftwareInterruptEn: bit'(1), HaltAddress: 64'h800, ExceptionAddress: 64'h808, RASDepth: unsigned'(CVA6ConfigRASDepth), @@ -126,6 +130,7 @@ package cva6_config_pkg; PMPCfgRstVal: {64{64'h0}}, PMPAddrRstVal: {64{64'h0}}, PMPEntryReadOnly: 64'd0, + PMPNapotEn: bit'(1), NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, NrNonIdempotentRules: unsigned'(2), NonIdempotentAddrBase: 1024'({64'b0, 64'b0}), @@ -146,6 +151,8 @@ package cva6_config_pkg; DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize), DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc), DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth), + DcacheFlushOnFence: bit'(CVA6ConfigDcacheFlushOnFence), + DcacheInvalidateOnFlush: bit'(CVA6ConfigDcacheInvalidateOnFlush), DataUserEn: unsigned'(CVA6ConfigDataUserEn), WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth), FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth), diff --git a/core/include/cv64a6_imafdc_sv39_hpdcache_wb_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_hpdcache_wb_config_pkg.sv new file mode 100644 index 0000000000..88fa3f2af8 --- /dev/null +++ b/core/include/cv64a6_imafdc_sv39_hpdcache_wb_config_pkg.sv @@ -0,0 +1,169 @@ +// Copyright 2021 Thales DIS design services SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Jean-Roch COULON - Thales +// +// Copyright 2023 Commissariat a l'Energie Atomique et aux Energies +// Alternatives (CEA) +// +// Author: Cesar Fuguet - CEA +// Date: August, 2023 +// Description: CVA6 configuration package using the HPDcache as cache subsystem + + +package cva6_config_pkg; + + localparam CVA6ConfigXlen = 64; + + localparam CVA6ConfigRVF = 1; + localparam CVA6ConfigF16En = 0; + localparam CVA6ConfigF16AltEn = 0; + localparam CVA6ConfigF8En = 0; + localparam CVA6ConfigFVecEn = 0; + + localparam CVA6ConfigCvxifEn = 1; + localparam CVA6ConfigCExtEn = 1; + localparam CVA6ConfigZcbExtEn = 1; + localparam CVA6ConfigZcmpExtEn = 0; + localparam CVA6ConfigAExtEn = 1; + localparam CVA6ConfigBExtEn = 1; + localparam CVA6ConfigVExtEn = 0; + localparam CVA6ConfigHExtEn = 0; + localparam CVA6ConfigRVZiCond = 1; + + localparam CVA6ConfigAxiIdWidth = 4; + localparam CVA6ConfigAxiAddrWidth = 64; + localparam CVA6ConfigAxiDataWidth = 64; + localparam CVA6ConfigFetchUserEn = 0; + localparam CVA6ConfigFetchUserWidth = CVA6ConfigXlen; + localparam CVA6ConfigDataUserEn = 0; + localparam CVA6ConfigDataUserWidth = CVA6ConfigXlen; + + localparam CVA6ConfigIcacheByteSize = 16384; + localparam CVA6ConfigIcacheSetAssoc = 4; + localparam CVA6ConfigIcacheLineWidth = 128; + localparam CVA6ConfigDcacheByteSize = 32768; + localparam CVA6ConfigDcacheSetAssoc = 8; + localparam CVA6ConfigDcacheLineWidth = 128; + + localparam CVA6ConfigDcacheFlushOnFence = 1'b1; + localparam CVA6ConfigDcacheInvalidateOnFlush = 1'b0; + + localparam CVA6ConfigDcacheIdWidth = 3; + localparam CVA6ConfigMemTidWidth = CVA6ConfigAxiIdWidth; + + localparam CVA6ConfigWtDcacheWbufDepth = 8; + + localparam CVA6ConfigNrScoreboardEntries = 8; + + localparam CVA6ConfigNrLoadPipeRegs = 1; + localparam CVA6ConfigNrStorePipeRegs = 0; + localparam CVA6ConfigNrLoadBufEntries = 8; + + localparam CVA6ConfigRASDepth = 2; + localparam CVA6ConfigBTBEntries = 32; + localparam CVA6ConfigBHTEntries = 128; + + localparam CVA6ConfigTvalEn = 1; + + localparam CVA6ConfigNrPMPEntries = 8; + + localparam CVA6ConfigPerfCounterEn = 1; + + localparam config_pkg::cache_type_t CVA6ConfigDcacheType = config_pkg::HPDCACHE_WB; + + localparam CVA6ConfigMmuPresent = 1; + + localparam CVA6ConfigRvfiTrace = 1; + + localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{ + XLEN: unsigned'(CVA6ConfigXlen), + VLEN: unsigned'(64), + FpgaEn: bit'(0), // for Xilinx and Altera + FpgaAlteraEn: bit'(0), // for Altera (only) + TechnoCut: bit'(0), + SuperscalarEn: bit'(0), + NrCommitPorts: unsigned'(2), + AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth), + AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth), + AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth), + AxiUserWidth: unsigned'(CVA6ConfigDataUserWidth), + MemTidWidth: unsigned'(CVA6ConfigMemTidWidth), + NrLoadBufEntries: unsigned'(CVA6ConfigNrLoadBufEntries), + RVF: bit'(CVA6ConfigRVF), + RVD: bit'(CVA6ConfigRVF), + XF16: bit'(CVA6ConfigF16En), + XF16ALT: bit'(CVA6ConfigF16AltEn), + XF8: bit'(CVA6ConfigF8En), + RVA: bit'(CVA6ConfigAExtEn), + RVB: bit'(CVA6ConfigBExtEn), + ZKN: bit'(1), + RVV: bit'(CVA6ConfigVExtEn), + RVC: bit'(CVA6ConfigCExtEn), + RVH: bit'(CVA6ConfigHExtEn), + RVZCB: bit'(CVA6ConfigZcbExtEn), + RVZCMP: bit'(CVA6ConfigZcmpExtEn), + XFVec: bit'(CVA6ConfigFVecEn), + CvxifEn: bit'(CVA6ConfigCvxifEn), + RVZiCond: bit'(CVA6ConfigRVZiCond), + RVZicntr: bit'(1), + RVZihpm: bit'(1), + NrScoreboardEntries: unsigned'(CVA6ConfigNrScoreboardEntries), + PerfCounterEn: bit'(CVA6ConfigPerfCounterEn), + MmuPresent: bit'(CVA6ConfigMmuPresent), + RVS: bit'(1), + RVU: bit'(1), + SoftwareInterruptEn: bit'(1), + HaltAddress: 64'h800, + ExceptionAddress: 64'h808, + RASDepth: unsigned'(CVA6ConfigRASDepth), + BTBEntries: unsigned'(CVA6ConfigBTBEntries), + BHTEntries: unsigned'(CVA6ConfigBHTEntries), + DmBaseAddress: 64'h0, + TvalEn: bit'(CVA6ConfigTvalEn), + DirectVecOnly: bit'(0), + NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries), + PMPCfgRstVal: {64{64'h0}}, + PMPAddrRstVal: {64{64'h0}}, + PMPEntryReadOnly: 64'd0, + PMPNapotEn: bit'(1), + NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, + NrNonIdempotentRules: unsigned'(2), + NonIdempotentAddrBase: 1024'({64'b0, 64'b0}), + NonIdempotentLength: 1024'({64'b0, 64'b0}), + NrExecuteRegionRules: unsigned'(3), + ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h1_0000, 64'h0}), + ExecuteRegionLength: 1024'({64'h40000000, 64'h10000, 64'h1000}), + NrCachedRegionRules: unsigned'(1), + CachedRegionAddrBase: 1024'({64'h8000_0000}), + CachedRegionLength: 1024'({64'h40000000}), + MaxOutstandingStores: unsigned'(7), + DebugEn: bit'(1), + AxiBurstWriteEn: bit'(0), + IcacheByteSize: unsigned'(CVA6ConfigIcacheByteSize), + IcacheSetAssoc: unsigned'(CVA6ConfigIcacheSetAssoc), + IcacheLineWidth: unsigned'(CVA6ConfigIcacheLineWidth), + DCacheType: CVA6ConfigDcacheType, + DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize), + DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc), + DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth), + DcacheFlushOnFence: bit'(CVA6ConfigDcacheFlushOnFence), + DcacheInvalidateOnFlush: bit'(CVA6ConfigDcacheInvalidateOnFlush), + DataUserEn: unsigned'(CVA6ConfigDataUserEn), + WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth), + FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth), + FetchUserEn: unsigned'(CVA6ConfigFetchUserEn), + InstrTlbEntries: int'(16), + DataTlbEntries: int'(16), + UseSharedTlb: bit'(0), + SharedTlbDepth: int'(64), + NrLoadPipeRegs: int'(CVA6ConfigNrLoadPipeRegs), + NrStorePipeRegs: int'(CVA6ConfigNrStorePipeRegs), + DcacheIdWidth: int'(CVA6ConfigDcacheIdWidth) + }; + +endpackage diff --git a/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv index e36dffbdb2..3f22ee98a4 100644 --- a/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv @@ -43,6 +43,9 @@ package cva6_config_pkg; localparam CVA6ConfigDcacheSetAssoc = 8; localparam CVA6ConfigDcacheLineWidth = 128; + localparam CVA6ConfigDcacheFlushOnFence = 1'b0; + localparam CVA6ConfigDcacheInvalidateOnFlush = 1'b0; + localparam CVA6ConfigDcacheIdWidth = 1; localparam CVA6ConfigMemTidWidth = 2; @@ -107,6 +110,7 @@ package cva6_config_pkg; MmuPresent: bit'(CVA6ConfigMmuPresent), RVS: bit'(1), RVU: bit'(1), + SoftwareInterruptEn: bit'(1), HaltAddress: 64'h800, ExceptionAddress: 64'h808, RASDepth: unsigned'(CVA6ConfigRASDepth), @@ -119,6 +123,7 @@ package cva6_config_pkg; PMPCfgRstVal: {64{64'h0}}, PMPAddrRstVal: {64{64'h0}}, PMPEntryReadOnly: 64'd0, + PMPNapotEn: bit'(1), NOCType: config_pkg::NOC_TYPE_L15_BIG_ENDIAN, NrNonIdempotentRules: unsigned'(2), NonIdempotentAddrBase: 1024'({64'b0, 64'b0}), @@ -139,6 +144,8 @@ package cva6_config_pkg; DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize), DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc), DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth), + DcacheFlushOnFence: unsigned'(CVA6ConfigDcacheFlushOnFence), + DcacheInvalidateOnFlush: unsigned'(CVA6ConfigDcacheInvalidateOnFlush), DataUserEn: unsigned'(CVA6ConfigDataUserEn), WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth), FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth), diff --git a/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv index 6f46e4127c..fbcef4e597 100644 --- a/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv @@ -43,6 +43,9 @@ package cva6_config_pkg; localparam CVA6ConfigDcacheSetAssoc = 8; localparam CVA6ConfigDcacheLineWidth = 128; + localparam CVA6ConfigDcacheFlushOnFence = 1'b1; + localparam CVA6ConfigDcacheInvalidateOnFlush = 1'b0; + localparam CVA6ConfigDcacheIdWidth = 1; localparam CVA6ConfigMemTidWidth = 2; @@ -107,6 +110,7 @@ package cva6_config_pkg; MmuPresent: bit'(CVA6ConfigMmuPresent), RVS: bit'(1), RVU: bit'(1), + SoftwareInterruptEn: bit'(1), HaltAddress: 64'h800, ExceptionAddress: 64'h808, RASDepth: unsigned'(CVA6ConfigRASDepth), @@ -119,6 +123,7 @@ package cva6_config_pkg; PMPCfgRstVal: {64{64'h0}}, PMPAddrRstVal: {64{64'h0}}, PMPEntryReadOnly: 64'd0, + PMPNapotEn: bit'(1), NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, NrNonIdempotentRules: unsigned'(2), NonIdempotentAddrBase: 1024'({64'b0, 64'b0}), @@ -139,6 +144,8 @@ package cva6_config_pkg; DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize), DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc), DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth), + DcacheFlushOnFence: unsigned'(CVA6ConfigDcacheFlushOnFence), + DcacheInvalidateOnFlush: unsigned'(CVA6ConfigDcacheInvalidateOnFlush), DataUserEn: unsigned'(CVA6ConfigDataUserEn), WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth), FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth), diff --git a/core/include/cv64a6_imafdch_sv39_config_pkg.sv b/core/include/cv64a6_imafdch_sv39_config_pkg.sv index 5cce0a9ec1..e5551ff5c4 100644 --- a/core/include/cv64a6_imafdch_sv39_config_pkg.sv +++ b/core/include/cv64a6_imafdch_sv39_config_pkg.sv @@ -43,6 +43,9 @@ package cva6_config_pkg; localparam CVA6ConfigDcacheSetAssoc = 8; localparam CVA6ConfigDcacheLineWidth = 128; + localparam CVA6ConfigDcacheFlushOnFence = 1'b0; + localparam CVA6ConfigDcacheInvalidateOnFlush = 1'b0; + localparam CVA6ConfigDcacheIdWidth = 1; localparam CVA6ConfigMemTidWidth = 2; @@ -107,6 +110,7 @@ package cva6_config_pkg; MmuPresent: bit'(CVA6ConfigMmuPresent), RVS: bit'(1), RVU: bit'(1), + SoftwareInterruptEn: bit'(1), HaltAddress: 64'h800, ExceptionAddress: 64'h808, RASDepth: unsigned'(CVA6ConfigRASDepth), @@ -119,6 +123,7 @@ package cva6_config_pkg; PMPCfgRstVal: {64{64'h0}}, PMPAddrRstVal: {64{64'h0}}, PMPEntryReadOnly: 64'd0, + PMPNapotEn: bit'(1), NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, NrNonIdempotentRules: unsigned'(2), NonIdempotentAddrBase: 1024'({64'b0, 64'b0}), @@ -139,6 +144,8 @@ package cva6_config_pkg; DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize), DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc), DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth), + DcacheFlushOnFence: unsigned'(CVA6ConfigDcacheFlushOnFence), + DcacheInvalidateOnFlush: unsigned'(CVA6ConfigDcacheInvalidateOnFlush), DataUserEn: unsigned'(CVA6ConfigDataUserEn), WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth), FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth), diff --git a/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv b/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv index 2705c7583b..909987eaab 100644 --- a/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv +++ b/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv @@ -43,6 +43,9 @@ package cva6_config_pkg; localparam CVA6ConfigDcacheSetAssoc = 8; localparam CVA6ConfigDcacheLineWidth = 128; + localparam CVA6ConfigDcacheFlushOnFence = 1'b1; + localparam CVA6ConfigDcacheInvalidateOnFlush = 1'b0; + localparam CVA6ConfigDcacheIdWidth = 1; localparam CVA6ConfigMemTidWidth = 2; @@ -107,6 +110,7 @@ package cva6_config_pkg; MmuPresent: bit'(CVA6ConfigMmuPresent), RVS: bit'(1), RVU: bit'(1), + SoftwareInterruptEn: bit'(1), HaltAddress: 64'h800, ExceptionAddress: 64'h808, RASDepth: unsigned'(CVA6ConfigRASDepth), @@ -119,6 +123,7 @@ package cva6_config_pkg; PMPCfgRstVal: {64{64'h0}}, PMPAddrRstVal: {64{64'h0}}, PMPEntryReadOnly: 64'd0, + PMPNapotEn: bit'(1), NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, NrNonIdempotentRules: unsigned'(2), NonIdempotentAddrBase: 1024'({64'b0, 64'b0}), @@ -139,6 +144,8 @@ package cva6_config_pkg; DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize), DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc), DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth), + DcacheFlushOnFence: unsigned'(CVA6ConfigDcacheFlushOnFence), + DcacheInvalidateOnFlush: unsigned'(CVA6ConfigDcacheInvalidateOnFlush), DataUserEn: unsigned'(CVA6ConfigDataUserEn), WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth), FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth), diff --git a/core/include/cv64a6_imafdcv_sv39_config_pkg.sv b/core/include/cv64a6_imafdcv_sv39_config_pkg.sv index c7a36e6d9b..85d25125c3 100644 --- a/core/include/cv64a6_imafdcv_sv39_config_pkg.sv +++ b/core/include/cv64a6_imafdcv_sv39_config_pkg.sv @@ -43,6 +43,9 @@ package cva6_config_pkg; localparam CVA6ConfigDcacheSetAssoc = 4; localparam CVA6ConfigDcacheLineWidth = 128; + localparam CVA6ConfigDcacheFlushOnFence = 1'b0; + localparam CVA6ConfigDcacheInvalidateOnFlush = 1'b0; + localparam CVA6ConfigDcacheIdWidth = 1; localparam CVA6ConfigMemTidWidth = 2; @@ -107,6 +110,7 @@ package cva6_config_pkg; MmuPresent: bit'(CVA6ConfigMmuPresent), RVS: bit'(1), RVU: bit'(1), + SoftwareInterruptEn: bit'(1), HaltAddress: 64'h800, ExceptionAddress: 64'h808, RASDepth: unsigned'(CVA6ConfigRASDepth), @@ -119,6 +123,7 @@ package cva6_config_pkg; PMPCfgRstVal: {64{64'h0}}, PMPAddrRstVal: {64{64'h0}}, PMPEntryReadOnly: 64'd0, + PMPNapotEn: bit'(1), NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, NrNonIdempotentRules: unsigned'(2), NonIdempotentAddrBase: 1024'({64'b0, 64'b0}), @@ -138,6 +143,8 @@ package cva6_config_pkg; DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize), DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc), DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth), + DcacheFlushOnFence: unsigned'(CVA6ConfigDcacheFlushOnFence), + DcacheInvalidateOnFlush: unsigned'(CVA6ConfigDcacheInvalidateOnFlush), DataUserEn: unsigned'(CVA6ConfigDataUserEn), WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth), FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth), diff --git a/core/include/cv64a6_mmu_config_pkg.sv b/core/include/cv64a6_mmu_config_pkg.sv index 3d902c4240..7d7df43de4 100644 --- a/core/include/cv64a6_mmu_config_pkg.sv +++ b/core/include/cv64a6_mmu_config_pkg.sv @@ -62,6 +62,7 @@ package cva6_config_pkg; MmuPresent: bit'(1), RVS: bit'(1), RVU: bit'(1), + SoftwareInterruptEn: bit'(1), HaltAddress: 64'h800, ExceptionAddress: 64'h808, RASDepth: unsigned'(2), @@ -74,6 +75,7 @@ package cva6_config_pkg; PMPCfgRstVal: {64{64'h0}}, PMPAddrRstVal: {64{64'h0}}, PMPEntryReadOnly: 64'd0, + PMPNapotEn: bit'(1), NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, NrNonIdempotentRules: unsigned'(2), NonIdempotentAddrBase: 1024'({64'b0, 64'b0}), @@ -94,6 +96,8 @@ package cva6_config_pkg; DcacheByteSize: unsigned'(32768), DcacheSetAssoc: unsigned'(8), DcacheLineWidth: unsigned'(128), + DcacheFlushOnFence: bit'(0), + DcacheInvalidateOnFlush: bit'(0), DataUserEn: unsigned'(0), WtDcacheWbufDepth: int'(2), FetchUserWidth: unsigned'(64), diff --git a/core/issue_read_operands.sv b/core/issue_read_operands.sv index 8ea332dc03..6d1b09df40 100644 --- a/core/issue_read_operands.sv +++ b/core/issue_read_operands.sv @@ -141,19 +141,22 @@ module issue_read_operands rs3_len_t operand_c_fpr; // output flipflop (ID <-> EX) fu_data_t [CVA6Cfg.NrIssuePorts-1:0] fu_data_n, fu_data_q; - logic [ CVA6Cfg.XLEN-1:0] imm_forward_rs3; - - logic [CVA6Cfg.NrIssuePorts-1:0] alu_valid_q; - logic [CVA6Cfg.NrIssuePorts-1:0] mult_valid_q; - logic [CVA6Cfg.NrIssuePorts-1:0] fpu_valid_q; - logic [ 1:0] fpu_fmt_q; - logic [ 2:0] fpu_rm_q; - logic [CVA6Cfg.NrIssuePorts-1:0] alu2_valid_q; - logic [CVA6Cfg.NrIssuePorts-1:0] lsu_valid_q; - logic [CVA6Cfg.NrIssuePorts-1:0] csr_valid_q; - logic [CVA6Cfg.NrIssuePorts-1:0] branch_valid_q; - logic [CVA6Cfg.NrIssuePorts-1:0] cvxif_valid_q; - logic [ 31:0] cvxif_off_instr_q; + logic [CVA6Cfg.VLEN-1:0] pc_n; + logic is_compressed_instr_n; + branchpredict_sbe_t branch_predict_n; + logic [CVA6Cfg.XLEN-1:0] imm_forward_rs3; + + logic [CVA6Cfg.NrIssuePorts-1:0] alu_valid_n, alu_valid_q; + logic [CVA6Cfg.NrIssuePorts-1:0] mult_valid_n, mult_valid_q; + logic [CVA6Cfg.NrIssuePorts-1:0] fpu_valid_n, fpu_valid_q; + logic [1:0] fpu_fmt_n, fpu_fmt_q; + logic [2:0] fpu_rm_n, fpu_rm_q; + logic [CVA6Cfg.NrIssuePorts-1:0] alu2_valid_n, alu2_valid_q; + logic [CVA6Cfg.NrIssuePorts-1:0] lsu_valid_n, lsu_valid_q; + logic [CVA6Cfg.NrIssuePorts-1:0] csr_valid_n, csr_valid_q; + logic [CVA6Cfg.NrIssuePorts-1:0] branch_valid_n, branch_valid_q; + logic [CVA6Cfg.NrIssuePorts-1:0] cvxif_valid_n, cvxif_valid_q; + logic [31:0] cvxif_off_instr_n, cvxif_off_instr_q; logic cvxif_instruction_valid; //fwd logic @@ -197,7 +200,7 @@ module issue_read_operands // CVXIF Signals logic cvxif_req_allowed; - logic x_transaction_rejected; + logic x_transaction_rejected, x_transaction_rejected_n; logic [OPERANDS_PER_INSTR-1:0] rs_valid; logic [OPERANDS_PER_INSTR-1:0][CVA6Cfg.XLEN-1:0] rs; @@ -225,8 +228,7 @@ module issue_read_operands .x_off_instr_i (orig_instr_i[0]), .x_trans_id_i (issue_instr_i[0].trans_id), .register_i (rs), - .rs_valid_i (rs_valid), - .cvxif_busy_o () + .rs_valid_i (rs_valid) ); if (OPERANDS_PER_INSTR == 3) begin assign rs_valid = {~stall_rs3[0], ~stall_rs2[0], ~stall_rs1[0]}; @@ -284,7 +286,7 @@ module issue_read_operands // after a multiplication was issued we can only issue another multiplication // otherwise we will get contentions on the fixed latency bus - if (mult_valid_q) begin + if (|mult_valid_q) begin fus_busy[0].alu = 1'b1; fus_busy[0].ctrl_flow = 1'b1; fus_busy[0].csr = 1'b1; @@ -310,7 +312,7 @@ module issue_read_operands fus_busy[1].cvxif = 1'b1; unique case (issue_instr_i[0].fu) - NONE: fus_busy[1].none = 1'b1; + NONE: fus_busy[1].none = 1'b1; CTRL_FLOW: begin if (CVA6Cfg.SpeculativeSb) begin // Issue speculative instruction, will be removed on BMISS @@ -350,7 +352,7 @@ module issue_read_operands // Control hazard fus_busy[1] = '1; end - MULT: fus_busy[1].mult = 1'b1; + MULT: fus_busy[1].mult = 1'b1; FPU, FPU_VEC: begin fus_busy[1].fpu = 1'b1; fus_busy[1].fpu_vec = 1'b1; @@ -360,6 +362,7 @@ module issue_read_operands fus_busy[1].store = 1'b1; end CVXIF: ; + default: ; endcase end end @@ -776,6 +779,64 @@ module issue_read_operands end end + always_comb begin + alu_valid_n = '0; + lsu_valid_n = '0; + mult_valid_n = '0; + fpu_valid_n = '0; + fpu_fmt_n = '0; + fpu_rm_n = '0; + alu2_valid_n = '0; + csr_valid_n = '0; + branch_valid_n = '0; + for (int unsigned i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin + if (!issue_instr_i[i].ex.valid && issue_instr_valid_i[i] && issue_ack_o[i]) begin + case (issue_instr_i[i].fu) + ALU: begin + if (CVA6Cfg.SuperscalarEn && !fus_busy[i].alu2) begin + alu2_valid_n[i] = 1'b1; + end else begin + alu_valid_n[i] = 1'b1; + end + end + CTRL_FLOW: begin + branch_valid_n[i] = 1'b1; + end + MULT: begin + mult_valid_n[i] = 1'b1; + end + LOAD, STORE: begin + lsu_valid_n[i] = 1'b1; + end + CSR: begin + csr_valid_n[i] = 1'b1; + end + default: begin + if (issue_instr_i[i].fu == FPU && CVA6Cfg.FpPresent) begin + fpu_valid_n[i] = 1'b1; + fpu_fmt_n = orig_instr.rftype.fmt; // fmt bits from instruction + fpu_rm_n = orig_instr.rftype.rm; // rm bits from instruction + end else if (issue_instr_i[i].fu == FPU_VEC && CVA6Cfg.FpPresent) begin + fpu_valid_n[i] = 1'b1; + fpu_fmt_n = orig_instr.rvftype.vfmt; // vfmt bits from instruction + fpu_rm_n = {2'b0, orig_instr.rvftype.repl}; // repl bit from instruction + end + end + endcase + end + end + // if we got a flush request, de-assert the valid flag, otherwise we will start this + // functional unit with the wrong inputs + if (flush_i) begin + alu_valid_n = '0; + lsu_valid_n = '0; + mult_valid_n = '0; + fpu_valid_n = '0; + alu2_valid_n = '0; + csr_valid_n = '0; + branch_valid_n = '0; + end + end // FU select, assert the correct valid out signal (in the next cycle) // This needs to be like this to make verilator happy. I know its ugly. always_ff @(posedge clk_i or negedge rst_ni) begin @@ -790,91 +851,45 @@ module issue_read_operands csr_valid_q <= '0; branch_valid_q <= '0; end else begin - alu_valid_q <= '0; - lsu_valid_q <= '0; - mult_valid_q <= '0; - fpu_valid_q <= '0; - fpu_fmt_q <= '0; - fpu_rm_q <= '0; - alu2_valid_q <= '0; - csr_valid_q <= '0; - branch_valid_q <= '0; - // Exception pass through: - // If an exception has occurred simply pass it through - // we do not want to issue this instruction + alu_valid_q <= alu_valid_n; + lsu_valid_q <= lsu_valid_n; + mult_valid_q <= mult_valid_n; + fpu_valid_q <= fpu_valid_n; + fpu_fmt_q <= fpu_fmt_n; + fpu_rm_q <= fpu_rm_n; + alu2_valid_q <= alu2_valid_n; + csr_valid_q <= csr_valid_n; + branch_valid_q <= branch_valid_n; + end + end + + if (CVA6Cfg.CvxifEn) begin + always_comb begin + cvxif_valid_n = '0; + cvxif_off_instr_n = 32'b0; for (int unsigned i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin if (!issue_instr_i[i].ex.valid && issue_instr_valid_i[i] && issue_ack_o[i]) begin case (issue_instr_i[i].fu) - ALU: begin - if (CVA6Cfg.SuperscalarEn && !fus_busy[i].alu2) begin - alu2_valid_q[i] <= 1'b1; - end else begin - alu_valid_q[i] <= 1'b1; - end - end - CTRL_FLOW: begin - branch_valid_q[i] <= 1'b1; - end - MULT: begin - mult_valid_q[i] <= 1'b1; - end - LOAD, STORE: begin - lsu_valid_q[i] <= 1'b1; - end - CSR: begin - csr_valid_q[i] <= 1'b1; - end - default: begin - if (issue_instr_i[i].fu == FPU && CVA6Cfg.FpPresent) begin - fpu_valid_q[i] <= 1'b1; - fpu_fmt_q <= orig_instr.rftype.fmt; // fmt bits from instruction - fpu_rm_q <= orig_instr.rftype.rm; // rm bits from instruction - end else if (issue_instr_i[i].fu == FPU_VEC && CVA6Cfg.FpPresent) begin - fpu_valid_q[i] <= 1'b1; - fpu_fmt_q <= orig_instr.rvftype.vfmt; // vfmt bits from instruction - fpu_rm_q <= {2'b0, orig_instr.rvftype.repl}; // repl bit from instruction - end + CVXIF: begin + cvxif_valid_n[i] = 1'b1; + cvxif_off_instr_n = orig_instr[i]; end + default: ; endcase end end - // if we got a flush request, de-assert the valid flag, otherwise we will start this - // functional unit with the wrong inputs if (flush_i) begin - alu_valid_q <= '0; - lsu_valid_q <= '0; - mult_valid_q <= '0; - fpu_valid_q <= '0; - alu2_valid_q <= '0; - csr_valid_q <= '0; - branch_valid_q <= '0; + cvxif_valid_n = '0; + cvxif_off_instr_n = 32'b0; end end - end - - if (CVA6Cfg.CvxifEn) begin always_ff @(posedge clk_i or negedge rst_ni) begin if (!rst_ni) begin cvxif_valid_q <= '0; cvxif_off_instr_q <= 32'b0; end else begin - cvxif_valid_q <= '0; - cvxif_off_instr_q <= 32'b0; - for (int unsigned i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin - if (!issue_instr_i[i].ex.valid && issue_instr_valid_i[i] && issue_ack_o[i]) begin - case (issue_instr_i[i].fu) - CVXIF: begin - cvxif_valid_q[i] <= 1'b1; - cvxif_off_instr_q <= orig_instr[i]; - end - default: ; - endcase - end - end - if (flush_i) begin - cvxif_valid_q <= '0; - cvxif_off_instr_q <= 32'b0; - end + cvxif_valid_q <= cvxif_valid_n; + cvxif_off_instr_q <= cvxif_off_instr_n; end end end @@ -1094,6 +1109,30 @@ module issue_read_operands // ---------------------- // Registers (ID <-> EX) // ---------------------- + + always_comb begin + pc_n = '0; + is_compressed_instr_n = 1'b0; + branch_predict_n = {cf_t'(0), {CVA6Cfg.VLEN{1'b0}}}; + if (CVA6Cfg.SuperscalarEn) begin + if (issue_instr_i[1].fu == CTRL_FLOW) begin + pc_n = issue_instr_i[1].pc; + is_compressed_instr_n = issue_instr_i[1].is_compressed; + branch_predict_n = issue_instr_i[1].bp; + end + end + if (issue_instr_i[0].fu == CTRL_FLOW) begin + pc_n = issue_instr_i[0].pc; + is_compressed_instr_n = issue_instr_i[0].is_compressed; + branch_predict_n = issue_instr_i[0].bp; + end + x_transaction_rejected_n = 1'b0; + if (issue_instr_i[0].fu == CVXIF) begin + x_transaction_rejected_n = x_transaction_rejected; + end + end + + always_ff @(posedge clk_i or negedge rst_ni) begin if (!rst_ni) begin fu_data_q <= '0; @@ -1109,22 +1148,10 @@ module issue_read_operands if (CVA6Cfg.RVH) begin tinst_q <= tinst_n; end - if (CVA6Cfg.SuperscalarEn) begin - if (issue_instr_i[1].fu == CTRL_FLOW) begin - pc_o <= issue_instr_i[1].pc; - is_compressed_instr_o <= issue_instr_i[1].is_compressed; - branch_predict_o <= issue_instr_i[1].bp; - end - end - if (issue_instr_i[0].fu == CTRL_FLOW) begin - pc_o <= issue_instr_i[0].pc; - is_compressed_instr_o <= issue_instr_i[0].is_compressed; - branch_predict_o <= issue_instr_i[0].bp; - end - x_transaction_rejected_o <= 1'b0; - if (issue_instr_i[0].fu == CVXIF) begin - x_transaction_rejected_o <= x_transaction_rejected; - end + pc_o <= pc_n; + is_compressed_instr_o <= is_compressed_instr_n; + branch_predict_o <= branch_predict_n; + x_transaction_rejected_o <= x_transaction_rejected_n; end end diff --git a/core/load_store_unit.sv b/core/load_store_unit.sv index 134b6a3dc1..0fec645319 100644 --- a/core/load_store_unit.sv +++ b/core/load_store_unit.sv @@ -148,14 +148,14 @@ module load_store_unit input amo_resp_t amo_resp_i, // PMP configuration - CSR_REGFILE - input riscv::pmpcfg_t [CVA6Cfg.NrPMPEntries-1:0] pmpcfg_i, + input riscv::pmpcfg_t [(CVA6Cfg.NrPMPEntries > 0 ? CVA6Cfg.NrPMPEntries-1 : 0):0] pmpcfg_i, // PMP address - CSR_REGFILE - input logic [CVA6Cfg.NrPMPEntries-1:0][CVA6Cfg.PLEN-3:0] pmpaddr_i, + input logic [(CVA6Cfg.NrPMPEntries > 0 ? CVA6Cfg.NrPMPEntries-1 : 0):0][CVA6Cfg.PLEN-3:0] pmpaddr_i, // RVFI inforamtion - RVFI output lsu_ctrl_t rvfi_lsu_ctrl_o, // RVFI information - RVFI - output [CVA6Cfg.PLEN-1:0] rvfi_mem_paddr_o + output logic [CVA6Cfg.PLEN-1:0] rvfi_mem_paddr_o ); // data is misaligned diff --git a/core/load_unit.sv b/core/load_unit.sv index 2109b08ded..0a66c51062 100644 --- a/core/load_unit.sv +++ b/core/load_unit.sv @@ -546,7 +546,6 @@ module load_unit /////////////////////////////////////////////////////// //pragma translate_off -`ifndef VERILATOR initial assert (CVA6Cfg.DcacheIdWidth >= REQ_ID_BITS) else $fatal(1, "DcacheIdWidth parameter is not wide enough to encode pending loads"); @@ -563,7 +562,6 @@ module load_unit assert property (@(posedge clk_i) disable iff (~rst_ni) ldbuf_w |-> (ldbuf_wdata.operation inside {ariane_pkg::LB, ariane_pkg::LBU}) |-> ldbuf_wdata.address_offset < 8) else $fatal(1, "invalid address offset used with {LB, LBU}"); -`endif //pragma translate_on endmodule diff --git a/core/mult.sv b/core/mult.sv index 425965e40a..ae4962ac8c 100644 --- a/core/mult.sv +++ b/core/mult.sv @@ -67,8 +67,7 @@ module mult .result_o (mul_result), .mult_valid_i (mul_valid_op), .mult_valid_o (mul_valid), - .mult_trans_id_o(mul_trans_id), - .mult_ready_o () // this unit is unconditionally ready + .mult_trans_id_o(mul_trans_id) ); // --------------------- diff --git a/core/multiplier.sv b/core/multiplier.sv index 4a46ee671a..b6c44f7f7b 100644 --- a/core/multiplier.sv +++ b/core/multiplier.sv @@ -38,8 +38,6 @@ module multiplier output logic [ CVA6Cfg.XLEN-1:0] result_o, // Mutliplier result is valid - Mult output logic mult_valid_o, - // Multiplier FU is ready - Mult - output logic mult_ready_o, // Multiplier transaction ID - Mult output logic [CVA6Cfg.TRANS_ID_BITS-1:0] mult_trans_id_o ); @@ -90,7 +88,6 @@ module multiplier // control signals assign mult_valid_o = mult_valid_q; assign mult_trans_id_o = trans_id_q; - assign mult_ready_o = 1'b1; assign mult_valid = mult_valid_i && (operation_i inside {MUL, MULH, MULHU, MULHSU, MULW, CLMUL, CLMULH, CLMULR}); diff --git a/core/pmp/src/pmp.sv b/core/pmp/src/pmp.sv index 1d2cf02651..f3498711ed 100644 --- a/core/pmp/src/pmp.sv +++ b/core/pmp/src/pmp.sv @@ -13,34 +13,29 @@ // Description: purely combinatorial PMP unit (with extraction for more complex configs such as NAPOT) module pmp #( - parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, - parameter int unsigned PLEN = 34, // rv64: 56 - parameter int unsigned PMP_LEN = 32, // rv64: 54 - parameter int unsigned NR_ENTRIES = 4 + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty ) ( // Input - input logic [PLEN-1:0] addr_i, + input logic [CVA6Cfg.PLEN-1:0] addr_i, input riscv::pmp_access_t access_type_i, input riscv::priv_lvl_t priv_lvl_i, // Configuration - input logic [NR_ENTRIES-1:0][PMP_LEN-1:0] conf_addr_i, - input riscv::pmpcfg_t [NR_ENTRIES-1:0] conf_i, + input logic [(CVA6Cfg.NrPMPEntries > 0 ? CVA6Cfg.NrPMPEntries-1 : 0):0][CVA6Cfg.PLEN-3:0] conf_addr_i, + input riscv::pmpcfg_t [(CVA6Cfg.NrPMPEntries > 0 ? CVA6Cfg.NrPMPEntries-1 : 0):0] conf_i, // Output output logic allow_o ); // if there are no PMPs we can always grant the access. - if (NR_ENTRIES > 0) begin : gen_pmp - logic [NR_ENTRIES-1:0] match; + if (CVA6Cfg.NrPMPEntries > 0) begin : gen_pmp + logic [(CVA6Cfg.NrPMPEntries > 0 ? CVA6Cfg.NrPMPEntries-1 : 0):0] match; - for (genvar i = 0; i < NR_ENTRIES; i++) begin - logic [PMP_LEN-1:0] conf_addr_prev; + for (genvar i = 0; i < CVA6Cfg.NrPMPEntries; i++) begin + logic [CVA6Cfg.PLEN-3:0] conf_addr_prev; assign conf_addr_prev = (i == 0) ? '0 : conf_addr_i[i-1]; pmp_entry #( - .CVA6Cfg(CVA6Cfg), - .PLEN (PLEN), - .PMP_LEN(PMP_LEN) + .CVA6Cfg(CVA6Cfg) ) i_pmp_entry ( .addr_i (addr_i), .conf_addr_i (conf_addr_i[i]), @@ -54,7 +49,7 @@ module pmp #( int i; allow_o = 1'b0; - for (i = 0; i < NR_ENTRIES; i++) begin + for (i = 0; i < CVA6Cfg.NrPMPEntries; i++) begin // either we are in S or U mode or the config is locked in which // case it also applies in M mode if (priv_lvl_i != riscv::PRIV_LVL_M || conf_i[i].locked) begin @@ -65,7 +60,7 @@ module pmp #( end end end - if (i == NR_ENTRIES) begin // no PMP entry matched the address + if (i == CVA6Cfg.NrPMPEntries) begin // no PMP entry matched the address // allow all accesses from M-mode for no pmp match if (priv_lvl_i == riscv::PRIV_LVL_M) allow_o = 1'b1; // disallow accesses for all other modes diff --git a/core/pmp/src/pmp_data_if.sv b/core/pmp/src/pmp_data_if.sv index 2e6c03a11f..d18149fb29 100644 --- a/core/pmp/src/pmp_data_if.sv +++ b/core/pmp/src/pmp_data_if.sv @@ -36,8 +36,8 @@ module pmp_data_if input riscv::priv_lvl_t ld_st_priv_lvl_i, input logic ld_st_v_i, // PMP - input riscv::pmpcfg_t [CVA6Cfg.NrPMPEntries-1:0] pmpcfg_i, - input logic [CVA6Cfg.NrPMPEntries-1:0][CVA6Cfg.PLEN-3:0] pmpaddr_i + input riscv::pmpcfg_t [(CVA6Cfg.NrPMPEntries > 0 ? CVA6Cfg.NrPMPEntries-1 : 0):0] pmpcfg_i, + input logic [(CVA6Cfg.NrPMPEntries > 0 ? CVA6Cfg.NrPMPEntries-1 : 0):0][CVA6Cfg.PLEN-3:0] pmpaddr_i ); // virtual address causing the exception logic [CVA6Cfg.XLEN-1:0] fetch_vaddr_xlen, lsu_vaddr_xlen; @@ -96,10 +96,7 @@ module pmp_data_if // Instruction fetch pmp #( - .CVA6Cfg (CVA6Cfg), - .PLEN (CVA6Cfg.PLEN), - .PMP_LEN (CVA6Cfg.PLEN - 2), - .NR_ENTRIES(CVA6Cfg.NrPMPEntries) + .CVA6Cfg(CVA6Cfg) ) i_pmp_if ( .addr_i (icache_areq_i.fetch_paddr), .priv_lvl_i (priv_lvl_i), @@ -144,10 +141,7 @@ module pmp_data_if // Load/store PMP check pmp #( - .CVA6Cfg (CVA6Cfg), - .PLEN (CVA6Cfg.PLEN), - .PMP_LEN (CVA6Cfg.PLEN - 2), - .NR_ENTRIES(CVA6Cfg.NrPMPEntries) + .CVA6Cfg(CVA6Cfg) ) i_pmp_data ( .addr_i (lsu_paddr_i), .priv_lvl_i (ld_st_priv_lvl_i), diff --git a/core/pmp/src/pmp_entry.sv b/core/pmp/src/pmp_entry.sv index 667ae18911..d024a9a09f 100644 --- a/core/pmp/src/pmp_entry.sv +++ b/core/pmp/src/pmp_entry.sv @@ -18,24 +18,24 @@ module pmp_entry #( parameter int unsigned PMP_LEN = 54 ) ( // Input - input logic [PLEN-1:0] addr_i, + input logic [CVA6Cfg.PLEN-1:0] addr_i, // Configuration - input logic [PMP_LEN-1:0] conf_addr_i, - input logic [PMP_LEN-1:0] conf_addr_prev_i, + input logic [CVA6Cfg.PLEN-3:0] conf_addr_i, + input logic [CVA6Cfg.PLEN-3:0] conf_addr_prev_i, input riscv::pmp_addr_mode_t conf_addr_mode_i, // Output output logic match_o ); - logic [PLEN-1:0] conf_addr_n; - logic [$clog2(PLEN)-1:0] trail_ones; - logic [PLEN-1:0] base; - logic [PLEN-1:0] mask; + logic [CVA6Cfg.PLEN-1:0] conf_addr_n; + logic [$clog2(CVA6Cfg.PLEN)-1:0] trail_ones; + logic [CVA6Cfg.PLEN-1:0] base; + logic [CVA6Cfg.PLEN-1:0] mask; int unsigned size; assign conf_addr_n = {2'b11, ~conf_addr_i}; lzc #( - .WIDTH(PLEN), + .WIDTH(CVA6Cfg.PLEN), .MODE (1'b0) ) i_lzc ( .in_i (conf_addr_n), @@ -64,13 +64,10 @@ module pmp_entry #( // synthesis translate_on end - riscv::NA4, riscv::NAPOT: begin + riscv::NAPOT: begin - if (conf_addr_mode_i == riscv::NA4) size = 2; - else begin - // use the extracted trailing ones - size = {{(32 - $clog2(PLEN)) {1'b0}}, trail_ones} + 3; - end + // use the extracted trailing ones + size = {{(32 - $clog2(CVA6Cfg.PLEN)) {1'b0}}, trail_ones} + 3; mask = '1 << size; base = ({2'b0, conf_addr_i} << 2) & mask; @@ -81,15 +78,15 @@ module pmp_entry #( assert (size >= 2); if (conf_addr_mode_i == riscv::NAPOT) begin assert (size > 2); - if (size < PMP_LEN) assert (conf_addr_i[size-3] == 0); - for (int i = 0; i < PMP_LEN; i++) begin + if (size < CVA6Cfg.PLEN - 2) assert (conf_addr_i[size-3] == 0); + for (int i = 0; i < CVA6Cfg.PLEN - 2; i++) begin if (size > 3 && i <= size - 4) begin assert (conf_addr_i[i] == 1); // check that all the rest are ones end end end - if (size < PLEN - 1) begin + if (size < CVA6Cfg.PLEN - 1) begin if (base + 2 ** size > base) begin // check for overflow if (match_o == 0) begin assert (addr_i >= base + 2 ** size || addr_i < base); diff --git a/core/store_buffer.sv b/core/store_buffer.sv index d0053bd155..7c22a97fe2 100644 --- a/core/store_buffer.sv +++ b/core/store_buffer.sv @@ -41,7 +41,7 @@ module store_buffer input logic valid_without_flush_i, // just tell if the address is valid which we are current putting and do not take any further action input logic [CVA6Cfg.PLEN-1:0] paddr_i, // physical address of store which needs to be placed in the queue - output [CVA6Cfg.PLEN-1:0] rvfi_mem_paddr_o, + output logic [CVA6Cfg.PLEN-1:0] rvfi_mem_paddr_o, input logic [CVA6Cfg.XLEN-1:0] data_i, // data which is placed in the queue input logic [(CVA6Cfg.XLEN/8)-1:0] be_i, // byte enable in input logic [1:0] data_size_i, // type of request we are making (e.g.: bytes to write) @@ -85,7 +85,6 @@ module store_buffer speculative_status_cnt = speculative_status_cnt_q; // default assignments - speculative_status_cnt_n = speculative_status_cnt_q; speculative_read_pointer_n = speculative_read_pointer_q; speculative_write_pointer_n = speculative_write_pointer_q; speculative_queue_n = speculative_queue_q; @@ -147,10 +146,11 @@ module store_buffer CVA6Cfg.DCACHE_INDEX_WIDTH-1 : CVA6Cfg.DCACHE_INDEX_WIDTH]; assign req_port_o.data_wdata = commit_queue_q[commit_read_pointer_q].data; + assign req_port_o.data_wuser = '0; assign req_port_o.data_be = commit_queue_q[commit_read_pointer_q].be; assign req_port_o.data_size = commit_queue_q[commit_read_pointer_q].data_size; - assign rvfi_mem_paddr_o = commit_queue_n[commit_read_pointer_n].address; + assign rvfi_mem_paddr_o = speculative_queue_q[speculative_read_pointer_q].address; always_comb begin : store_if automatic logic [$clog2(DEPTH_COMMIT):0] commit_status_cnt; diff --git a/core/store_unit.sv b/core/store_unit.sv index d000623a25..141763dda7 100644 --- a/core/store_unit.sv +++ b/core/store_unit.sv @@ -59,7 +59,7 @@ module store_unit // Virtual address - TO_BE_COMPLETED output logic [CVA6Cfg.VLEN-1:0] vaddr_o, // RVFI information - RVFI - output [CVA6Cfg.PLEN-1:0] rvfi_mem_paddr_o, + output logic [CVA6Cfg.PLEN-1:0] rvfi_mem_paddr_o, // Transformed trap instruction out - TO_BE_COMPLETED output logic [31:0] tinst_o, // TO_BE_COMPLETED - TO_BE_COMPLETED diff --git a/corev_apu/altera/Makefile b/corev_apu/altera/Makefile new file mode 100644 index 0000000000..f3f8983f75 --- /dev/null +++ b/corev_apu/altera/Makefile @@ -0,0 +1,197 @@ +# // Copyright (c) 2024 PlanV Technologies +# // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# // Copyright and related rights are licensed under the Solderpad Hardware +# // License, Version 0.51 (the "License"); you may not use this file except in +# // compliance with the License. You may obtain a copy of the License at +# // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +# // or agreed to in writing, software, hardware and materials distributed under +# // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# // CONDITIONS OF ANY KIND, either express or implied. See the License for the +# // specific language governing permissions and limitations under the License. + +# // Description: Makefile for Altera project +# // Author: Mustafa Karadayi, PlanV Technology +################################################################### +# Project Configuration: +# +# Specify the name of the design (project) and the Quartus II +# Settings File (.qsf) +################################################################### + +PROJECT =Example-Project##mkdigitals ask for project name +TOP_LEVEL_ENTITY = ####mkdigitals ask for the top level entity +ASSIGNMENT_FILES = $(PROJECT).qpf $(PROJECT).qsf +SOURCES_FILE = ./sourcelist.txt +# Define the output bitstream file +BITSTREAM := $(PROJECT).sof +################################################################### +# Part, Family, Boardfile DE1 or DE2 +## FAMILY COMES FROM THE CALLING MAKEFILE +## PART COMES FROM THE CALLING MAKEFILE +## BOARDFILE COMES FROM THE CALLING MAKEFILE ## mkdigitals ask if there is a board file +################################################################### + +################################################################### +# Setup your sources here +SRCS = $(shell cat $(SOURCES_FILE)) + +################################################################### +# Main Targets +# +# all: build everything +# clean: remove output files and database +# program: program your device with the compiled design +################################################################### + +all: create_project \ + write_settings \ + write_loc_constraints \ + write_io_standard_constraints \ + write_ip_files \ + write_search_paths \ + write_source_files \ + write_timing_constraints \ + generate_ips \ + sta + +clean: + $(RM) -rf *.rpt *.chg smart.log *.htm *.eqn *.pin *.sof *.pof db incremental_db *.summary *.smsg *.jdi $(ASSIGNMENT_FILES) +# Capture the Quartus version +QUARTUS_VERSION := $(shell quartus_sh --version | grep -oP 'Version \K[0-9]+\.[0-9]+') +CURRENT_DATETIME := $(shell date +"%H:%M:%S %B %d, %Y") +create_project: + @echo "Creating or regenerating $(PROJECT).qpf" + @rm -f "$(PROJECT).qpf" + @touch "$(PROJECT).qpf" + @echo "QUARTUS_VERSION = \"$(QUARTUS_VERSION)\"" >> "$(PROJECT).qpf" + @echo "DATE = \"$(CURRENT_DATETIME)\"" >> "$(PROJECT).qpf" + @echo "PROJECT_REVISION = \"$(PROJECT)\"" >> "$(PROJECT).qpf" + + @echo "Creating or regenerating $(PROJECT).qsf" + @rm -f "$(PROJECT).qsf" + @touch "$(PROJECT).qsf" + $(QSYS_PATH)qsys-script --script=ip/interconnect.tcl + $(QSYS_PATH)qsys-generate interconnect.qsys --quartus_project=ip/interconnect --synthesis + rm -f interconnect/*.v + rm -f interconnect/*.vhd + rm -f interconnect/synth/*.v + +write_settings: + @echo "Reading from settings.csv and writing to $(PROJECT).qsf with modifications" + @while IFS= read -r line; do \ + echo "set_global_assignment -name $$line" >> "$(PROJECT).qsf"; \ + done < settings.csv + +write_loc_constraints: + @echo "Reading from loc_constraints.csv and writing to $(PROJECT).qsf with modifications" + @while IFS= read -r line; do \ + echo "set_location_assignment $$line" >> "$(PROJECT).qsf"; \ + done < loc_constraints.csv + +write_io_standard_constraints: + @echo "Reading from io_standard_constraints.csv and writing to $(PROJECT).qsf with modifications" + @while IFS= read -r line; do \ + echo "set_instance_assignment -name $$line" >> "$(PROJECT).qsf"; \ + done < io_standard_constraints.csv + +write_ip_files: + @echo "Reading from ip_files.csv and writing to $(PROJECT).qsf with modifications" + @while IFS= read -r line; do \ + echo "set_global_assignment -name IP_FILE $$line" >> "$(PROJECT).qsf"; \ + done < ip_files.csv + +write_search_paths: + @echo "Reading from search_paths.csv and writing to $(PROJECT).qsf with modifications" + @while IFS= read -r line; do \ + echo "set_global_assignment -name SEARCH_PATH $$line" >> "$(PROJECT).qsf"; \ + done < search_paths.csv + +write_source_files: + @find ./interconnect -type f -name "*.v" -o -name "*.sv" -o -name "*.svh" >> $(SOURCES_FILE) + @echo $(var) + @echo >> $(SOURCES_FILE) + @echo "Reading from $(SOURCES_FILE) and writing to $(PROJECT).qsf with modifications" + @while IFS= read -r line; do \ + for word in $$line; do \ + if echo "$$word" | grep -q "\.vhd$$"; then \ + echo "set_global_assignment -name VHDL_FILE $$word" >> "$(PROJECT).qsf"; \ + elif echo "$$word" | grep -q "\.v$$"; then \ + echo "set_global_assignment -name VERILOG_FILE $$word" >> "$(PROJECT).qsf"; \ + elif echo "$$word" | grep -q "\.sv$$"; then \ + echo "set_global_assignment -name SYSTEMVERILOG_FILE $$word" >> "$(PROJECT).qsf"; \ + elif echo "$$word" | grep -q "\.svh$$"; then \ + echo "set_global_assignment -name SYSTEMVERILOG_FILE $$word" >> "$(PROJECT).qsf"; \ + else \ + echo "set_global_assignment -name SOURCE_FILE $$word" >> "$(PROJECT).qsf"; \ + fi; \ + done; \ + done < $(SOURCES_FILE) + +write_timing_constraints: + @echo "Generating constraints file list" + find ./constraints -type f -name "*.sdc" -exec realpath {} \; | sed 's|^|set_global_assignment -name SDC_FILE |' >> "$(PROJECT).qsf" + +generate_ips: + $(QSYS_PATH)qsys-script --script=ip/test_mm_ccb_0.tcl + $(QSYS_PATH)qsys-script --script=ip/cva6_intel_jtag_uart_0.tcl + $(QSYS_PATH)qsys-script --script=ip/ed_synth_emif_fm_0.tcl + $(QSYS_PATH)qsys-script --script=ip/emif_cal.tcl + $(QSYS_PATH)qsys-script --script=ip/iddr_intel.tcl + $(QSYS_PATH)qsys-script --script=ip/io_pll.tcl + $(QSYS_PATH)qsys-script --script=ip/iobuf.tcl + $(QSYS_PATH)qsys-script --script=ip/oddr_intel.tcl + $(QSYS_PATH)qsys-script --script=ip/vJTAG.tcl + $(QUARTUS_PATH)quartus_ipgenerate --generate_project_ip_files $(PROJECT) + +map: + @echo "Running Quartus Map" + $(QUARTUS_PATH)quartus_syn $(PROJECT) + +fit: map + @echo "Running Quartus Fit" + $(QUARTUS_PATH)quartus_fit $(PROJECT) + +asm: fit + @echo "Running Quartus Assembly" + $(QUARTUS_PATH)quartus_asm $(PROJECT) + +sta: asm + @echo "Running Quartus Timing Analysis" + $(QUARTUS_PATH)quartus_sta $(PROJECT) --do_report_timing + +clean: + @echo "Cleaning project files" + rm -f $(PROJECT).qsf $(PROJECT).qpf $(PROJECT).map.rpt $(PROJECT).fit.rpt $(PROJECT).asm.rpt $(PROJECT).sta.rpt + rm -f interconnect.qsys* + rm -f *.backup + rm -f *.hex + rm -f *.txt + rm -f *.ip + rm -f ip/board.info + rm -f ip/*.qpf + rm -f ip/*.qsf + rm -rf ip/dni + rm -rf ip/.qsys_edit + rm -rf ip/qdb + rm -rf output_files + rm -rf db incremental_db + rm -rf qdb + rm -rf tmp-clearbox + rm -rf intel + rm -rf dni + rm -rf interconnect + rm -rf ip/interconnect + rm -rf cva6_intel_jtag_uart_0 + rm -rf ed_synth_emif_fm_0 + rm -rf emif_cal + rm -rf iddr_intel + rm -rf oddr_intel + rm -rf test_mm_ccb_0 + rm -rf vJTAG + rm -rf interconnect + rm -rf io_pll + rm -rf iobuf + + $(QUARTUS_PATH)quartus_ipgenerate --clean $(PROJECT) + +.PHONY: all write_search_paths write_source_files map fit asm sta clean \ No newline at end of file diff --git a/corev_apu/altera/altera.cfg b/corev_apu/altera/altera.cfg new file mode 100644 index 0000000000..327e047c04 --- /dev/null +++ b/corev_apu/altera/altera.cfg @@ -0,0 +1,47 @@ +# * Copyright 2024 Thales AVS +# * Copyright 2024 PlanV Technologies +# * Copyright and related rights are licensed under the Solderpad Hardware +# * License, Version 0.51 (the “License”); you may not use this file except in +# * compliance with the License. You may obtain a copy of the License at +# * http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +# * or agreed to in writing, software, hardware and materials distributed under +# * this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR +# * CONDITIONS OF ANY KIND, either express or implied. See the License for the +# * specific language governing permissions and limitations under the License. +# * +# * Author: Nicolas Levasseur, Thales AVS +# * Additional contributions by Angela Gonzalez, PlanV Technologies +# * Date: 8.11.2024 +# * Description: Configuration file for openocd connection +# * +# */ + +adapter driver aji_client + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME agilex7 +} + +jtag newtap $_CHIPNAME.fpga tap -irlen 10 -expected-id 0xC341A0DD +#0xC341A0DD + +# VJTAG ID : +# ------------------------------------------------------- +# | 31 - 27 | 26 - 19 | 18 - 8 | 7 - 0 | +# |-----------------------------------------------------| +# | Node Version | Node ID | Node mfg_id | Node_inst_id | +# ------------------------------------------------------- +# Info : node 0 idcode=00406E00 position_n=0 CVA6 core #0 + +vjtag create $_CHIPNAME.fpga.tap.cva6.0 -chain-position $_CHIPNAME.fpga.tap -expected-id 0x00406E00 +target create $_CHIPNAME.cva6.0 riscv -chain-position $_CHIPNAME.fpga.tap.cva6.0 -coreid 0 + +scan_chain + +init + +halt +echo "Ready for Remote Connections" + diff --git a/corev_apu/altera/constraints/SDC1.sdc b/corev_apu/altera/constraints/SDC1.sdc new file mode 100644 index 0000000000..c349fb30b9 --- /dev/null +++ b/corev_apu/altera/constraints/SDC1.sdc @@ -0,0 +1,7 @@ +set_false_path -from [get_clocks {inst_ddr4|emif_fm_0_core_usr_clk}] -to [get_clocks {clocks|iopll_0_outclk0}] +set_false_path -from [get_clocks {clocks|iopll_0_outclk0}] -to [get_clocks {inst_ddr4|emif_fm_0_core_usr_clk}] +set_false_path -from [get_clocks {clocks|iopll_0_outclk0}] -to [get_clocks {clocks|iopll_0_refclk}] +set_false_path -from [get_clocks {clocks|iopll_0_refclk}] -to [get_clocks {clocks|iopll_0_outclk0}] +set_disable_timing [get_ports led[*]] +set_false_path -hold -through [get_pins -hierarchical "*async*"] +set_max_delay -through [get_pins -hierarchical "*async*"] 5.000 diff --git a/corev_apu/altera/io_standard_constraints.csv b/corev_apu/altera/io_standard_constraints.csv new file mode 100644 index 0000000000..e4fbc9e30e --- /dev/null +++ b/corev_apu/altera/io_standard_constraints.csv @@ -0,0 +1,7 @@ +IO_STANDARD "1.2 V" -to cpu_resetn -entity cva6_altera +IO_STANDARD "TRUE DIFFERENTIAL SIGNALING" -to pll_ref_clk_p -entity cva6_altera +IO_STANDARD "TRUE DIFFERENTIAL SIGNALING" -to clk_ddr4_ch0_p -entity cva6_altera +IO_STANDARD "1.2 V" -to led[3] -entity cva6_altera +IO_STANDARD "1.2 V" -to led[2] -entity cva6_altera +IO_STANDARD "1.2 V" -to led[1] -entity cva6_altera +IO_STANDARD "1.2 V" -to led[0] -entity cva6_altera diff --git a/corev_apu/altera/ip/cva6_intel_jtag_uart_0.tcl b/corev_apu/altera/ip/cva6_intel_jtag_uart_0.tcl new file mode 100644 index 0000000000..422fc7451a --- /dev/null +++ b/corev_apu/altera/ip/cva6_intel_jtag_uart_0.tcl @@ -0,0 +1,70 @@ +# Quartus Pro License required to use this file +package require -exact qsys 24.1 + +# create the system "cva6_intel_jtag_uart_0" +proc do_create_cva6_intel_jtag_uart_0 {} { + # create the system + create_system cva6_intel_jtag_uart_0 + set_project_property BOARD {default} + set_project_property DEVICE {AGFB014R24B2E2V} + set_project_property DEVICE_FAMILY {Agilex 7} + set_project_property HIDE_FROM_IP_CATALOG {false} + set_use_testbench_naming_pattern 0 {} + + # add HDL parameters + + # add the components + add_instance jtag_uart_0 altera_avalon_jtag_uart 19.2.4 + set_instance_parameter_value jtag_uart_0 {allowMultipleConnections} {0} + set_instance_parameter_value jtag_uart_0 {hubInstanceID} {0} + set_instance_parameter_value jtag_uart_0 {readBufferDepth} {64} + set_instance_parameter_value jtag_uart_0 {readIRQThreshold} {8} + set_instance_parameter_value jtag_uart_0 {simInputCharacterStream} {} + set_instance_parameter_value jtag_uart_0 {simInteractiveOptions} {NO_INTERACTIVE_WINDOWS} + set_instance_parameter_value jtag_uart_0 {useRegistersForReadBuffer} {0} + set_instance_parameter_value jtag_uart_0 {useRegistersForWriteBuffer} {0} + set_instance_parameter_value jtag_uart_0 {useRelativePathForSimFile} {0} + set_instance_parameter_value jtag_uart_0 {writeBufferDepth} {64} + set_instance_parameter_value jtag_uart_0 {writeIRQThreshold} {8} + set_instance_property jtag_uart_0 AUTO_EXPORT true + + # add wirelevel expressions + + # preserve ports for debug + + # add the exports + set_interface_property clk EXPORT_OF jtag_uart_0.clk + set_interface_property reset EXPORT_OF jtag_uart_0.reset + set_interface_property avalon_jtag_slave EXPORT_OF jtag_uart_0.avalon_jtag_slave + set_interface_property irq EXPORT_OF jtag_uart_0.irq + + # set values for exposed HDL parameters + + # set the the module properties + set_module_property BONUS_DATA { + + + + + +} + set_module_property FILE {cva6_intel_jtag_uart_0.ip} + set_module_property GENERATION_ID {0x00000000} + set_module_property NAME {cva6_intel_jtag_uart_0} + + # save the system + sync_sysinfo_parameters + save_system cva6_intel_jtag_uart_0 +} + +proc do_set_exported_interface_sysinfo_parameters {} { + load_system cva6_intel_jtag_uart_0.ip + set_exported_interface_sysinfo_parameter_value clk clock_rate {300000000} + save_system cva6_intel_jtag_uart_0.ip +} + +# create all the systems, from bottom up +do_create_cva6_intel_jtag_uart_0 + +# set system info parameters on exported interface, from bottom up +do_set_exported_interface_sysinfo_parameters diff --git a/corev_apu/altera/ip/ed_synth_emif_fm_0.tcl b/corev_apu/altera/ip/ed_synth_emif_fm_0.tcl new file mode 100644 index 0000000000..20beb1362a --- /dev/null +++ b/corev_apu/altera/ip/ed_synth_emif_fm_0.tcl @@ -0,0 +1,1640 @@ +# Quartus Pro License required to use this file +package require -exact qsys 24.1 + +# create the system "ed_synth_emif_fm_0" +proc do_create_ed_synth_emif_fm_0 {} { + # create the system + create_system ed_synth_emif_fm_0 + set_project_property BOARD {default} + set_project_property DEVICE {AGFB014R24B2E2V} + set_project_property DEVICE_FAMILY {Agilex 7} + set_project_property HIDE_FROM_IP_CATALOG {false} + set_use_testbench_naming_pattern 0 {} + + # add HDL parameters + + # add the components + add_instance emif_fm_0 altera_emif_fm 2.7.4 + set_instance_parameter_value emif_fm_0 {BOARD_DDR3_AC_TO_CK_SKEW_NS} {0.0} + set_instance_parameter_value emif_fm_0 {BOARD_DDR3_BRD_SKEW_WITHIN_AC_NS} {0.02} + set_instance_parameter_value emif_fm_0 {BOARD_DDR3_BRD_SKEW_WITHIN_DQS_NS} {0.02} + set_instance_parameter_value emif_fm_0 {BOARD_DDR3_DQS_TO_CK_SKEW_NS} {0.02} + set_instance_parameter_value emif_fm_0 {BOARD_DDR3_IS_SKEW_WITHIN_AC_DESKEWED} {1} + set_instance_parameter_value emif_fm_0 {BOARD_DDR3_IS_SKEW_WITHIN_DQS_DESKEWED} {0} + set_instance_parameter_value emif_fm_0 {BOARD_DDR3_MAX_CK_DELAY_NS} {0.6} + set_instance_parameter_value emif_fm_0 {BOARD_DDR3_MAX_DQS_DELAY_NS} {0.6} + set_instance_parameter_value emif_fm_0 {BOARD_DDR3_PKG_BRD_SKEW_WITHIN_AC_NS} {0.02} + set_instance_parameter_value emif_fm_0 {BOARD_DDR3_PKG_BRD_SKEW_WITHIN_DQS_NS} {0.02} + set_instance_parameter_value emif_fm_0 {BOARD_DDR3_SKEW_BETWEEN_DIMMS_NS} {0.05} + set_instance_parameter_value emif_fm_0 {BOARD_DDR3_SKEW_BETWEEN_DQS_NS} {0.02} + set_instance_parameter_value emif_fm_0 {BOARD_DDR3_USER_AC_ISI_NS} {0.0} + set_instance_parameter_value emif_fm_0 {BOARD_DDR3_USER_AC_SLEW_RATE} {2.0} + set_instance_parameter_value emif_fm_0 {BOARD_DDR3_USER_CK_SLEW_RATE} {4.0} + set_instance_parameter_value emif_fm_0 {BOARD_DDR3_USER_RCLK_ISI_NS} {0.0} + set_instance_parameter_value emif_fm_0 {BOARD_DDR3_USER_RCLK_SLEW_RATE} {5.0} + set_instance_parameter_value emif_fm_0 {BOARD_DDR3_USER_RDATA_ISI_NS} {0.0} + set_instance_parameter_value emif_fm_0 {BOARD_DDR3_USER_RDATA_SLEW_RATE} {2.5} + set_instance_parameter_value emif_fm_0 {BOARD_DDR3_USER_WCLK_ISI_NS} {0.0} + set_instance_parameter_value emif_fm_0 {BOARD_DDR3_USER_WCLK_SLEW_RATE} {4.0} + set_instance_parameter_value emif_fm_0 {BOARD_DDR3_USER_WDATA_ISI_NS} {0.0} + set_instance_parameter_value emif_fm_0 {BOARD_DDR3_USER_WDATA_SLEW_RATE} {2.0} + set_instance_parameter_value emif_fm_0 {BOARD_DDR3_USE_DEFAULT_ISI_VALUES} {1} + set_instance_parameter_value emif_fm_0 {BOARD_DDR3_USE_DEFAULT_SLEW_RATES} {1} + set_instance_parameter_value emif_fm_0 {BOARD_DDR4_AC_TO_CK_SKEW_NS} {0.0} + set_instance_parameter_value emif_fm_0 {BOARD_DDR4_BRD_SKEW_WITHIN_AC_NS} {0.02} + set_instance_parameter_value emif_fm_0 {BOARD_DDR4_BRD_SKEW_WITHIN_DQS_NS} {0.02} + set_instance_parameter_value emif_fm_0 {BOARD_DDR4_DQS_TO_CK_SKEW_NS} {0.02} + set_instance_parameter_value emif_fm_0 {BOARD_DDR4_IS_SKEW_WITHIN_AC_DESKEWED} {0} + set_instance_parameter_value emif_fm_0 {BOARD_DDR4_IS_SKEW_WITHIN_DQS_DESKEWED} {1} + set_instance_parameter_value emif_fm_0 {BOARD_DDR4_MAX_CK_DELAY_NS} {0.6} + set_instance_parameter_value emif_fm_0 {BOARD_DDR4_MAX_DQS_DELAY_NS} {0.6} + set_instance_parameter_value emif_fm_0 {BOARD_DDR4_PKG_BRD_SKEW_WITHIN_AC_NS} {0.02} + set_instance_parameter_value emif_fm_0 {BOARD_DDR4_PKG_BRD_SKEW_WITHIN_DQS_NS} {0.02} + set_instance_parameter_value emif_fm_0 {BOARD_DDR4_SKEW_BETWEEN_DIMMS_NS} {0.05} + set_instance_parameter_value emif_fm_0 {BOARD_DDR4_SKEW_BETWEEN_DQS_NS} {0.02} + set_instance_parameter_value emif_fm_0 {BOARD_DDR4_USER_AC_ISI_NS} {0.0} + set_instance_parameter_value emif_fm_0 {BOARD_DDR4_USER_AC_SLEW_RATE} {2.0} + set_instance_parameter_value emif_fm_0 {BOARD_DDR4_USER_CK_SLEW_RATE} {4.0} + set_instance_parameter_value emif_fm_0 {BOARD_DDR4_USER_RCLK_ISI_NS} {0.0} + set_instance_parameter_value emif_fm_0 {BOARD_DDR4_USER_RCLK_SLEW_RATE} {8.0} + set_instance_parameter_value emif_fm_0 {BOARD_DDR4_USER_RDATA_ISI_NS} {0.0} + set_instance_parameter_value emif_fm_0 {BOARD_DDR4_USER_RDATA_SLEW_RATE} {4.0} + set_instance_parameter_value emif_fm_0 {BOARD_DDR4_USER_WCLK_ISI_NS} {0.0} + set_instance_parameter_value emif_fm_0 {BOARD_DDR4_USER_WCLK_SLEW_RATE} {4.0} + set_instance_parameter_value emif_fm_0 {BOARD_DDR4_USER_WDATA_ISI_NS} {0.0} + set_instance_parameter_value emif_fm_0 {BOARD_DDR4_USER_WDATA_SLEW_RATE} {2.0} + set_instance_parameter_value emif_fm_0 {BOARD_DDR4_USE_DEFAULT_ISI_VALUES} {1} + set_instance_parameter_value emif_fm_0 {BOARD_DDR4_USE_DEFAULT_SLEW_RATES} {1} + set_instance_parameter_value emif_fm_0 {BOARD_DDRT_AC_TO_CK_SKEW_NS} {0.0} + set_instance_parameter_value emif_fm_0 {BOARD_DDRT_BRD_SKEW_WITHIN_AC_NS} {0.02} + set_instance_parameter_value emif_fm_0 {BOARD_DDRT_BRD_SKEW_WITHIN_DQS_NS} {0.02} + set_instance_parameter_value emif_fm_0 {BOARD_DDRT_DQS_TO_CK_SKEW_NS} {0.02} + set_instance_parameter_value emif_fm_0 {BOARD_DDRT_IS_SKEW_WITHIN_AC_DESKEWED} {0} + set_instance_parameter_value emif_fm_0 {BOARD_DDRT_IS_SKEW_WITHIN_DQS_DESKEWED} {1} + set_instance_parameter_value emif_fm_0 {BOARD_DDRT_MAX_CK_DELAY_NS} {0.6} + set_instance_parameter_value emif_fm_0 {BOARD_DDRT_MAX_DQS_DELAY_NS} {0.6} + set_instance_parameter_value emif_fm_0 {BOARD_DDRT_PKG_BRD_SKEW_WITHIN_AC_NS} {0.02} + set_instance_parameter_value emif_fm_0 {BOARD_DDRT_PKG_BRD_SKEW_WITHIN_DQS_NS} {0.02} + set_instance_parameter_value emif_fm_0 {BOARD_DDRT_SKEW_BETWEEN_DIMMS_NS} {0.05} + set_instance_parameter_value emif_fm_0 {BOARD_DDRT_SKEW_BETWEEN_DQS_NS} {0.02} + set_instance_parameter_value emif_fm_0 {BOARD_DDRT_USER_AC_ISI_NS} {0.0} + set_instance_parameter_value emif_fm_0 {BOARD_DDRT_USER_AC_SLEW_RATE} {2.0} + set_instance_parameter_value emif_fm_0 {BOARD_DDRT_USER_CK_SLEW_RATE} {4.0} + set_instance_parameter_value emif_fm_0 {BOARD_DDRT_USER_RCLK_ISI_NS} {0.0} + set_instance_parameter_value emif_fm_0 {BOARD_DDRT_USER_RCLK_SLEW_RATE} {8.0} + set_instance_parameter_value emif_fm_0 {BOARD_DDRT_USER_RDATA_ISI_NS} {0.0} + set_instance_parameter_value emif_fm_0 {BOARD_DDRT_USER_RDATA_SLEW_RATE} {4.0} + set_instance_parameter_value emif_fm_0 {BOARD_DDRT_USER_WCLK_ISI_NS} {0.0} + set_instance_parameter_value emif_fm_0 {BOARD_DDRT_USER_WCLK_SLEW_RATE} {4.0} + set_instance_parameter_value emif_fm_0 {BOARD_DDRT_USER_WDATA_ISI_NS} {0.0} + set_instance_parameter_value emif_fm_0 {BOARD_DDRT_USER_WDATA_SLEW_RATE} {2.0} + set_instance_parameter_value emif_fm_0 {BOARD_DDRT_USE_DEFAULT_ISI_VALUES} {1} + set_instance_parameter_value emif_fm_0 {BOARD_DDRT_USE_DEFAULT_SLEW_RATES} {1} + set_instance_parameter_value emif_fm_0 {BOARD_LPDDR3_AC_TO_CK_SKEW_NS} {0.0} + set_instance_parameter_value emif_fm_0 {BOARD_LPDDR3_BRD_SKEW_WITHIN_AC_NS} {0.02} + set_instance_parameter_value emif_fm_0 {BOARD_LPDDR3_BRD_SKEW_WITHIN_DQS_NS} {0.02} + set_instance_parameter_value emif_fm_0 {BOARD_LPDDR3_DQS_TO_CK_SKEW_NS} {0.02} + set_instance_parameter_value emif_fm_0 {BOARD_LPDDR3_IS_SKEW_WITHIN_AC_DESKEWED} {1} + set_instance_parameter_value emif_fm_0 {BOARD_LPDDR3_IS_SKEW_WITHIN_DQS_DESKEWED} {0} + set_instance_parameter_value emif_fm_0 {BOARD_LPDDR3_MAX_CK_DELAY_NS} {0.6} + set_instance_parameter_value emif_fm_0 {BOARD_LPDDR3_MAX_DQS_DELAY_NS} {0.6} + set_instance_parameter_value emif_fm_0 {BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_AC_NS} {0.02} + set_instance_parameter_value emif_fm_0 {BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_DQS_NS} {0.02} + set_instance_parameter_value emif_fm_0 {BOARD_LPDDR3_SKEW_BETWEEN_DIMMS_NS} {0.05} + set_instance_parameter_value emif_fm_0 {BOARD_LPDDR3_SKEW_BETWEEN_DQS_NS} {0.02} + set_instance_parameter_value emif_fm_0 {BOARD_LPDDR3_USER_AC_ISI_NS} {0.0} + set_instance_parameter_value emif_fm_0 {BOARD_LPDDR3_USER_AC_SLEW_RATE} {2.0} + set_instance_parameter_value emif_fm_0 {BOARD_LPDDR3_USER_CK_SLEW_RATE} {4.0} + set_instance_parameter_value emif_fm_0 {BOARD_LPDDR3_USER_RCLK_ISI_NS} {0.0} + set_instance_parameter_value emif_fm_0 {BOARD_LPDDR3_USER_RCLK_SLEW_RATE} {4.0} + set_instance_parameter_value emif_fm_0 {BOARD_LPDDR3_USER_RDATA_ISI_NS} {0.0} + set_instance_parameter_value emif_fm_0 {BOARD_LPDDR3_USER_RDATA_SLEW_RATE} {2.0} + set_instance_parameter_value emif_fm_0 {BOARD_LPDDR3_USER_WCLK_ISI_NS} {0.0} + set_instance_parameter_value emif_fm_0 {BOARD_LPDDR3_USER_WCLK_SLEW_RATE} {4.0} + set_instance_parameter_value emif_fm_0 {BOARD_LPDDR3_USER_WDATA_ISI_NS} {0.0} + set_instance_parameter_value emif_fm_0 {BOARD_LPDDR3_USER_WDATA_SLEW_RATE} {2.0} + set_instance_parameter_value emif_fm_0 {BOARD_LPDDR3_USE_DEFAULT_ISI_VALUES} {1} + set_instance_parameter_value emif_fm_0 {BOARD_LPDDR3_USE_DEFAULT_SLEW_RATES} {1} + set_instance_parameter_value emif_fm_0 {BOARD_QDR2_AC_TO_K_SKEW_NS} {0.0} + set_instance_parameter_value emif_fm_0 {BOARD_QDR2_BRD_SKEW_WITHIN_AC_NS} {0.02} + set_instance_parameter_value emif_fm_0 {BOARD_QDR2_BRD_SKEW_WITHIN_D_NS} {0.02} + set_instance_parameter_value emif_fm_0 {BOARD_QDR2_BRD_SKEW_WITHIN_Q_NS} {0.02} + set_instance_parameter_value emif_fm_0 {BOARD_QDR2_IS_SKEW_WITHIN_AC_DESKEWED} {1} + set_instance_parameter_value emif_fm_0 {BOARD_QDR2_IS_SKEW_WITHIN_D_DESKEWED} {0} + set_instance_parameter_value emif_fm_0 {BOARD_QDR2_IS_SKEW_WITHIN_Q_DESKEWED} {0} + set_instance_parameter_value emif_fm_0 {BOARD_QDR2_MAX_K_DELAY_NS} {0.6} + set_instance_parameter_value emif_fm_0 {BOARD_QDR2_PKG_BRD_SKEW_WITHIN_AC_NS} {0.02} + set_instance_parameter_value emif_fm_0 {BOARD_QDR2_PKG_BRD_SKEW_WITHIN_D_NS} {0.02} + set_instance_parameter_value emif_fm_0 {BOARD_QDR2_PKG_BRD_SKEW_WITHIN_Q_NS} {0.02} + set_instance_parameter_value emif_fm_0 {BOARD_QDR2_USER_AC_ISI_NS} {0.0} + set_instance_parameter_value emif_fm_0 {BOARD_QDR2_USER_AC_SLEW_RATE} {2.0} + set_instance_parameter_value emif_fm_0 {BOARD_QDR2_USER_K_SLEW_RATE} {4.0} + set_instance_parameter_value emif_fm_0 {BOARD_QDR2_USER_RCLK_ISI_NS} {0.0} + set_instance_parameter_value emif_fm_0 {BOARD_QDR2_USER_RCLK_SLEW_RATE} {4.0} + set_instance_parameter_value emif_fm_0 {BOARD_QDR2_USER_RDATA_ISI_NS} {0.0} + set_instance_parameter_value emif_fm_0 {BOARD_QDR2_USER_RDATA_SLEW_RATE} {2.0} + set_instance_parameter_value emif_fm_0 {BOARD_QDR2_USER_WCLK_ISI_NS} {0.0} + set_instance_parameter_value emif_fm_0 {BOARD_QDR2_USER_WDATA_ISI_NS} {0.0} + set_instance_parameter_value emif_fm_0 {BOARD_QDR2_USER_WDATA_SLEW_RATE} {2.0} + set_instance_parameter_value emif_fm_0 {BOARD_QDR2_USE_DEFAULT_ISI_VALUES} {1} + set_instance_parameter_value emif_fm_0 {BOARD_QDR2_USE_DEFAULT_SLEW_RATES} {1} + set_instance_parameter_value emif_fm_0 {BOARD_QDR4_AC_TO_CK_SKEW_NS} {0.0} + set_instance_parameter_value emif_fm_0 {BOARD_QDR4_BRD_SKEW_WITHIN_AC_NS} {0.02} + set_instance_parameter_value emif_fm_0 {BOARD_QDR4_BRD_SKEW_WITHIN_QK_NS} {0.02} + set_instance_parameter_value emif_fm_0 {BOARD_QDR4_DK_TO_CK_SKEW_NS} {-0.02} + set_instance_parameter_value emif_fm_0 {BOARD_QDR4_IS_SKEW_WITHIN_AC_DESKEWED} {1} + set_instance_parameter_value emif_fm_0 {BOARD_QDR4_IS_SKEW_WITHIN_QK_DESKEWED} {1} + set_instance_parameter_value emif_fm_0 {BOARD_QDR4_MAX_CK_DELAY_NS} {0.6} + set_instance_parameter_value emif_fm_0 {BOARD_QDR4_MAX_DK_DELAY_NS} {0.6} + set_instance_parameter_value emif_fm_0 {BOARD_QDR4_PKG_BRD_SKEW_WITHIN_AC_NS} {0.02} + set_instance_parameter_value emif_fm_0 {BOARD_QDR4_PKG_BRD_SKEW_WITHIN_QK_NS} {0.02} + set_instance_parameter_value emif_fm_0 {BOARD_QDR4_SKEW_BETWEEN_DIMMS_NS} {0.05} + set_instance_parameter_value emif_fm_0 {BOARD_QDR4_SKEW_BETWEEN_DK_NS} {0.02} + set_instance_parameter_value emif_fm_0 {BOARD_QDR4_USER_AC_ISI_NS} {0.0} + set_instance_parameter_value emif_fm_0 {BOARD_QDR4_USER_AC_SLEW_RATE} {2.0} + set_instance_parameter_value emif_fm_0 {BOARD_QDR4_USER_CK_SLEW_RATE} {4.0} + set_instance_parameter_value emif_fm_0 {BOARD_QDR4_USER_RCLK_ISI_NS} {0.0} + set_instance_parameter_value emif_fm_0 {BOARD_QDR4_USER_RCLK_SLEW_RATE} {5.0} + set_instance_parameter_value emif_fm_0 {BOARD_QDR4_USER_RDATA_ISI_NS} {0.0} + set_instance_parameter_value emif_fm_0 {BOARD_QDR4_USER_RDATA_SLEW_RATE} {2.5} + set_instance_parameter_value emif_fm_0 {BOARD_QDR4_USER_WCLK_ISI_NS} {0.0} + set_instance_parameter_value emif_fm_0 {BOARD_QDR4_USER_WCLK_SLEW_RATE} {4.0} + set_instance_parameter_value emif_fm_0 {BOARD_QDR4_USER_WDATA_ISI_NS} {0.0} + set_instance_parameter_value emif_fm_0 {BOARD_QDR4_USER_WDATA_SLEW_RATE} {2.0} + set_instance_parameter_value emif_fm_0 {BOARD_QDR4_USE_DEFAULT_ISI_VALUES} {1} + set_instance_parameter_value emif_fm_0 {BOARD_QDR4_USE_DEFAULT_SLEW_RATES} {1} + set_instance_parameter_value emif_fm_0 {BOARD_RLD3_AC_TO_CK_SKEW_NS} {0.0} + set_instance_parameter_value emif_fm_0 {BOARD_RLD3_BRD_SKEW_WITHIN_AC_NS} {0.02} + set_instance_parameter_value emif_fm_0 {BOARD_RLD3_BRD_SKEW_WITHIN_QK_NS} {0.02} + set_instance_parameter_value emif_fm_0 {BOARD_RLD3_DK_TO_CK_SKEW_NS} {-0.02} + set_instance_parameter_value emif_fm_0 {BOARD_RLD3_IS_SKEW_WITHIN_AC_DESKEWED} {1} + set_instance_parameter_value emif_fm_0 {BOARD_RLD3_IS_SKEW_WITHIN_QK_DESKEWED} {0} + set_instance_parameter_value emif_fm_0 {BOARD_RLD3_MAX_CK_DELAY_NS} {0.6} + set_instance_parameter_value emif_fm_0 {BOARD_RLD3_MAX_DK_DELAY_NS} {0.6} + set_instance_parameter_value emif_fm_0 {BOARD_RLD3_PKG_BRD_SKEW_WITHIN_AC_NS} {0.02} + set_instance_parameter_value emif_fm_0 {BOARD_RLD3_PKG_BRD_SKEW_WITHIN_QK_NS} {0.02} + set_instance_parameter_value emif_fm_0 {BOARD_RLD3_SKEW_BETWEEN_DIMMS_NS} {0.05} + set_instance_parameter_value emif_fm_0 {BOARD_RLD3_SKEW_BETWEEN_DK_NS} {0.02} + set_instance_parameter_value emif_fm_0 {BOARD_RLD3_USER_AC_ISI_NS} {0.0} + set_instance_parameter_value emif_fm_0 {BOARD_RLD3_USER_AC_SLEW_RATE} {2.0} + set_instance_parameter_value emif_fm_0 {BOARD_RLD3_USER_CK_SLEW_RATE} {4.0} + set_instance_parameter_value emif_fm_0 {BOARD_RLD3_USER_RCLK_ISI_NS} {0.0} + set_instance_parameter_value emif_fm_0 {BOARD_RLD3_USER_RCLK_SLEW_RATE} {7.0} + set_instance_parameter_value emif_fm_0 {BOARD_RLD3_USER_RDATA_ISI_NS} {0.0} + set_instance_parameter_value emif_fm_0 {BOARD_RLD3_USER_RDATA_SLEW_RATE} {3.5} + set_instance_parameter_value emif_fm_0 {BOARD_RLD3_USER_WCLK_ISI_NS} {0.0} + set_instance_parameter_value emif_fm_0 {BOARD_RLD3_USER_WCLK_SLEW_RATE} {4.0} + set_instance_parameter_value emif_fm_0 {BOARD_RLD3_USER_WDATA_ISI_NS} {0.0} + set_instance_parameter_value emif_fm_0 {BOARD_RLD3_USER_WDATA_SLEW_RATE} {2.0} + set_instance_parameter_value emif_fm_0 {BOARD_RLD3_USE_DEFAULT_ISI_VALUES} {1} + set_instance_parameter_value emif_fm_0 {BOARD_RLD3_USE_DEFAULT_SLEW_RATES} {1} + set_instance_parameter_value emif_fm_0 {CTRL_DDR3_ADDR_ORDER_ENUM} {DDR3_CTRL_ADDR_ORDER_CS_R_B_C} + set_instance_parameter_value emif_fm_0 {CTRL_DDR3_AUTO_POWER_DOWN_CYCS} {32} + set_instance_parameter_value emif_fm_0 {CTRL_DDR3_AUTO_POWER_DOWN_EN} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDR3_AUTO_PRECHARGE_EN} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDR3_AVL_PROTOCOL_ENUM} {CTRL_AVL_PROTOCOL_MM} + set_instance_parameter_value emif_fm_0 {CTRL_DDR3_ECC_AUTO_CORRECTION_EN} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDR3_ECC_EN} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDR3_ECC_READDATAERROR_EN} {1} + set_instance_parameter_value emif_fm_0 {CTRL_DDR3_ECC_STATUS_EN} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDR3_MMR_EN} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDR3_REORDER_EN} {1} + set_instance_parameter_value emif_fm_0 {CTRL_DDR3_SELF_REFRESH_EN} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDR3_STARVE_LIMIT} {10} + set_instance_parameter_value emif_fm_0 {CTRL_DDR3_USER_PRIORITY_EN} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDR3_USER_REFRESH_EN} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDR4_ADDR_ORDER_ENUM} {DDR4_CTRL_ADDR_ORDER_CS_R_B_C_BG} + set_instance_parameter_value emif_fm_0 {CTRL_DDR4_AUTO_POWER_DOWN_CYCS} {32} + set_instance_parameter_value emif_fm_0 {CTRL_DDR4_AUTO_POWER_DOWN_EN} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDR4_AUTO_PRECHARGE_EN} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDR4_AVL_PROTOCOL_ENUM} {CTRL_AVL_PROTOCOL_MM} + set_instance_parameter_value emif_fm_0 {CTRL_DDR4_ECC_AUTO_CORRECTION_EN} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDR4_ECC_EN} {1} + set_instance_parameter_value emif_fm_0 {CTRL_DDR4_ECC_READDATAERROR_EN} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDR4_ECC_STATUS_EN} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDR4_MAJOR_MODE_EN} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDR4_MMR_EN} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDR4_POST_REFRESH_EN} {1} + set_instance_parameter_value emif_fm_0 {CTRL_DDR4_POST_REFRESH_LOWER_LIMIT} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDR4_POST_REFRESH_UPPER_LIMIT} {2} + set_instance_parameter_value emif_fm_0 {CTRL_DDR4_PRE_REFRESH_EN} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDR4_PRE_REFRESH_UPPER_LIMIT} {1} + set_instance_parameter_value emif_fm_0 {CTRL_DDR4_RD_TO_RD_DIFF_CHIP_DELTA_CYCS} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDR4_RD_TO_WR_DIFF_CHIP_DELTA_CYCS} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDR4_RD_TO_WR_SAME_CHIP_DELTA_CYCS} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDR4_REORDER_EN} {1} + set_instance_parameter_value emif_fm_0 {CTRL_DDR4_SELF_REFRESH_EN} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDR4_STARVE_LIMIT} {10} + set_instance_parameter_value emif_fm_0 {CTRL_DDR4_USER_PRIORITY_EN} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDR4_USER_REFRESH_EN} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDR4_WR_TO_RD_DIFF_CHIP_DELTA_CYCS} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDR4_WR_TO_RD_SAME_CHIP_DELTA_CYCS} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDR4_WR_TO_WR_DIFF_CHIP_DELTA_CYCS} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDRT_ADDR_INTERLEAVING} {COARSE} + set_instance_parameter_value emif_fm_0 {CTRL_DDRT_ADDR_ORDER_ENUM} {DDRT_CTRL_ADDR_ORDER_CS_R_B_C_BG} + set_instance_parameter_value emif_fm_0 {CTRL_DDRT_AUTO_POWER_DOWN_CYCS} {32} + set_instance_parameter_value emif_fm_0 {CTRL_DDRT_AUTO_POWER_DOWN_EN} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDRT_AUTO_PRECHARGE_EN} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDRT_AVL_PROTOCOL_ENUM} {CTRL_AVL_PROTOCOL_MM} + set_instance_parameter_value emif_fm_0 {CTRL_DDRT_DIMM_DENSITY} {128} + set_instance_parameter_value emif_fm_0 {CTRL_DDRT_DIMM_VIRAL_FLOW_EN} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDRT_ECC_AUTO_CORRECTION_EN} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDRT_ECC_EN} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDRT_ECC_READDATAERROR_EN} {1} + set_instance_parameter_value emif_fm_0 {CTRL_DDRT_ECC_STATUS_EN} {1} + set_instance_parameter_value emif_fm_0 {CTRL_DDRT_ERR_INJECT_EN} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDRT_ERR_REPLAY_EN} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDRT_EXT_ERR_INJECT_EN} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDRT_GNT_TO_GNT_DIFF_CHIP_DELTA_CYCS} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDRT_GNT_TO_WR_DIFF_CHIP_DELTA_CYCS} {1} + set_instance_parameter_value emif_fm_0 {CTRL_DDRT_GNT_TO_WR_SAME_CHIP_DELTA_CYCS} {1} + set_instance_parameter_value emif_fm_0 {CTRL_DDRT_HOST_VIRAL_FLOW_EN} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDRT_MMR_EN} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDRT_NUM_OF_AXIS_ID} {1} + set_instance_parameter_value emif_fm_0 {CTRL_DDRT_PARITY_CMD_EN} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDRT_PMM_ADR_FLOW_EN} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDRT_PMM_WPQ_FLUSH_EN} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDRT_POISON_DETECTION_EN} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDRT_PORT_AFI_C_WIDTH} {2} + set_instance_parameter_value emif_fm_0 {CTRL_DDRT_RD_TO_RD_DIFF_CHIP_DELTA_CYCS} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDRT_RD_TO_WR_DIFF_CHIP_DELTA_CYCS} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDRT_RD_TO_WR_SAME_CHIP_DELTA_CYCS} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDRT_REORDER_EN} {1} + set_instance_parameter_value emif_fm_0 {CTRL_DDRT_SELF_REFRESH_EN} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDRT_STARVE_LIMIT} {10} + set_instance_parameter_value emif_fm_0 {CTRL_DDRT_UPI_EN} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDRT_UPI_ID_WIDTH} {8} + set_instance_parameter_value emif_fm_0 {CTRL_DDRT_USER_PRIORITY_EN} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDRT_USER_REFRESH_EN} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDRT_WR_ACK_POLICY} {POSTED} + set_instance_parameter_value emif_fm_0 {CTRL_DDRT_WR_TO_GNT_DIFF_CHIP_DELTA_CYCS} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDRT_WR_TO_GNT_SAME_CHIP_DELTA_CYCS} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDRT_WR_TO_RD_DIFF_CHIP_DELTA_CYCS} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDRT_WR_TO_RD_SAME_CHIP_DELTA_CYCS} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDRT_WR_TO_WR_DIFF_CHIP_DELTA_CYCS} {0} + set_instance_parameter_value emif_fm_0 {CTRL_DDRT_ZQ_INTERVAL_MS} {3} + set_instance_parameter_value emif_fm_0 {CTRL_LPDDR3_ADDR_ORDER_ENUM} {LPDDR3_CTRL_ADDR_ORDER_CS_R_B_C} + set_instance_parameter_value emif_fm_0 {CTRL_LPDDR3_AUTO_POWER_DOWN_CYCS} {32} + set_instance_parameter_value emif_fm_0 {CTRL_LPDDR3_AUTO_POWER_DOWN_EN} {0} + set_instance_parameter_value emif_fm_0 {CTRL_LPDDR3_AUTO_PRECHARGE_EN} {0} + set_instance_parameter_value emif_fm_0 {CTRL_LPDDR3_AVL_PROTOCOL_ENUM} {CTRL_AVL_PROTOCOL_MM} + set_instance_parameter_value emif_fm_0 {CTRL_LPDDR3_MMR_EN} {0} + set_instance_parameter_value emif_fm_0 {CTRL_LPDDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS} {0} + set_instance_parameter_value emif_fm_0 {CTRL_LPDDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS} {0} + set_instance_parameter_value emif_fm_0 {CTRL_LPDDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS} {0} + set_instance_parameter_value emif_fm_0 {CTRL_LPDDR3_REORDER_EN} {1} + set_instance_parameter_value emif_fm_0 {CTRL_LPDDR3_SELF_REFRESH_EN} {0} + set_instance_parameter_value emif_fm_0 {CTRL_LPDDR3_STARVE_LIMIT} {10} + set_instance_parameter_value emif_fm_0 {CTRL_LPDDR3_USER_PRIORITY_EN} {0} + set_instance_parameter_value emif_fm_0 {CTRL_LPDDR3_USER_REFRESH_EN} {0} + set_instance_parameter_value emif_fm_0 {CTRL_LPDDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS} {0} + set_instance_parameter_value emif_fm_0 {CTRL_LPDDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS} {0} + set_instance_parameter_value emif_fm_0 {CTRL_LPDDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS} {0} + set_instance_parameter_value emif_fm_0 {CTRL_QDR2_AVL_ENABLE_POWER_OF_TWO_BUS} {0} + set_instance_parameter_value emif_fm_0 {CTRL_QDR2_AVL_MAX_BURST_COUNT} {4} + set_instance_parameter_value emif_fm_0 {CTRL_QDR2_AVL_PROTOCOL_ENUM} {CTRL_AVL_PROTOCOL_MM} + set_instance_parameter_value emif_fm_0 {CTRL_QDR4_ADD_RAW_TURNAROUND_DELAY_CYC} {0} + set_instance_parameter_value emif_fm_0 {CTRL_QDR4_ADD_WAR_TURNAROUND_DELAY_CYC} {0} + set_instance_parameter_value emif_fm_0 {CTRL_QDR4_AVL_ENABLE_POWER_OF_TWO_BUS} {0} + set_instance_parameter_value emif_fm_0 {CTRL_QDR4_AVL_MAX_BURST_COUNT} {4} + set_instance_parameter_value emif_fm_0 {CTRL_QDR4_AVL_PROTOCOL_ENUM} {CTRL_AVL_PROTOCOL_MM} + set_instance_parameter_value emif_fm_0 {CTRL_QDR4_DEF_RAW_TURNAROUND_DELAY_CYC} {4} + set_instance_parameter_value emif_fm_0 {CTRL_RLD2_AVL_PROTOCOL_ENUM} {CTRL_AVL_PROTOCOL_MM} + set_instance_parameter_value emif_fm_0 {CTRL_RLD3_ADDR_ORDER_ENUM} {RLD3_CTRL_ADDR_ORDER_CS_R_B_C} + set_instance_parameter_value emif_fm_0 {CTRL_RLD3_AVL_PROTOCOL_ENUM} {CTRL_AVL_PROTOCOL_MM} + set_instance_parameter_value emif_fm_0 {DIAG_ADD_READY_PIPELINE} {1} + set_instance_parameter_value emif_fm_0 {DIAG_BOARD_DELAY_CONFIG_STR} {} + set_instance_parameter_value emif_fm_0 {DIAG_DB_RESET_AUTO_RELEASE} {avl_release} + set_instance_parameter_value emif_fm_0 {DIAG_DDR3_ABSTRACT_PHY} {0} + set_instance_parameter_value emif_fm_0 {DIAG_DDR3_AC_PARITY_ERR} {0} + set_instance_parameter_value emif_fm_0 {DIAG_DDR3_CAL_ADDR0} {0} + set_instance_parameter_value emif_fm_0 {DIAG_DDR3_CAL_ADDR1} {8} + set_instance_parameter_value emif_fm_0 {DIAG_DDR3_CAL_ENABLE_MICRON_AP} {0} + set_instance_parameter_value emif_fm_0 {DIAG_DDR3_CAL_ENABLE_NON_DES} {0} + set_instance_parameter_value emif_fm_0 {DIAG_DDR3_CAL_FULL_CAL_ON_RESET} {1} + set_instance_parameter_value emif_fm_0 {DIAG_DDR3_CA_DESKEW_EN} {1} + set_instance_parameter_value emif_fm_0 {DIAG_DDR3_CA_LEVEL_EN} {1} + set_instance_parameter_value emif_fm_0 {DIAG_DDR3_DISABLE_AFI_P2C_REGISTERS} {0} + set_instance_parameter_value emif_fm_0 {DIAG_DDR3_EFFICIENCY_MONITOR} {EFFMON_MODE_DISABLED} + set_instance_parameter_value emif_fm_0 {DIAG_DDR3_ENABLE_DEFAULT_MODE} {0} + set_instance_parameter_value emif_fm_0 {DIAG_DDR3_ENABLE_USER_MODE} {1} + set_instance_parameter_value emif_fm_0 {DIAG_DDR3_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN} {1} + set_instance_parameter_value emif_fm_0 {DIAG_DDR3_EXPORT_SEQ_AVALON_MASTER} {0} + set_instance_parameter_value emif_fm_0 {DIAG_DDR3_EXPORT_SEQ_AVALON_SLAVE} {CAL_DEBUG_EXPORT_MODE_DISABLED} + set_instance_parameter_value emif_fm_0 {DIAG_DDR3_EXPORT_TG_CFG_AVALON_SLAVE} {TG_CFG_AMM_EXPORT_MODE_EXPORT} + set_instance_parameter_value emif_fm_0 {DIAG_DDR3_EX_DESIGN_ISSP_EN} {1} + set_instance_parameter_value emif_fm_0 {DIAG_DDR3_EX_DESIGN_NUM_OF_SLAVES} {1} + set_instance_parameter_value emif_fm_0 {DIAG_DDR3_EX_DESIGN_SEPARATE_RZQS} {1} + set_instance_parameter_value emif_fm_0 {DIAG_DDR3_INTERFACE_ID} {0} + set_instance_parameter_value emif_fm_0 {DIAG_DDR3_SEPARATE_READ_WRITE_ITFS} {0} + set_instance_parameter_value emif_fm_0 {DIAG_DDR3_SIM_CAL_MODE_ENUM} {SIM_CAL_MODE_SKIP} + set_instance_parameter_value emif_fm_0 {DIAG_DDR3_SIM_VERBOSE} {1} + set_instance_parameter_value emif_fm_0 {DIAG_DDR3_TG2_TEST_DURATION} {SHORT} + set_instance_parameter_value emif_fm_0 {DIAG_DDR3_USER_SIM_MEMORY_PRELOAD} {0} + set_instance_parameter_value emif_fm_0 {DIAG_DDR3_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE} {EMIF_PRI_PRELOAD.txt} + set_instance_parameter_value emif_fm_0 {DIAG_DDR3_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE} {EMIF_SEC_PRELOAD.txt} + set_instance_parameter_value emif_fm_0 {DIAG_DDR3_USER_USE_SIM_MEMORY_VALIDATION_TG} {1} + set_instance_parameter_value emif_fm_0 {DIAG_DDR3_USE_NEW_EFFMON_S10} {0} + set_instance_parameter_value emif_fm_0 {DIAG_DDR3_USE_TG_AVL_2} {0} + set_instance_parameter_value emif_fm_0 {DIAG_DDR3_USE_TG_HBM} {0} + set_instance_parameter_value emif_fm_0 {DIAG_DDR4_ABSTRACT_PHY} {0} + set_instance_parameter_value emif_fm_0 {DIAG_DDR4_AC_PARITY_ERR} {0} + set_instance_parameter_value emif_fm_0 {DIAG_DDR4_CAL_ADDR0} {0} + set_instance_parameter_value emif_fm_0 {DIAG_DDR4_CAL_ADDR1} {8} + set_instance_parameter_value emif_fm_0 {DIAG_DDR4_CAL_ENABLE_NON_DES} {0} + set_instance_parameter_value emif_fm_0 {DIAG_DDR4_CAL_FULL_CAL_ON_RESET} {1} + set_instance_parameter_value emif_fm_0 {DIAG_DDR4_DISABLE_AFI_P2C_REGISTERS} {0} + set_instance_parameter_value emif_fm_0 {DIAG_DDR4_EFFICIENCY_MONITOR} {EFFMON_MODE_DISABLED} + set_instance_parameter_value emif_fm_0 {DIAG_DDR4_ENABLE_DEFAULT_MODE} {0} + set_instance_parameter_value emif_fm_0 {DIAG_DDR4_ENABLE_USER_MODE} {1} + set_instance_parameter_value emif_fm_0 {DIAG_DDR4_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN} {1} + set_instance_parameter_value emif_fm_0 {DIAG_DDR4_EXPORT_SEQ_AVALON_MASTER} {0} + set_instance_parameter_value emif_fm_0 {DIAG_DDR4_EXPORT_SEQ_AVALON_SLAVE} {CAL_DEBUG_EXPORT_MODE_JTAG} + set_instance_parameter_value emif_fm_0 {DIAG_DDR4_EXPORT_TG_CFG_AVALON_SLAVE} {TG_CFG_AMM_EXPORT_MODE_EXPORT} + set_instance_parameter_value emif_fm_0 {DIAG_DDR4_EX_DESIGN_ISSP_EN} {1} + set_instance_parameter_value emif_fm_0 {DIAG_DDR4_EX_DESIGN_NUM_OF_SLAVES} {1} + set_instance_parameter_value emif_fm_0 {DIAG_DDR4_EX_DESIGN_SEPARATE_RZQS} {1} + set_instance_parameter_value emif_fm_0 {DIAG_DDR4_INTERFACE_ID} {0} + set_instance_parameter_value emif_fm_0 {DIAG_DDR4_SEPARATE_READ_WRITE_ITFS} {0} + set_instance_parameter_value emif_fm_0 {DIAG_DDR4_SIM_CAL_MODE_ENUM} {SIM_CAL_MODE_SKIP} + set_instance_parameter_value emif_fm_0 {DIAG_DDR4_SIM_VERBOSE} {1} + set_instance_parameter_value emif_fm_0 {DIAG_DDR4_SKIP_AC_PARITY_CHECK} {0} + set_instance_parameter_value emif_fm_0 {DIAG_DDR4_SKIP_CA_DESKEW} {0} + set_instance_parameter_value emif_fm_0 {DIAG_DDR4_SKIP_CA_LEVEL} {0} + set_instance_parameter_value emif_fm_0 {DIAG_DDR4_SKIP_VREF_CAL} {0} + set_instance_parameter_value emif_fm_0 {DIAG_DDR4_TG2_TEST_DURATION} {SHORT} + set_instance_parameter_value emif_fm_0 {DIAG_DDR4_USER_SIM_MEMORY_PRELOAD} {0} + set_instance_parameter_value emif_fm_0 {DIAG_DDR4_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE} {EMIF_PRI_PRELOAD.txt} + set_instance_parameter_value emif_fm_0 {DIAG_DDR4_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE} {EMIF_SEC_PRELOAD.txt} + set_instance_parameter_value emif_fm_0 {DIAG_DDR4_USER_USE_SIM_MEMORY_VALIDATION_TG} {1} + set_instance_parameter_value emif_fm_0 {DIAG_DDR4_USE_NEW_EFFMON_S10} {0} + set_instance_parameter_value emif_fm_0 {DIAG_DDR4_USE_TG_AVL_2} {0} + set_instance_parameter_value emif_fm_0 {DIAG_DDR4_USE_TG_HBM} {0} + set_instance_parameter_value emif_fm_0 {DIAG_DDRT_ABSTRACT_PHY} {0} + set_instance_parameter_value emif_fm_0 {DIAG_DDRT_AC_PARITY_ERR} {0} + set_instance_parameter_value emif_fm_0 {DIAG_DDRT_CAL_ADDR0} {0} + set_instance_parameter_value emif_fm_0 {DIAG_DDRT_CAL_ADDR1} {8} + set_instance_parameter_value emif_fm_0 {DIAG_DDRT_CAL_ENABLE_NON_DES} {0} + set_instance_parameter_value emif_fm_0 {DIAG_DDRT_CAL_FULL_CAL_ON_RESET} {1} + set_instance_parameter_value emif_fm_0 {DIAG_DDRT_DISABLE_AFI_P2C_REGISTERS} {0} + set_instance_parameter_value emif_fm_0 {DIAG_DDRT_EFFICIENCY_MONITOR} {EFFMON_MODE_DISABLED} + set_instance_parameter_value emif_fm_0 {DIAG_DDRT_EFF_TEST} {0} + set_instance_parameter_value emif_fm_0 {DIAG_DDRT_ENABLE_DEFAULT_MODE} {0} + set_instance_parameter_value emif_fm_0 {DIAG_DDRT_ENABLE_DRIVER_MARGINING} {0} + set_instance_parameter_value emif_fm_0 {DIAG_DDRT_ENABLE_ENHANCED_TESTING} {0} + set_instance_parameter_value emif_fm_0 {DIAG_DDRT_ENABLE_USER_MODE} {1} + set_instance_parameter_value emif_fm_0 {DIAG_DDRT_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN} {1} + set_instance_parameter_value emif_fm_0 {DIAG_DDRT_EXPORT_SEQ_AVALON_MASTER} {0} + set_instance_parameter_value emif_fm_0 {DIAG_DDRT_EXPORT_SEQ_AVALON_SLAVE} {CAL_DEBUG_EXPORT_MODE_DISABLED} + set_instance_parameter_value emif_fm_0 {DIAG_DDRT_EXPORT_TG_CFG_AVALON_SLAVE} {TG_CFG_AMM_EXPORT_MODE_JTAG} + set_instance_parameter_value emif_fm_0 {DIAG_DDRT_EX_DESIGN_ISSP_EN} {1} + set_instance_parameter_value emif_fm_0 {DIAG_DDRT_EX_DESIGN_NUM_OF_SLAVES} {1} + set_instance_parameter_value emif_fm_0 {DIAG_DDRT_EX_DESIGN_SEPARATE_RZQS} {1} + set_instance_parameter_value emif_fm_0 {DIAG_DDRT_INTERFACE_ID} {0} + set_instance_parameter_value emif_fm_0 {DIAG_DDRT_SEPARATE_READ_WRITE_ITFS} {0} + set_instance_parameter_value emif_fm_0 {DIAG_DDRT_SIM_CAL_MODE_ENUM} {SIM_CAL_MODE_SKIP} + set_instance_parameter_value emif_fm_0 {DIAG_DDRT_SIM_VERBOSE} {1} + set_instance_parameter_value emif_fm_0 {DIAG_DDRT_SKIP_CA_DESKEW} {0} + set_instance_parameter_value emif_fm_0 {DIAG_DDRT_SKIP_CA_LEVEL} {0} + set_instance_parameter_value emif_fm_0 {DIAG_DDRT_SKIP_VREF_CAL} {0} + set_instance_parameter_value emif_fm_0 {DIAG_DDRT_TG2_TEST_DURATION} {SHORT} + set_instance_parameter_value emif_fm_0 {DIAG_DDRT_USER_SIM_MEMORY_PRELOAD} {0} + set_instance_parameter_value emif_fm_0 {DIAG_DDRT_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE} {EMIF_PRI_PRELOAD.txt} + set_instance_parameter_value emif_fm_0 {DIAG_DDRT_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE} {EMIF_SEC_PRELOAD.txt} + set_instance_parameter_value emif_fm_0 {DIAG_DDRT_USER_USE_SIM_MEMORY_VALIDATION_TG} {1} + set_instance_parameter_value emif_fm_0 {DIAG_DDRT_USE_NEW_EFFMON_S10} {0} + set_instance_parameter_value emif_fm_0 {DIAG_DDRT_USE_TG_AVL_2} {1} + set_instance_parameter_value emif_fm_0 {DIAG_DDRT_USE_TG_HBM} {0} + set_instance_parameter_value emif_fm_0 {DIAG_ECLIPSE_DEBUG} {0} + set_instance_parameter_value emif_fm_0 {DIAG_ENABLE_HPS_EMIF_DEBUG} {0} + set_instance_parameter_value emif_fm_0 {DIAG_ENABLE_JTAG_UART} {0} + set_instance_parameter_value emif_fm_0 {DIAG_ENABLE_JTAG_UART_HEX} {0} + set_instance_parameter_value emif_fm_0 {DIAG_EXPORT_PLL_LOCKED} {1} + set_instance_parameter_value emif_fm_0 {DIAG_EXPORT_PLL_REF_CLK_OUT} {0} + set_instance_parameter_value emif_fm_0 {DIAG_EXPORT_VJI} {0} + set_instance_parameter_value emif_fm_0 {DIAG_EXPOSE_DFT_SIGNALS} {0} + set_instance_parameter_value emif_fm_0 {DIAG_EXPOSE_EARLY_READY} {0} + set_instance_parameter_value emif_fm_0 {DIAG_EXPOSE_RD_TYPE} {0} + set_instance_parameter_value emif_fm_0 {DIAG_EXTRA_CONFIGS} {} + set_instance_parameter_value emif_fm_0 {DIAG_EXT_DOCS} {0} + set_instance_parameter_value emif_fm_0 {DIAG_EX_DESIGN_ADD_TEST_EMIFS} {} + set_instance_parameter_value emif_fm_0 {DIAG_EX_DESIGN_SEPARATE_RESETS} {0} + set_instance_parameter_value emif_fm_0 {DIAG_FAST_SIM_OVERRIDE} {FAST_SIM_OVERRIDE_DEFAULT} + set_instance_parameter_value emif_fm_0 {DIAG_HMC_HRC} {auto} + set_instance_parameter_value emif_fm_0 {DIAG_LPDDR3_ABSTRACT_PHY} {0} + set_instance_parameter_value emif_fm_0 {DIAG_LPDDR3_AC_PARITY_ERR} {0} + set_instance_parameter_value emif_fm_0 {DIAG_LPDDR3_DISABLE_AFI_P2C_REGISTERS} {0} + set_instance_parameter_value emif_fm_0 {DIAG_LPDDR3_EFFICIENCY_MONITOR} {EFFMON_MODE_DISABLED} + set_instance_parameter_value emif_fm_0 {DIAG_LPDDR3_ENABLE_DEFAULT_MODE} {0} + set_instance_parameter_value emif_fm_0 {DIAG_LPDDR3_ENABLE_USER_MODE} {1} + set_instance_parameter_value emif_fm_0 {DIAG_LPDDR3_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN} {1} + set_instance_parameter_value emif_fm_0 {DIAG_LPDDR3_EXPORT_SEQ_AVALON_MASTER} {0} + set_instance_parameter_value emif_fm_0 {DIAG_LPDDR3_EXPORT_SEQ_AVALON_SLAVE} {CAL_DEBUG_EXPORT_MODE_DISABLED} + set_instance_parameter_value emif_fm_0 {DIAG_LPDDR3_EXPORT_TG_CFG_AVALON_SLAVE} {TG_CFG_AMM_EXPORT_MODE_EXPORT} + set_instance_parameter_value emif_fm_0 {DIAG_LPDDR3_EX_DESIGN_ISSP_EN} {1} + set_instance_parameter_value emif_fm_0 {DIAG_LPDDR3_EX_DESIGN_NUM_OF_SLAVES} {1} + set_instance_parameter_value emif_fm_0 {DIAG_LPDDR3_EX_DESIGN_SEPARATE_RZQS} {1} + set_instance_parameter_value emif_fm_0 {DIAG_LPDDR3_INTERFACE_ID} {0} + set_instance_parameter_value emif_fm_0 {DIAG_LPDDR3_SEPARATE_READ_WRITE_ITFS} {0} + set_instance_parameter_value emif_fm_0 {DIAG_LPDDR3_SIM_CAL_MODE_ENUM} {SIM_CAL_MODE_SKIP} + set_instance_parameter_value emif_fm_0 {DIAG_LPDDR3_SIM_VERBOSE} {1} + set_instance_parameter_value emif_fm_0 {DIAG_LPDDR3_SKIP_CA_DESKEW} {0} + set_instance_parameter_value emif_fm_0 {DIAG_LPDDR3_SKIP_CA_LEVEL} {0} + set_instance_parameter_value emif_fm_0 {DIAG_LPDDR3_TG2_TEST_DURATION} {SHORT} + set_instance_parameter_value emif_fm_0 {DIAG_LPDDR3_USER_SIM_MEMORY_PRELOAD} {0} + set_instance_parameter_value emif_fm_0 {DIAG_LPDDR3_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE} {EMIF_PRI_PRELOAD.txt} + set_instance_parameter_value emif_fm_0 {DIAG_LPDDR3_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE} {EMIF_SEC_PRELOAD.txt} + set_instance_parameter_value emif_fm_0 {DIAG_LPDDR3_USER_USE_SIM_MEMORY_VALIDATION_TG} {1} + set_instance_parameter_value emif_fm_0 {DIAG_LPDDR3_USE_NEW_EFFMON_S10} {0} + set_instance_parameter_value emif_fm_0 {DIAG_LPDDR3_USE_TG_AVL_2} {0} + set_instance_parameter_value emif_fm_0 {DIAG_LPDDR3_USE_TG_HBM} {0} + set_instance_parameter_value emif_fm_0 {DIAG_QDR2_ABSTRACT_PHY} {0} + set_instance_parameter_value emif_fm_0 {DIAG_QDR2_AC_PARITY_ERR} {0} + set_instance_parameter_value emif_fm_0 {DIAG_QDR2_DISABLE_AFI_P2C_REGISTERS} {0} + set_instance_parameter_value emif_fm_0 {DIAG_QDR2_EFFICIENCY_MONITOR} {EFFMON_MODE_DISABLED} + set_instance_parameter_value emif_fm_0 {DIAG_QDR2_ENABLE_DEFAULT_MODE} {0} + set_instance_parameter_value emif_fm_0 {DIAG_QDR2_ENABLE_USER_MODE} {1} + set_instance_parameter_value emif_fm_0 {DIAG_QDR2_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN} {1} + set_instance_parameter_value emif_fm_0 {DIAG_QDR2_EXPORT_SEQ_AVALON_MASTER} {0} + set_instance_parameter_value emif_fm_0 {DIAG_QDR2_EXPORT_SEQ_AVALON_SLAVE} {CAL_DEBUG_EXPORT_MODE_DISABLED} + set_instance_parameter_value emif_fm_0 {DIAG_QDR2_EXPORT_TG_CFG_AVALON_SLAVE} {TG_CFG_AMM_EXPORT_MODE_EXPORT} + set_instance_parameter_value emif_fm_0 {DIAG_QDR2_EX_DESIGN_ISSP_EN} {1} + set_instance_parameter_value emif_fm_0 {DIAG_QDR2_EX_DESIGN_NUM_OF_SLAVES} {1} + set_instance_parameter_value emif_fm_0 {DIAG_QDR2_EX_DESIGN_SEPARATE_RZQS} {1} + set_instance_parameter_value emif_fm_0 {DIAG_QDR2_INTERFACE_ID} {0} + set_instance_parameter_value emif_fm_0 {DIAG_QDR2_SEPARATE_READ_WRITE_ITFS} {0} + set_instance_parameter_value emif_fm_0 {DIAG_QDR2_SIM_CAL_MODE_ENUM} {SIM_CAL_MODE_SKIP} + set_instance_parameter_value emif_fm_0 {DIAG_QDR2_SIM_VERBOSE} {1} + set_instance_parameter_value emif_fm_0 {DIAG_QDR2_TG2_TEST_DURATION} {SHORT} + set_instance_parameter_value emif_fm_0 {DIAG_QDR2_USER_SIM_MEMORY_PRELOAD} {0} + set_instance_parameter_value emif_fm_0 {DIAG_QDR2_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE} {EMIF_PRI_PRELOAD.txt} + set_instance_parameter_value emif_fm_0 {DIAG_QDR2_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE} {EMIF_SEC_PRELOAD.txt} + set_instance_parameter_value emif_fm_0 {DIAG_QDR2_USER_USE_SIM_MEMORY_VALIDATION_TG} {1} + set_instance_parameter_value emif_fm_0 {DIAG_QDR2_USE_NEW_EFFMON_S10} {0} + set_instance_parameter_value emif_fm_0 {DIAG_QDR2_USE_TG_AVL_2} {0} + set_instance_parameter_value emif_fm_0 {DIAG_QDR2_USE_TG_HBM} {0} + set_instance_parameter_value emif_fm_0 {DIAG_QDR4_ABSTRACT_PHY} {0} + set_instance_parameter_value emif_fm_0 {DIAG_QDR4_AC_PARITY_ERR} {0} + set_instance_parameter_value emif_fm_0 {DIAG_QDR4_DISABLE_AFI_P2C_REGISTERS} {0} + set_instance_parameter_value emif_fm_0 {DIAG_QDR4_EFFICIENCY_MONITOR} {EFFMON_MODE_DISABLED} + set_instance_parameter_value emif_fm_0 {DIAG_QDR4_ENABLE_DEFAULT_MODE} {0} + set_instance_parameter_value emif_fm_0 {DIAG_QDR4_ENABLE_USER_MODE} {1} + set_instance_parameter_value emif_fm_0 {DIAG_QDR4_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN} {1} + set_instance_parameter_value emif_fm_0 {DIAG_QDR4_EXPORT_SEQ_AVALON_MASTER} {0} + set_instance_parameter_value emif_fm_0 {DIAG_QDR4_EXPORT_SEQ_AVALON_SLAVE} {CAL_DEBUG_EXPORT_MODE_DISABLED} + set_instance_parameter_value emif_fm_0 {DIAG_QDR4_EXPORT_TG_CFG_AVALON_SLAVE} {TG_CFG_AMM_EXPORT_MODE_EXPORT} + set_instance_parameter_value emif_fm_0 {DIAG_QDR4_EX_DESIGN_ISSP_EN} {1} + set_instance_parameter_value emif_fm_0 {DIAG_QDR4_EX_DESIGN_NUM_OF_SLAVES} {1} + set_instance_parameter_value emif_fm_0 {DIAG_QDR4_EX_DESIGN_SEPARATE_RZQS} {1} + set_instance_parameter_value emif_fm_0 {DIAG_QDR4_INTERFACE_ID} {0} + set_instance_parameter_value emif_fm_0 {DIAG_QDR4_SEPARATE_READ_WRITE_ITFS} {0} + set_instance_parameter_value emif_fm_0 {DIAG_QDR4_SIM_CAL_MODE_ENUM} {SIM_CAL_MODE_SKIP} + set_instance_parameter_value emif_fm_0 {DIAG_QDR4_SIM_VERBOSE} {1} + set_instance_parameter_value emif_fm_0 {DIAG_QDR4_SKIP_VREF_CAL} {0} + set_instance_parameter_value emif_fm_0 {DIAG_QDR4_TG2_TEST_DURATION} {SHORT} + set_instance_parameter_value emif_fm_0 {DIAG_QDR4_USER_SIM_MEMORY_PRELOAD} {0} + set_instance_parameter_value emif_fm_0 {DIAG_QDR4_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE} {EMIF_PRI_PRELOAD.txt} + set_instance_parameter_value emif_fm_0 {DIAG_QDR4_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE} {EMIF_SEC_PRELOAD.txt} + set_instance_parameter_value emif_fm_0 {DIAG_QDR4_USER_USE_SIM_MEMORY_VALIDATION_TG} {1} + set_instance_parameter_value emif_fm_0 {DIAG_QDR4_USE_NEW_EFFMON_S10} {0} + set_instance_parameter_value emif_fm_0 {DIAG_QDR4_USE_TG_AVL_2} {0} + set_instance_parameter_value emif_fm_0 {DIAG_QDR4_USE_TG_HBM} {0} + set_instance_parameter_value emif_fm_0 {DIAG_RLD2_ABSTRACT_PHY} {0} + set_instance_parameter_value emif_fm_0 {DIAG_RLD2_AC_PARITY_ERR} {0} + set_instance_parameter_value emif_fm_0 {DIAG_RLD2_DISABLE_AFI_P2C_REGISTERS} {0} + set_instance_parameter_value emif_fm_0 {DIAG_RLD2_EFFICIENCY_MONITOR} {EFFMON_MODE_DISABLED} + set_instance_parameter_value emif_fm_0 {DIAG_RLD2_ENABLE_DEFAULT_MODE} {0} + set_instance_parameter_value emif_fm_0 {DIAG_RLD2_ENABLE_USER_MODE} {1} + set_instance_parameter_value emif_fm_0 {DIAG_RLD2_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN} {1} + set_instance_parameter_value emif_fm_0 {DIAG_RLD2_EXPORT_SEQ_AVALON_MASTER} {0} + set_instance_parameter_value emif_fm_0 {DIAG_RLD2_EXPORT_SEQ_AVALON_SLAVE} {CAL_DEBUG_EXPORT_MODE_DISABLED} + set_instance_parameter_value emif_fm_0 {DIAG_RLD2_EXPORT_TG_CFG_AVALON_SLAVE} {TG_CFG_AMM_EXPORT_MODE_EXPORT} + set_instance_parameter_value emif_fm_0 {DIAG_RLD2_EX_DESIGN_ISSP_EN} {1} + set_instance_parameter_value emif_fm_0 {DIAG_RLD2_EX_DESIGN_NUM_OF_SLAVES} {1} + set_instance_parameter_value emif_fm_0 {DIAG_RLD2_EX_DESIGN_SEPARATE_RZQS} {1} + set_instance_parameter_value emif_fm_0 {DIAG_RLD2_INTERFACE_ID} {0} + set_instance_parameter_value emif_fm_0 {DIAG_RLD2_SEPARATE_READ_WRITE_ITFS} {0} + set_instance_parameter_value emif_fm_0 {DIAG_RLD2_SIM_CAL_MODE_ENUM} {SIM_CAL_MODE_SKIP} + set_instance_parameter_value emif_fm_0 {DIAG_RLD2_SIM_VERBOSE} {1} + set_instance_parameter_value emif_fm_0 {DIAG_RLD2_TG2_TEST_DURATION} {SHORT} + set_instance_parameter_value emif_fm_0 {DIAG_RLD2_USER_SIM_MEMORY_PRELOAD} {0} + set_instance_parameter_value emif_fm_0 {DIAG_RLD2_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE} {EMIF_PRI_PRELOAD.txt} + set_instance_parameter_value emif_fm_0 {DIAG_RLD2_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE} {EMIF_SEC_PRELOAD.txt} + set_instance_parameter_value emif_fm_0 {DIAG_RLD2_USER_USE_SIM_MEMORY_VALIDATION_TG} {1} + set_instance_parameter_value emif_fm_0 {DIAG_RLD2_USE_NEW_EFFMON_S10} {0} + set_instance_parameter_value emif_fm_0 {DIAG_RLD2_USE_TG_AVL_2} {0} + set_instance_parameter_value emif_fm_0 {DIAG_RLD2_USE_TG_HBM} {0} + set_instance_parameter_value emif_fm_0 {DIAG_RLD3_ABSTRACT_PHY} {0} + set_instance_parameter_value emif_fm_0 {DIAG_RLD3_AC_PARITY_ERR} {0} + set_instance_parameter_value emif_fm_0 {DIAG_RLD3_CA_DESKEW_EN} {1} + set_instance_parameter_value emif_fm_0 {DIAG_RLD3_CA_LEVEL_EN} {1} + set_instance_parameter_value emif_fm_0 {DIAG_RLD3_DISABLE_AFI_P2C_REGISTERS} {0} + set_instance_parameter_value emif_fm_0 {DIAG_RLD3_EFFICIENCY_MONITOR} {EFFMON_MODE_DISABLED} + set_instance_parameter_value emif_fm_0 {DIAG_RLD3_ENABLE_DEFAULT_MODE} {0} + set_instance_parameter_value emif_fm_0 {DIAG_RLD3_ENABLE_USER_MODE} {1} + set_instance_parameter_value emif_fm_0 {DIAG_RLD3_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN} {1} + set_instance_parameter_value emif_fm_0 {DIAG_RLD3_EXPORT_SEQ_AVALON_MASTER} {0} + set_instance_parameter_value emif_fm_0 {DIAG_RLD3_EXPORT_SEQ_AVALON_SLAVE} {CAL_DEBUG_EXPORT_MODE_DISABLED} + set_instance_parameter_value emif_fm_0 {DIAG_RLD3_EXPORT_TG_CFG_AVALON_SLAVE} {TG_CFG_AMM_EXPORT_MODE_EXPORT} + set_instance_parameter_value emif_fm_0 {DIAG_RLD3_EX_DESIGN_ISSP_EN} {1} + set_instance_parameter_value emif_fm_0 {DIAG_RLD3_EX_DESIGN_NUM_OF_SLAVES} {1} + set_instance_parameter_value emif_fm_0 {DIAG_RLD3_EX_DESIGN_SEPARATE_RZQS} {1} + set_instance_parameter_value emif_fm_0 {DIAG_RLD3_INTERFACE_ID} {0} + set_instance_parameter_value emif_fm_0 {DIAG_RLD3_SEPARATE_READ_WRITE_ITFS} {0} + set_instance_parameter_value emif_fm_0 {DIAG_RLD3_SIM_CAL_MODE_ENUM} {SIM_CAL_MODE_SKIP} + set_instance_parameter_value emif_fm_0 {DIAG_RLD3_SIM_VERBOSE} {1} + set_instance_parameter_value emif_fm_0 {DIAG_RLD3_TG2_TEST_DURATION} {SHORT} + set_instance_parameter_value emif_fm_0 {DIAG_RLD3_USER_SIM_MEMORY_PRELOAD} {0} + set_instance_parameter_value emif_fm_0 {DIAG_RLD3_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE} {EMIF_PRI_PRELOAD.txt} + set_instance_parameter_value emif_fm_0 {DIAG_RLD3_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE} {EMIF_SEC_PRELOAD.txt} + set_instance_parameter_value emif_fm_0 {DIAG_RLD3_USER_USE_SIM_MEMORY_VALIDATION_TG} {1} + set_instance_parameter_value emif_fm_0 {DIAG_RLD3_USE_NEW_EFFMON_S10} {0} + set_instance_parameter_value emif_fm_0 {DIAG_RLD3_USE_TG_AVL_2} {0} + set_instance_parameter_value emif_fm_0 {DIAG_RLD3_USE_TG_HBM} {0} + set_instance_parameter_value emif_fm_0 {DIAG_RS232_UART_BAUDRATE} {57600} + set_instance_parameter_value emif_fm_0 {DIAG_SEQ_RESET_AUTO_RELEASE} {avl} + set_instance_parameter_value emif_fm_0 {DIAG_SIM_REGTEST_MODE} {0} + set_instance_parameter_value emif_fm_0 {DIAG_SOFT_NIOS_CLOCK_FREQUENCY} {100} + set_instance_parameter_value emif_fm_0 {DIAG_SOFT_NIOS_MODE} {SOFT_NIOS_MODE_DISABLED} + set_instance_parameter_value emif_fm_0 {DIAG_SYNTH_FOR_SIM} {0} + set_instance_parameter_value emif_fm_0 {DIAG_TG_AVL_2_NUM_CFG_INTERFACES} {0} + set_instance_parameter_value emif_fm_0 {DIAG_TIMING_REGTEST_MODE} {0} + set_instance_parameter_value emif_fm_0 {DIAG_USE_BOARD_DELAY_MODEL} {0} + set_instance_parameter_value emif_fm_0 {DIAG_USE_RS232_UART} {0} + set_instance_parameter_value emif_fm_0 {DIAG_VERBOSE_IOAUX} {0} + set_instance_parameter_value emif_fm_0 {EMIF_0_CONN_TO_CALIP} {CALIP_0} + set_instance_parameter_value emif_fm_0 {EMIF_0_REF_CLK_SHARING} {EXPORTED} + set_instance_parameter_value emif_fm_0 {EMIF_0_STORED_PARAM} {} + set_instance_parameter_value emif_fm_0 {EMIF_10_CONN_TO_CALIP} {CALIP_0} + set_instance_parameter_value emif_fm_0 {EMIF_10_REF_CLK_SHARING} {EXPORTED} + set_instance_parameter_value emif_fm_0 {EMIF_10_STORED_PARAM} {} + set_instance_parameter_value emif_fm_0 {EMIF_11_CONN_TO_CALIP} {CALIP_0} + set_instance_parameter_value emif_fm_0 {EMIF_11_REF_CLK_SHARING} {EXPORTED} + set_instance_parameter_value emif_fm_0 {EMIF_11_STORED_PARAM} {} + set_instance_parameter_value emif_fm_0 {EMIF_12_CONN_TO_CALIP} {CALIP_0} + set_instance_parameter_value emif_fm_0 {EMIF_12_REF_CLK_SHARING} {EXPORTED} + set_instance_parameter_value emif_fm_0 {EMIF_12_STORED_PARAM} {} + set_instance_parameter_value emif_fm_0 {EMIF_13_CONN_TO_CALIP} {CALIP_0} + set_instance_parameter_value emif_fm_0 {EMIF_13_REF_CLK_SHARING} {EXPORTED} + set_instance_parameter_value emif_fm_0 {EMIF_13_STORED_PARAM} {} + set_instance_parameter_value emif_fm_0 {EMIF_14_CONN_TO_CALIP} {CALIP_0} + set_instance_parameter_value emif_fm_0 {EMIF_14_REF_CLK_SHARING} {EXPORTED} + set_instance_parameter_value emif_fm_0 {EMIF_14_STORED_PARAM} {} + set_instance_parameter_value emif_fm_0 {EMIF_15_CONN_TO_CALIP} {CALIP_0} + set_instance_parameter_value emif_fm_0 {EMIF_15_REF_CLK_SHARING} {EXPORTED} + set_instance_parameter_value emif_fm_0 {EMIF_15_STORED_PARAM} {} + set_instance_parameter_value emif_fm_0 {EMIF_1_CONN_TO_CALIP} {CALIP_0} + set_instance_parameter_value emif_fm_0 {EMIF_1_REF_CLK_SHARING} {EXPORTED} + set_instance_parameter_value emif_fm_0 {EMIF_1_STORED_PARAM} {} + set_instance_parameter_value emif_fm_0 {EMIF_2_CONN_TO_CALIP} {CALIP_0} + set_instance_parameter_value emif_fm_0 {EMIF_2_REF_CLK_SHARING} {EXPORTED} + set_instance_parameter_value emif_fm_0 {EMIF_2_STORED_PARAM} {} + set_instance_parameter_value emif_fm_0 {EMIF_3_CONN_TO_CALIP} {CALIP_0} + set_instance_parameter_value emif_fm_0 {EMIF_3_REF_CLK_SHARING} {EXPORTED} + set_instance_parameter_value emif_fm_0 {EMIF_3_STORED_PARAM} {} + set_instance_parameter_value emif_fm_0 {EMIF_4_CONN_TO_CALIP} {CALIP_0} + set_instance_parameter_value emif_fm_0 {EMIF_4_REF_CLK_SHARING} {EXPORTED} + set_instance_parameter_value emif_fm_0 {EMIF_4_STORED_PARAM} {} + set_instance_parameter_value emif_fm_0 {EMIF_5_CONN_TO_CALIP} {CALIP_0} + set_instance_parameter_value emif_fm_0 {EMIF_5_REF_CLK_SHARING} {EXPORTED} + set_instance_parameter_value emif_fm_0 {EMIF_5_STORED_PARAM} {} + set_instance_parameter_value emif_fm_0 {EMIF_6_CONN_TO_CALIP} {CALIP_0} + set_instance_parameter_value emif_fm_0 {EMIF_6_REF_CLK_SHARING} {EXPORTED} + set_instance_parameter_value emif_fm_0 {EMIF_6_STORED_PARAM} {} + set_instance_parameter_value emif_fm_0 {EMIF_7_CONN_TO_CALIP} {CALIP_0} + set_instance_parameter_value emif_fm_0 {EMIF_7_REF_CLK_SHARING} {EXPORTED} + set_instance_parameter_value emif_fm_0 {EMIF_7_STORED_PARAM} {} + set_instance_parameter_value emif_fm_0 {EMIF_8_CONN_TO_CALIP} {CALIP_0} + set_instance_parameter_value emif_fm_0 {EMIF_8_REF_CLK_SHARING} {EXPORTED} + set_instance_parameter_value emif_fm_0 {EMIF_8_STORED_PARAM} {} + set_instance_parameter_value emif_fm_0 {EMIF_9_CONN_TO_CALIP} {CALIP_0} + set_instance_parameter_value emif_fm_0 {EMIF_9_REF_CLK_SHARING} {EXPORTED} + set_instance_parameter_value emif_fm_0 {EMIF_9_STORED_PARAM} {} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_DDR3_GEN_BSI} {0} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_DDR3_GEN_CDC} {0} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_DDR3_GEN_SIM} {1} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_DDR3_GEN_SYNTH} {1} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_DDR3_HDL_FORMAT} {HDL_FORMAT_VERILOG} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_DDR3_PREV_PRESET} {TARGET_DEV_KIT_NONE} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_DDR3_SEL_DESIGN} {AVAIL_EX_DESIGNS_GEN_DESIGN} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_DDR3_TARGET_DEV_KIT} {TARGET_DEV_KIT_NONE} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_DDR4_GEN_BSI} {0} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_DDR4_GEN_CDC} {0} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_DDR4_GEN_SIM} {1} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_DDR4_GEN_SYNTH} {1} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_DDR4_HDL_FORMAT} {HDL_FORMAT_VERILOG} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_DDR4_PREV_PRESET} {TARGET_DEV_KIT_NONE} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_DDR4_SEL_DESIGN} {AVAIL_EX_DESIGNS_GEN_DESIGN} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_DDR4_TARGET_DEV_KIT} {TARGET_DEV_KIT_NONE} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_DDRT_GEN_BSI} {0} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_DDRT_GEN_CDC} {0} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_DDRT_GEN_SIM} {1} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_DDRT_GEN_SYNTH} {1} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_DDRT_HDL_FORMAT} {HDL_FORMAT_VERILOG} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_DDRT_PREV_PRESET} {TARGET_DEV_KIT_NONE} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_DDRT_SEL_DESIGN} {AVAIL_EX_DESIGNS_GEN_DESIGN} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_DDRT_TARGET_DEV_KIT} {TARGET_DEV_KIT_NONE} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_LPDDR3_GEN_BSI} {0} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_LPDDR3_GEN_CDC} {0} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_LPDDR3_GEN_SIM} {1} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_LPDDR3_GEN_SYNTH} {1} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_LPDDR3_HDL_FORMAT} {HDL_FORMAT_VERILOG} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_LPDDR3_PREV_PRESET} {TARGET_DEV_KIT_NONE} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_LPDDR3_SEL_DESIGN} {AVAIL_EX_DESIGNS_GEN_DESIGN} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_LPDDR3_TARGET_DEV_KIT} {TARGET_DEV_KIT_NONE} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_QDR2_GEN_BSI} {0} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_QDR2_GEN_CDC} {0} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_QDR2_GEN_SIM} {1} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_QDR2_GEN_SYNTH} {1} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_QDR2_HDL_FORMAT} {HDL_FORMAT_VERILOG} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_QDR2_PREV_PRESET} {TARGET_DEV_KIT_NONE} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_QDR2_SEL_DESIGN} {AVAIL_EX_DESIGNS_GEN_DESIGN} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_QDR2_TARGET_DEV_KIT} {TARGET_DEV_KIT_NONE} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_QDR4_GEN_BSI} {0} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_QDR4_GEN_CDC} {0} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_QDR4_GEN_SIM} {1} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_QDR4_GEN_SYNTH} {1} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_QDR4_HDL_FORMAT} {HDL_FORMAT_VERILOG} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_QDR4_PREV_PRESET} {TARGET_DEV_KIT_NONE} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_QDR4_SEL_DESIGN} {AVAIL_EX_DESIGNS_GEN_DESIGN} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_QDR4_TARGET_DEV_KIT} {TARGET_DEV_KIT_NONE} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_RLD2_GEN_BSI} {0} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_RLD2_GEN_CDC} {0} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_RLD2_GEN_SIM} {1} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_RLD2_GEN_SYNTH} {1} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_RLD2_HDL_FORMAT} {HDL_FORMAT_VERILOG} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_RLD2_PREV_PRESET} {TARGET_DEV_KIT_NONE} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_RLD2_SEL_DESIGN} {AVAIL_EX_DESIGNS_GEN_DESIGN} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_RLD2_TARGET_DEV_KIT} {TARGET_DEV_KIT_NONE} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_RLD3_GEN_BSI} {0} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_RLD3_GEN_CDC} {0} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_RLD3_GEN_SIM} {1} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_RLD3_GEN_SYNTH} {1} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_RLD3_HDL_FORMAT} {HDL_FORMAT_VERILOG} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_RLD3_PREV_PRESET} {TARGET_DEV_KIT_NONE} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_RLD3_SEL_DESIGN} {AVAIL_EX_DESIGNS_GEN_DESIGN} + set_instance_parameter_value emif_fm_0 {EX_DESIGN_GUI_RLD3_TARGET_DEV_KIT} {TARGET_DEV_KIT_NONE} + set_instance_parameter_value emif_fm_0 {INTERNAL_TESTING_MODE} {0} + set_instance_parameter_value emif_fm_0 {IS_ED_SLAVE} {0} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_ALERT_N_DQS_GROUP} {0} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_ALERT_N_PLACEMENT_ENUM} {DDR3_ALERT_N_PLACEMENT_AC_LANES} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_ASR_ENUM} {DDR3_ASR_MANUAL} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_ATCL_ENUM} {DDR3_ATCL_DISABLED} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_BANK_ADDR_WIDTH} {3} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_BL_ENUM} {DDR3_BL_BL8} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_BT_ENUM} {DDR3_BT_SEQUENTIAL} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_CFG_GEN_DBE} {0} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_CFG_GEN_SBE} {0} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_CKE_PER_DIMM} {1} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_CK_WIDTH} {1} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_COL_ADDR_WIDTH} {10} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_DISCRETE_CS_WIDTH} {1} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_DISCRETE_MIRROR_ADDRESSING_EN} {0} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_DLL_EN} {1} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_DM_EN} {1} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_DQ_PER_DQS} {8} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_DQ_WIDTH} {72} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_DRV_STR_ENUM} {DDR3_DRV_STR_RZQ_7} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_FORMAT_ENUM} {MEM_FORMAT_UDIMM} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_HIDE_ADV_MR_SETTINGS} {1} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_LRDIMM_EXTENDED_CONFIG} {000000000000000000} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_MIRROR_ADDRESSING_EN} {1} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_NUM_OF_DIMMS} {1} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_PD_ENUM} {DDR3_PD_OFF} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_RANKS_PER_DIMM} {1} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_RDIMM_CONFIG} {0000000000000000} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_ROW_ADDR_WIDTH} {15} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_RTT_NOM_ENUM} {DDR3_RTT_NOM_ODT_DISABLED} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_RTT_WR_ENUM} {DDR3_RTT_WR_RZQ_4} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_R_ODT0_1X1} {off} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_R_ODT0_2X2} {off off} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_R_ODT0_4X2} {off off on on} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_R_ODT0_4X4} {off off on off} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_R_ODT1_2X2} {off off} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_R_ODT1_4X2} {on on off off} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_R_ODT1_4X4} {off off off on} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_R_ODT2_4X4} {on off off off} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_R_ODT3_4X4} {off on off off} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_R_ODTN_1X1} {Rank\ 0} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_R_ODTN_2X2} {Rank\ 0 Rank\ 1} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_R_ODTN_4X2} {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_R_ODTN_4X4} {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_SPEEDBIN_ENUM} {DDR3_SPEEDBIN_2133} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_SRT_ENUM} {DDR3_SRT_NORMAL} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_TCL} {14} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_TDH_DC_MV} {100} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_TDH_PS} {55} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_TDQSCK_PS} {180} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_TDQSQ_PS} {75} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_TDQSS_CYC} {0.27} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_TDSH_CYC} {0.18} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_TDSS_CYC} {0.18} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_TDS_AC_MV} {135} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_TDS_PS} {53} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_TFAW_NS} {25.0} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_TIH_DC_MV} {100} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_TIH_PS} {95} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_TINIT_US} {500} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_TIS_AC_MV} {135} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_TIS_PS} {60} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_TMRD_CK_CYC} {4} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_TQH_CYC} {0.38} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_TQSH_CYC} {0.4} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_TRAS_NS} {33.0} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_TRCD_NS} {13.09} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_TREFI_US} {7.8} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_TRFC_NS} {160.0} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_TRP_NS} {13.09} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_TRRD_CYC} {6} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_TRTP_CYC} {8} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_TWLH_PS} {125.0} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_TWLS_PS} {125.0} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_TWR_NS} {15.0} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_TWTR_CYC} {8} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_USE_DEFAULT_ODT} {1} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_WTCL} {10} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_W_ODT0_1X1} {on} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_W_ODT0_2X2} {on off} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_W_ODT0_4X2} {off off on on} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_W_ODT0_4X4} {on off on off} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_W_ODT1_2X2} {off on} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_W_ODT1_4X2} {on on off off} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_W_ODT1_4X4} {off on off on} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_W_ODT2_4X4} {on off on off} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_W_ODT3_4X4} {off on off on} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_W_ODTN_1X1} {Rank\ 0} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_W_ODTN_2X2} {Rank\ 0 Rank\ 1} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_W_ODTN_4X2} {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} + set_instance_parameter_value emif_fm_0 {MEM_DDR3_W_ODTN_4X4} {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_AC_PARITY_LATENCY} {DDR4_AC_PARITY_LATENCY_DISABLE} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_AC_PERSISTENT_ERROR} {0} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_ALERT_N_AC_LANE} {3} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_ALERT_N_AC_PIN} {8} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_ALERT_N_DQS_GROUP} {0} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_ALERT_N_PLACEMENT_ENUM} {DDR4_ALERT_N_PLACEMENT_FM_LANE3} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_ALERT_PAR_EN} {1} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_ASR_ENUM} {DDR4_ASR_MANUAL_NORMAL} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_ATCL_ENUM} {DDR4_ATCL_DISABLED} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_BANK_ADDR_WIDTH} {2} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_BANK_GROUP_WIDTH} {2} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_BL_ENUM} {DDR4_BL_BL8} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_BT_ENUM} {DDR4_BT_SEQUENTIAL} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_CAL_MODE} {0} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_CFG_GEN_DBE} {0} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_CFG_GEN_SBE} {0} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_CHIP_ID_WIDTH} {0} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_CKE_PER_DIMM} {1} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_CK_WIDTH} {1} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_COL_ADDR_WIDTH} {10} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_DB_DQ_DRV_ENUM} {DDR4_DB_DRV_STR_RZQ_7} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_DB_RTT_NOM_ENUM} {DDR4_DB_RTT_NOM_ODT_DISABLED} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_DB_RTT_PARK_ENUM} {DDR4_DB_RTT_PARK_ODT_DISABLED} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_DB_RTT_WR_ENUM} {DDR4_DB_RTT_WR_RZQ_3} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_DEFAULT_VREFOUT} {1} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_DISCRETE_CS_WIDTH} {1} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_DISCRETE_MIRROR_ADDRESSING_EN} {0} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_DLL_EN} {1} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_DM_EN} {1} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_DQ_PER_DQS} {8} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_DQ_WIDTH} {72} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_DRV_STR_ENUM} {DDR4_DRV_STR_RZQ_7} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_FINE_GRANULARITY_REFRESH} {DDR4_FINE_REFRESH_FIXED_1X} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_FORMAT_ENUM} {MEM_FORMAT_RDIMM} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_GEARDOWN} {DDR4_GEARDOWN_HR} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_HIDE_ADV_MR_SETTINGS} {1} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_INTEL_DEFAULT_TERM} {1} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_INTERNAL_VREFDQ_MONITOR} {0} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_LRDIMM_ODT_LESS_BS} {1} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_LRDIMM_ODT_LESS_BS_PARK_OHM} {240} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_LRDIMM_VREFDQ_VALUE} {} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_MAX_POWERDOWN} {0} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_MIRROR_ADDRESSING_EN} {1} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_MPR_READ_FORMAT} {DDR4_MPR_READ_FORMAT_SERIAL} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_NUM_OF_DIMMS} {1} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_ODT_IN_POWERDOWN} {1} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_PER_DRAM_ADDR} {0} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_RANKS_PER_DIMM} {1} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_RCD_CA_IBT_ENUM} {DDR4_RCD_CA_IBT_100} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_RCD_CKE_IBT_ENUM} {DDR4_RCD_CKE_IBT_100} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_RCD_CS_IBT_ENUM} {DDR4_RCD_CS_IBT_100} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_RCD_ODT_IBT_ENUM} {DDR4_RCD_ODT_IBT_100} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_READ_DBI} {1} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_READ_PREAMBLE} {2} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_READ_PREAMBLE_TRAINING} {0} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_ROW_ADDR_WIDTH} {16} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_RTT_NOM_ENUM} {DDR4_RTT_NOM_RZQ_4} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_RTT_PARK} {DDR4_RTT_PARK_ODT_DISABLED} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_RTT_WR_ENUM} {DDR4_RTT_WR_ODT_DISABLED} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_R_ODT0_1X1} {off} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_R_ODT0_2X2} {off off} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_R_ODT0_4X2} {off off on on} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_R_ODT0_4X4} {off off on off} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_R_ODT1_2X2} {off off} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_R_ODT1_4X2} {on on off off} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_R_ODT1_4X4} {off off off on} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_R_ODT2_4X4} {on off off off} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_R_ODT3_4X4} {off on off off} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_R_ODTN_1X1} {Rank\ 0} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_R_ODTN_2X2} {Rank\ 0 Rank\ 1} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_R_ODTN_4X2} {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_R_ODTN_4X4} {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_SELF_RFSH_ABORT} {0} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_SPD_133_RCD_DB_VENDOR_LSB} {0} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_SPD_134_RCD_DB_VENDOR_MSB} {0} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_SPD_135_RCD_REV} {0} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_SPD_137_RCD_CA_DRV} {101} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_SPD_138_RCD_CK_DRV} {5} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_SPD_139_DB_REV} {0} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_SPD_140_DRAM_VREFDQ_R0} {29} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_SPD_141_DRAM_VREFDQ_R1} {29} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_SPD_142_DRAM_VREFDQ_R2} {29} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_SPD_143_DRAM_VREFDQ_R3} {29} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_SPD_144_DB_VREFDQ} {37} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_SPD_145_DB_MDQ_DRV} {21} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_SPD_148_DRAM_DRV} {0} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_SPD_149_DRAM_RTT_WR_NOM} {20} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_SPD_152_DRAM_RTT_PARK} {39} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_SPD_155_DB_VREFDQ_RANGE} {0} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_SPEEDBIN_ENUM} {DDR4_SPEEDBIN_2666} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TCCD_L_CYC} {6} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TCCD_S_CYC} {4} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TCL} {21} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TDIVW_DJ_CYC} {0.1} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TDIVW_TOTAL_UI} {0.2} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TDQSCK_PS} {175} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TDQSQ_PS} {66} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TDQSQ_UI} {0.14} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TDQSS_CYC} {0.27} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TDSH_CYC} {0.18} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TDSS_CYC} {0.18} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TDVWP_UI} {0.72} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TEMP_CONTROLLED_RFSH_ENA} {0} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TEMP_CONTROLLED_RFSH_RANGE} {DDR4_TEMP_CONTROLLED_RFSH_NORMAL} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TEMP_SENSOR_READOUT} {0} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TFAW_DLR_CYC} {16} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TFAW_NS} {21.0} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TIH_DC_MV} {75} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TIH_PS} {87} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TINIT_US} {500} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TIS_AC_MV} {100} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TIS_PS} {62} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TMRD_CK_CYC} {8} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TQH_CYC} {0.38} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TQH_UI} {0.74} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TQSH_CYC} {0.4} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TRAS_NS} {32.0} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TRCD_NS} {14.16} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TREFI_US} {7.8} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TRFC_DLR_NS} {90.0} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TRFC_NS} {350.0} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TRP_NS} {14.16} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TRRD_DLR_CYC} {4} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TRRD_L_CYC} {6} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TRRD_S_CYC} {4} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TWLH_CYC} {0.13} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TWLH_PS} {0.0} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TWLS_CYC} {0.13} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TWLS_PS} {0.0} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TWR_NS} {15.0} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TWTR_L_CYC} {9} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TWTR_S_CYC} {3} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_USER_VREFDQ_TRAINING_RANGE} {DDR4_VREFDQ_TRAINING_RANGE_1} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_USER_VREFDQ_TRAINING_VALUE} {56.0} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_USE_DEFAULT_ODT} {1} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_VDIVW_TOTAL} {130} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_WRITE_CRC} {0} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_WRITE_DBI} {0} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_WRITE_PREAMBLE} {1} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_WTCL} {16} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_W_ODT0_1X1} {on} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_W_ODT0_2X2} {on off} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_W_ODT0_4X2} {off off on on} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_W_ODT0_4X4} {on off on off} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_W_ODT1_2X2} {off on} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_W_ODT1_4X2} {on on off off} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_W_ODT1_4X4} {off on off on} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_W_ODT2_4X4} {on off on off} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_W_ODT3_4X4} {off on off on} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_W_ODTN_1X1} {Rank\ 0} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_W_ODTN_2X2} {Rank\ 0 Rank\ 1} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_W_ODTN_4X2} {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_W_ODTN_4X4} {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_AC_PARITY_LATENCY} {DDRT_AC_PARITY_LATENCY_DISABLE} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_AC_PERSISTENT_ERROR} {0} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_ALERT_N_AC_LANE} {0} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_ALERT_N_AC_PIN} {0} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_ALERT_N_DQS_GROUP} {0} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_ALERT_N_PLACEMENT_ENUM} {DDRT_ALERT_N_PLACEMENT_AUTO} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_ALERT_PAR_EN} {1} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_ASR_ENUM} {DDRT_ASR_MANUAL_NORMAL} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_ATCL_ENUM} {DDRT_ATCL_DISABLED} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_BANK_ADDR_WIDTH} {2} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_BANK_GROUP_WIDTH} {2} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_BL_ENUM} {DDRT_BL_BL8} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_BT_ENUM} {DDRT_BT_SEQUENTIAL} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_CAL_MODE} {0} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_CFG_GEN_DBE} {0} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_CFG_GEN_SBE} {0} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_CKE_PER_DIMM} {1} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_COL_ADDR_WIDTH} {10} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_DB_DQ_DRV_ENUM} {DDRT_DB_DRV_STR_RZQ_7} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_DB_RTT_NOM_ENUM} {DDRT_DB_RTT_NOM_ODT_DISABLED} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_DB_RTT_PARK_ENUM} {DDRT_DB_RTT_PARK_ODT_DISABLED} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_DB_RTT_WR_ENUM} {DDRT_DB_RTT_WR_RZQ_4} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_DEFAULT_ADDED_LATENCY} {1} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_DEFAULT_PREAMBLE} {1} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_DEFAULT_VREFOUT} {1} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_DISCRETE_CS_WIDTH} {1} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_DISCRETE_MIRROR_ADDRESSING_EN} {0} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_DLL_EN} {1} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_DM_EN} {0} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_DQ_PER_DQS} {4} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_DQ_WIDTH} {72} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_DRV_STR_ENUM} {DDRT_DRV_STR_RZQ_7} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_FINE_GRANULARITY_REFRESH} {DDRT_FINE_REFRESH_FIXED_1X} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_FORMAT_ENUM} {MEM_FORMAT_LRDIMM} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_GEARDOWN} {DDRT_GEARDOWN_HR} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_HIDE_ADV_MR_SETTINGS} {1} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_HIDE_LATENCY_SETTINGS} {1} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_I2C_DIMM_0_SA} {0} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_I2C_DIMM_1_SA} {1} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_I2C_DIMM_2_SA} {2} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_I2C_DIMM_3_SA} {3} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_INTERNAL_VREFDQ_MONITOR} {0} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_LRDIMM_ODT_LESS_BS} {0} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_LRDIMM_ODT_LESS_BS_PARK_OHM} {240} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_LRDIMM_VREFDQ_VALUE} {} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_MAX_POWERDOWN} {0} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_MIRROR_ADDRESSING_EN} {1} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_MPR_READ_FORMAT} {DDRT_MPR_READ_FORMAT_SERIAL} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_NUM_OF_DIMMS} {1} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_ODT_IN_POWERDOWN} {1} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_PARTIAL_WRITES} {0} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_PERSISTENT_MODE} {1} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_PER_DRAM_ADDR} {0} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_PWR_MODE} {DDRT_PWR_MODE_12W} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_RANKS_PER_DIMM} {1} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_RCD_CA_IBT_ENUM} {DDRT_RCD_CA_IBT_100} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_RCD_CKE_IBT_ENUM} {DDRT_RCD_CKE_IBT_100} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_RCD_CS_IBT_ENUM} {DDRT_RCD_CS_IBT_100} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_RCD_ODT_IBT_ENUM} {DDRT_RCD_ODT_IBT_100} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_READ_DBI} {0} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_READ_PREAMBLE_TRAINING} {0} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_ROW_ADDR_WIDTH} {18} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_RTT_NOM_ENUM} {DDRT_RTT_NOM_RZQ_4} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_RTT_PARK} {DDRT_RTT_PARK_ODT_DISABLED} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_RTT_WR_ENUM} {DDRT_RTT_WR_ODT_DISABLED} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_R_ODT0_1X1} {off} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_R_ODT0_2X2} {off off} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_R_ODT0_4X2} {off off on on} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_R_ODT0_4X4} {off off off off} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_R_ODT1_2X2} {off off} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_R_ODT1_4X2} {on on off off} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_R_ODT1_4X4} {off off on on} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_R_ODT2_4X4} {off off off off} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_R_ODT3_4X4} {on on off off} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_R_ODTN_1X1} {Rank\ 0} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_R_ODTN_2X2} {Rank\ 0 Rank\ 1} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_R_ODTN_4X2} {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_R_ODTN_4X4} {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_SELF_RFSH_ABORT} {0} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_SPD_133_RCD_DB_VENDOR_LSB} {0} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_SPD_134_RCD_DB_VENDOR_MSB} {0} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_SPD_135_RCD_REV} {0} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_SPD_137_RCD_CA_DRV} {85} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_SPD_138_RCD_CK_DRV} {5} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_SPD_139_DB_REV} {0} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_SPD_140_DRAM_VREFDQ_R0} {29} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_SPD_141_DRAM_VREFDQ_R1} {29} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_SPD_142_DRAM_VREFDQ_R2} {29} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_SPD_143_DRAM_VREFDQ_R3} {29} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_SPD_144_DB_VREFDQ} {25} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_SPD_145_DB_MDQ_DRV} {21} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_SPD_148_DRAM_DRV} {0} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_SPD_149_DRAM_RTT_WR_NOM} {20} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_SPD_152_DRAM_RTT_PARK} {39} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_SPEEDBIN_ENUM} {DDRT_SPEEDBIN_2400} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_TCCD_L_CYC} {6} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_TCCD_S_CYC} {4} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_TCL} {15} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_TDIVW_DJ_CYC} {0.1} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_TDIVW_TOTAL_UI} {0.2} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_TDQSCK_PS} {165} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_TDQSQ_PS} {66} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_TDQSQ_UI} {0.16} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_TDQSS_CYC} {0.27} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_TDSH_CYC} {0.18} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_TDSS_CYC} {0.18} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_TDVWP_UI} {0.72} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_TEMP_CONTROLLED_RFSH_ENA} {0} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_TEMP_CONTROLLED_RFSH_RANGE} {DDRT_TEMP_CONTROLLED_RFSH_NORMAL} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_TEMP_SENSOR_READOUT} {0} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_TFAW_DLR_CYC} {16} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_TFAW_NS} {21.0} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_TIH_DC_MV} {75} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_TIH_PS} {95} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_TINIT_US} {500} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_TIS_AC_MV} {100} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_TIS_PS} {60} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_TMRD_CK_CYC} {8} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_TQH_CYC} {0.38} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_TQH_UI} {0.76} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_TQSH_CYC} {0.38} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_TRAS_NS} {32.0} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_TRCD_NS} {15.0} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_TREFI_US} {7.8} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_TRFC_DLR_NS} {90.0} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_TRFC_NS} {260.0} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_TRP_NS} {15.0} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_TRRD_DLR_CYC} {4} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_TRRD_L_CYC} {6} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_TRRD_S_CYC} {4} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_TWLH_CYC} {0.13} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_TWLH_PS} {0.0} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_TWLS_CYC} {0.13} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_TWLS_PS} {0.0} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_TWR_NS} {15.0} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_TWTR_L_CYC} {9} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_TWTR_S_CYC} {3} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_USER_READ_PREAMBLE} {1} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_USER_TCL_ADDED} {0} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_USER_VREFDQ_TRAINING_RANGE} {DDRT_VREFDQ_TRAINING_RANGE_1} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_USER_VREFDQ_TRAINING_VALUE} {56.0} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_USER_WRITE_PREAMBLE} {1} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_USER_WTCL_ADDED} {6} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_USE_DEFAULT_ODT} {1} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_VDIVW_TOTAL} {136} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_WRITE_CRC} {0} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_WRITE_DBI} {0} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_WTCL} {18} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_W_ODT0_1X1} {on} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_W_ODT0_2X2} {on off} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_W_ODT0_4X2} {off off on on} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_W_ODT0_4X4} {on on off off} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_W_ODT1_2X2} {off on} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_W_ODT1_4X2} {on on off off} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_W_ODT1_4X4} {off off on on} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_W_ODT2_4X4} {off off on on} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_W_ODT3_4X4} {on on off off} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_W_ODTN_1X1} {Rank\ 0} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_W_ODTN_2X2} {Rank\ 0 Rank\ 1} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_W_ODTN_4X2} {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} + set_instance_parameter_value emif_fm_0 {MEM_DDRT_W_ODTN_4X4} {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_BANK_ADDR_WIDTH} {3} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_BL} {LPDDR3_BL_BL8} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_CK_WIDTH} {1} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_COL_ADDR_WIDTH} {10} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_DATA_LATENCY} {LPDDR3_DL_RL12_WL6} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_DISCRETE_CS_WIDTH} {1} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_DM_EN} {1} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_DQODT} {LPDDR3_DQODT_DISABLE} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_DQ_WIDTH} {32} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_DRV_STR} {LPDDR3_DRV_STR_40D_40U} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_PDODT} {LPDDR3_PDODT_DISABLED} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_ROW_ADDR_WIDTH} {15} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_R_ODT0_1X1} {off} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_R_ODT0_2X2} {off off} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_R_ODT0_4X4} {off off off off} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_R_ODT1_2X2} {off off} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_R_ODT1_4X4} {off off off off} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_R_ODT2_4X4} {off off off off} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_R_ODT3_4X4} {off off off off} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_R_ODTN_1X1} {Rank\ 0} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_R_ODTN_2X2} {Rank\ 0 Rank\ 1} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_R_ODTN_4X4} {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_SPEEDBIN_ENUM} {LPDDR3_SPEEDBIN_1600} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_TDH_DC_MV} {100} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_TDH_PS} {100} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_TDQSCKDL} {614} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_TDQSQ_PS} {135} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_TDQSS_CYC} {1.25} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_TDSH_CYC} {0.2} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_TDSS_CYC} {0.2} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_TDS_AC_MV} {150} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_TDS_PS} {75} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_TFAW_NS} {50.0} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_TIH_DC_MV} {100} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_TIH_PS} {100} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_TINIT_US} {500} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_TIS_AC_MV} {150} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_TIS_PS} {75} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_TMRR_CK_CYC} {4} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_TMRW_CK_CYC} {10} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_TQH_CYC} {0.38} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_TQSH_CYC} {0.38} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_TRAS_NS} {42.5} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_TRCD_NS} {18.0} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_TREFI_US} {3.9} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_TRFC_NS} {210.0} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_TRP_NS} {18.0} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_TRRD_CYC} {8} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_TRTP_CYC} {6} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_TWLH_PS} {175.0} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_TWLS_PS} {175.0} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_TWR_NS} {15.0} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_TWTR_CYC} {6} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_USE_DEFAULT_ODT} {1} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_W_ODT0_1X1} {on} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_W_ODT0_2X2} {on on} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_W_ODT0_4X4} {on on on on} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_W_ODT1_2X2} {off off} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_W_ODT1_4X4} {off off off off} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_W_ODT2_4X4} {off off off off} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_W_ODT3_4X4} {off off off off} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_W_ODTN_1X1} {Rank\ 0} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_W_ODTN_2X2} {Rank\ 0 Rank\ 1} + set_instance_parameter_value emif_fm_0 {MEM_LPDDR3_W_ODTN_4X4} {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} + set_instance_parameter_value emif_fm_0 {MEM_QDR2_ADDR_WIDTH} {19} + set_instance_parameter_value emif_fm_0 {MEM_QDR2_BL} {4} + set_instance_parameter_value emif_fm_0 {MEM_QDR2_BWS_EN} {1} + set_instance_parameter_value emif_fm_0 {MEM_QDR2_DATA_PER_DEVICE} {36} + set_instance_parameter_value emif_fm_0 {MEM_QDR2_INTERNAL_JITTER_NS} {0.08} + set_instance_parameter_value emif_fm_0 {MEM_QDR2_SPEEDBIN_ENUM} {QDR2_SPEEDBIN_633} + set_instance_parameter_value emif_fm_0 {MEM_QDR2_TCCQO_NS} {0.45} + set_instance_parameter_value emif_fm_0 {MEM_QDR2_TCQDOH_NS} {-0.09} + set_instance_parameter_value emif_fm_0 {MEM_QDR2_TCQD_NS} {0.09} + set_instance_parameter_value emif_fm_0 {MEM_QDR2_TCQH_NS} {0.71} + set_instance_parameter_value emif_fm_0 {MEM_QDR2_THA_NS} {0.18} + set_instance_parameter_value emif_fm_0 {MEM_QDR2_THD_NS} {0.18} + set_instance_parameter_value emif_fm_0 {MEM_QDR2_TRL_CYC} {2.5} + set_instance_parameter_value emif_fm_0 {MEM_QDR2_TSA_NS} {0.23} + set_instance_parameter_value emif_fm_0 {MEM_QDR2_TSD_NS} {0.23} + set_instance_parameter_value emif_fm_0 {MEM_QDR2_WIDTH_EXPANDED} {0} + set_instance_parameter_value emif_fm_0 {MEM_QDR4_AC_ODT_MODE_ENUM} {QDR4_ODT_25_PCT} + set_instance_parameter_value emif_fm_0 {MEM_QDR4_ADDR_INV_ENA} {0} + set_instance_parameter_value emif_fm_0 {MEM_QDR4_ADDR_WIDTH} {21} + set_instance_parameter_value emif_fm_0 {MEM_QDR4_CK_ODT_MODE_ENUM} {QDR4_ODT_25_PCT} + set_instance_parameter_value emif_fm_0 {MEM_QDR4_DATA_INV_ENA} {1} + set_instance_parameter_value emif_fm_0 {MEM_QDR4_DATA_ODT_MODE_ENUM} {QDR4_ODT_25_PCT} + set_instance_parameter_value emif_fm_0 {MEM_QDR4_DQ_PER_PORT_PER_DEVICE} {36} + set_instance_parameter_value emif_fm_0 {MEM_QDR4_MEM_TYPE_ENUM} {MEM_XP} + set_instance_parameter_value emif_fm_0 {MEM_QDR4_PD_OUTPUT_DRIVE_MODE_ENUM} {QDR4_OUTPUT_DRIVE_25_PCT} + set_instance_parameter_value emif_fm_0 {MEM_QDR4_PU_OUTPUT_DRIVE_MODE_ENUM} {QDR4_OUTPUT_DRIVE_25_PCT} + set_instance_parameter_value emif_fm_0 {MEM_QDR4_SKIP_ODT_SWEEPING} {1} + set_instance_parameter_value emif_fm_0 {MEM_QDR4_SPEEDBIN_ENUM} {QDR4_SPEEDBIN_2133} + set_instance_parameter_value emif_fm_0 {MEM_QDR4_TASH_PS} {170} + set_instance_parameter_value emif_fm_0 {MEM_QDR4_TCKDK_MAX_PS} {150} + set_instance_parameter_value emif_fm_0 {MEM_QDR4_TCKDK_MIN_PS} {-150} + set_instance_parameter_value emif_fm_0 {MEM_QDR4_TCKQK_MAX_PS} {225} + set_instance_parameter_value emif_fm_0 {MEM_QDR4_TCSH_PS} {170} + set_instance_parameter_value emif_fm_0 {MEM_QDR4_TISH_PS} {150} + set_instance_parameter_value emif_fm_0 {MEM_QDR4_TQH_CYC} {0.4} + set_instance_parameter_value emif_fm_0 {MEM_QDR4_TQKQ_MAX_PS} {75} + set_instance_parameter_value emif_fm_0 {MEM_QDR4_USE_ADDR_PARITY} {0} + set_instance_parameter_value emif_fm_0 {MEM_QDR4_WIDTH_EXPANDED} {0} + set_instance_parameter_value emif_fm_0 {MEM_RLD2_ADDR_WIDTH} {21} + set_instance_parameter_value emif_fm_0 {MEM_RLD2_BANK_ADDR_WIDTH} {3} + set_instance_parameter_value emif_fm_0 {MEM_RLD2_BL} {4} + set_instance_parameter_value emif_fm_0 {MEM_RLD2_CONFIG_ENUM} {RLD2_CONFIG_TRC_8_TRL_8_TWL_9} + set_instance_parameter_value emif_fm_0 {MEM_RLD2_DM_EN} {1} + set_instance_parameter_value emif_fm_0 {MEM_RLD2_DQ_PER_DEVICE} {9} + set_instance_parameter_value emif_fm_0 {MEM_RLD2_DRIVE_IMPEDENCE_ENUM} {RLD2_DRIVE_IMPEDENCE_INTERNAL_50} + set_instance_parameter_value emif_fm_0 {MEM_RLD2_ODT_MODE_ENUM} {RLD2_ODT_ON} + set_instance_parameter_value emif_fm_0 {MEM_RLD2_REFRESH_INTERVAL_US} {0.24} + set_instance_parameter_value emif_fm_0 {MEM_RLD2_SPEEDBIN_ENUM} {RLD2_SPEEDBIN_18} + set_instance_parameter_value emif_fm_0 {MEM_RLD2_TAH_NS} {0.3} + set_instance_parameter_value emif_fm_0 {MEM_RLD2_TAS_NS} {0.3} + set_instance_parameter_value emif_fm_0 {MEM_RLD2_TCKDK_MAX_NS} {0.3} + set_instance_parameter_value emif_fm_0 {MEM_RLD2_TCKDK_MIN_NS} {-0.3} + set_instance_parameter_value emif_fm_0 {MEM_RLD2_TCKH_CYC} {0.45} + set_instance_parameter_value emif_fm_0 {MEM_RLD2_TCKQK_MAX_NS} {0.2} + set_instance_parameter_value emif_fm_0 {MEM_RLD2_TDH_NS} {0.17} + set_instance_parameter_value emif_fm_0 {MEM_RLD2_TDS_NS} {0.17} + set_instance_parameter_value emif_fm_0 {MEM_RLD2_TQKH_HCYC} {0.9} + set_instance_parameter_value emif_fm_0 {MEM_RLD2_TQKQ_MAX_NS} {0.12} + set_instance_parameter_value emif_fm_0 {MEM_RLD2_TQKQ_MIN_NS} {-0.12} + set_instance_parameter_value emif_fm_0 {MEM_RLD2_WIDTH_EXPANDED} {0} + set_instance_parameter_value emif_fm_0 {MEM_RLD3_ADDR_WIDTH} {20} + set_instance_parameter_value emif_fm_0 {MEM_RLD3_AREF_PROTOCOL_ENUM} {RLD3_AREF_BAC} + set_instance_parameter_value emif_fm_0 {MEM_RLD3_BANK_ADDR_WIDTH} {4} + set_instance_parameter_value emif_fm_0 {MEM_RLD3_BL} {2} + set_instance_parameter_value emif_fm_0 {MEM_RLD3_DATA_LATENCY_MODE_ENUM} {RLD3_DL_RL16_WL17} + set_instance_parameter_value emif_fm_0 {MEM_RLD3_DEPTH_EXPANDED} {0} + set_instance_parameter_value emif_fm_0 {MEM_RLD3_DM_EN} {1} + set_instance_parameter_value emif_fm_0 {MEM_RLD3_DQ_PER_DEVICE} {36} + set_instance_parameter_value emif_fm_0 {MEM_RLD3_ODT_MODE_ENUM} {RLD3_ODT_40} + set_instance_parameter_value emif_fm_0 {MEM_RLD3_OUTPUT_DRIVE_MODE_ENUM} {RLD3_OUTPUT_DRIVE_40} + set_instance_parameter_value emif_fm_0 {MEM_RLD3_SPEEDBIN_ENUM} {RLD3_SPEEDBIN_093E} + set_instance_parameter_value emif_fm_0 {MEM_RLD3_TCKDK_MAX_CYC} {0.27} + set_instance_parameter_value emif_fm_0 {MEM_RLD3_TCKDK_MIN_CYC} {-0.27} + set_instance_parameter_value emif_fm_0 {MEM_RLD3_TCKQK_MAX_PS} {135} + set_instance_parameter_value emif_fm_0 {MEM_RLD3_TDH_DC_MV} {100} + set_instance_parameter_value emif_fm_0 {MEM_RLD3_TDH_PS} {5} + set_instance_parameter_value emif_fm_0 {MEM_RLD3_TDS_AC_MV} {150} + set_instance_parameter_value emif_fm_0 {MEM_RLD3_TDS_PS} {-30} + set_instance_parameter_value emif_fm_0 {MEM_RLD3_TIH_DC_MV} {100} + set_instance_parameter_value emif_fm_0 {MEM_RLD3_TIH_PS} {65} + set_instance_parameter_value emif_fm_0 {MEM_RLD3_TIS_AC_MV} {150} + set_instance_parameter_value emif_fm_0 {MEM_RLD3_TIS_PS} {85} + set_instance_parameter_value emif_fm_0 {MEM_RLD3_TQH_CYC} {0.38} + set_instance_parameter_value emif_fm_0 {MEM_RLD3_TQKQ_MAX_PS} {75} + set_instance_parameter_value emif_fm_0 {MEM_RLD3_T_RC_MODE_ENUM} {RLD3_TRC_9} + set_instance_parameter_value emif_fm_0 {MEM_RLD3_WIDTH_EXPANDED} {0} + set_instance_parameter_value emif_fm_0 {MEM_RLD3_WRITE_PROTOCOL_ENUM} {RLD3_WRITE_1BANK} + set_instance_parameter_value emif_fm_0 {NUM_IPS} {1} + set_instance_parameter_value emif_fm_0 {PHY_DDR3_CAL_ADDR0} {0} + set_instance_parameter_value emif_fm_0 {PHY_DDR3_CAL_ADDR1} {8} + set_instance_parameter_value emif_fm_0 {PHY_DDR3_CAL_ENABLE_NON_DES} {0} + set_instance_parameter_value emif_fm_0 {PHY_DDR3_CONFIG_ENUM} {CONFIG_PHY_AND_HARD_CTRL} + set_instance_parameter_value emif_fm_0 {PHY_DDR3_CORE_CLKS_SHARING_ENUM} {CORE_CLKS_SHARING_DISABLED} + set_instance_parameter_value emif_fm_0 {PHY_DDR3_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT} {0} + set_instance_parameter_value emif_fm_0 {PHY_DDR3_DEFAULT_IO} {1} + set_instance_parameter_value emif_fm_0 {PHY_DDR3_DEFAULT_REF_CLK_FREQ} {1} + set_instance_parameter_value emif_fm_0 {PHY_DDR3_HPS_ENABLE_EARLY_RELEASE} {0} + set_instance_parameter_value emif_fm_0 {PHY_DDR3_IO_VOLTAGE} {1.5} + set_instance_parameter_value emif_fm_0 {PHY_DDR3_MEM_CLK_FREQ_MHZ} {1066.667} + set_instance_parameter_value emif_fm_0 {PHY_DDR3_MIMIC_HPS_EMIF} {0} + set_instance_parameter_value emif_fm_0 {PHY_DDR3_RATE_ENUM} {RATE_QUARTER} + set_instance_parameter_value emif_fm_0 {PHY_DDR3_REF_CLK_JITTER_PS} {10.0} + set_instance_parameter_value emif_fm_0 {PHY_DDR3_USER_AC_DEEMPHASIS_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_DDR3_USER_AC_IO_STD_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_DDR3_USER_AC_MODE_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_DDR3_USER_AC_SLEW_RATE_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_DDR3_USER_AUTO_STARTING_VREFIN_EN} {1} + set_instance_parameter_value emif_fm_0 {PHY_DDR3_USER_CK_DEEMPHASIS_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_DDR3_USER_CK_IO_STD_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_DDR3_USER_CK_MODE_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_DDR3_USER_CK_SLEW_RATE_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_DDR3_USER_DATA_IN_MODE_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_DDR3_USER_DATA_IO_STD_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_DDR3_USER_DATA_OUT_DEEMPHASIS_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_DDR3_USER_DATA_OUT_MODE_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_DDR3_USER_DATA_OUT_SLEW_RATE_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_DDR3_USER_DLL_CORE_UPDN_EN} {1} + set_instance_parameter_value emif_fm_0 {PHY_DDR3_USER_PERIODIC_OCT_RECAL_ENUM} {PERIODIC_OCT_RECAL_AUTO} + set_instance_parameter_value emif_fm_0 {PHY_DDR3_USER_PING_PONG_EN} {0} + set_instance_parameter_value emif_fm_0 {PHY_DDR3_USER_PLL_REF_CLK_IO_STD_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_DDR3_USER_REF_CLK_FREQ_MHZ} {-1.0} + set_instance_parameter_value emif_fm_0 {PHY_DDR3_USER_RZQ_IO_STD_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_DDR3_USER_STARTING_VREFIN} {70.0} + set_instance_parameter_value emif_fm_0 {PHY_DDR4_ALLOW_72_DQ_WIDTH} {0} + set_instance_parameter_value emif_fm_0 {PHY_DDR4_CONFIG_ENUM} {CONFIG_PHY_AND_HARD_CTRL} + set_instance_parameter_value emif_fm_0 {PHY_DDR4_CORE_CLKS_SHARING_ENUM} {CORE_CLKS_SHARING_DISABLED} + set_instance_parameter_value emif_fm_0 {PHY_DDR4_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT} {0} + set_instance_parameter_value emif_fm_0 {PHY_DDR4_DEFAULT_IO} {0} + set_instance_parameter_value emif_fm_0 {PHY_DDR4_DEFAULT_REF_CLK_FREQ} {0} + set_instance_parameter_value emif_fm_0 {PHY_DDR4_HPS_ENABLE_EARLY_RELEASE} {0} + set_instance_parameter_value emif_fm_0 {PHY_DDR4_IO_VOLTAGE} {1.2} + set_instance_parameter_value emif_fm_0 {PHY_DDR4_MEM_CLK_FREQ_MHZ} {1200.0} + set_instance_parameter_value emif_fm_0 {PHY_DDR4_MIMIC_HPS_EMIF} {0} + set_instance_parameter_value emif_fm_0 {PHY_DDR4_RATE_ENUM} {RATE_QUARTER} + set_instance_parameter_value emif_fm_0 {PHY_DDR4_REF_CLK_JITTER_PS} {10.0} + set_instance_parameter_value emif_fm_0 {PHY_DDR4_USER_AC_DEEMPHASIS_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_DDR4_USER_AC_IO_STD_ENUM} {IO_STD_SSTL_12} + set_instance_parameter_value emif_fm_0 {PHY_DDR4_USER_AC_MODE_ENUM} {OUT_OCT_40_CAL} + set_instance_parameter_value emif_fm_0 {PHY_DDR4_USER_AC_SLEW_RATE_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_DDR4_USER_AUTO_STARTING_VREFIN_EN} {1} + set_instance_parameter_value emif_fm_0 {PHY_DDR4_USER_CK_DEEMPHASIS_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_DDR4_USER_CK_IO_STD_ENUM} {IO_STD_SSTL_12} + set_instance_parameter_value emif_fm_0 {PHY_DDR4_USER_CK_MODE_ENUM} {OUT_OCT_40_CAL} + set_instance_parameter_value emif_fm_0 {PHY_DDR4_USER_CK_SLEW_RATE_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_DDR4_USER_CLAMSHELL_EN} {0} + set_instance_parameter_value emif_fm_0 {PHY_DDR4_USER_DATA_IN_MODE_ENUM} {IN_OCT_60_CAL} + set_instance_parameter_value emif_fm_0 {PHY_DDR4_USER_DATA_IO_STD_ENUM} {IO_STD_POD_12} + set_instance_parameter_value emif_fm_0 {PHY_DDR4_USER_DATA_OUT_DEEMPHASIS_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_DDR4_USER_DATA_OUT_MODE_ENUM} {OUT_OCT_40_CAL} + set_instance_parameter_value emif_fm_0 {PHY_DDR4_USER_DATA_OUT_SLEW_RATE_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_DDR4_USER_DLL_CORE_UPDN_EN} {1} + set_instance_parameter_value emif_fm_0 {PHY_DDR4_USER_PERIODIC_OCT_RECAL_ENUM} {PERIODIC_OCT_RECAL_AUTO} + set_instance_parameter_value emif_fm_0 {PHY_DDR4_USER_PING_PONG_EN} {0} + set_instance_parameter_value emif_fm_0 {PHY_DDR4_USER_PLL_REF_CLK_IO_STD_ENUM} {IO_STD_TRUE_DIFF_SIGNALING} + set_instance_parameter_value emif_fm_0 {PHY_DDR4_USER_REF_CLK_FREQ_MHZ} {33.333} + set_instance_parameter_value emif_fm_0 {PHY_DDR4_USER_RZQ_IO_STD_ENUM} {IO_STD_CMOS_12} + set_instance_parameter_value emif_fm_0 {PHY_DDR4_USER_STARTING_VREFIN} {70.0} + set_instance_parameter_value emif_fm_0 {PHY_DDRT_2CH_EN} {0} + set_instance_parameter_value emif_fm_0 {PHY_DDRT_CONFIG_ENUM} {CONFIG_PHY_AND_SOFT_CTRL} + set_instance_parameter_value emif_fm_0 {PHY_DDRT_CORE_CLKS_SHARING_ENUM} {CORE_CLKS_SHARING_DISABLED} + set_instance_parameter_value emif_fm_0 {PHY_DDRT_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT} {0} + set_instance_parameter_value emif_fm_0 {PHY_DDRT_DEFAULT_IO} {1} + set_instance_parameter_value emif_fm_0 {PHY_DDRT_DEFAULT_REF_CLK_FREQ} {1} + set_instance_parameter_value emif_fm_0 {PHY_DDRT_EXPORT_CLK_STP_IF} {0} + set_instance_parameter_value emif_fm_0 {PHY_DDRT_HPS_ENABLE_EARLY_RELEASE} {0} + set_instance_parameter_value emif_fm_0 {PHY_DDRT_I2C_USE_SMC} {0} + set_instance_parameter_value emif_fm_0 {PHY_DDRT_IC_EN} {1} + set_instance_parameter_value emif_fm_0 {PHY_DDRT_IO_VOLTAGE} {1.2} + set_instance_parameter_value emif_fm_0 {PHY_DDRT_MEM_CLK_FREQ_MHZ} {1200.0} + set_instance_parameter_value emif_fm_0 {PHY_DDRT_MIMIC_HPS_EMIF} {0} + set_instance_parameter_value emif_fm_0 {PHY_DDRT_RATE_ENUM} {RATE_QUARTER} + set_instance_parameter_value emif_fm_0 {PHY_DDRT_REF_CLK_JITTER_PS} {10.0} + set_instance_parameter_value emif_fm_0 {PHY_DDRT_USER_AC_DEEMPHASIS_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_DDRT_USER_AC_IN_MODE_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_DDRT_USER_AC_IO_STD_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_DDRT_USER_AC_MODE_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_DDRT_USER_AC_SLEW_RATE_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_DDRT_USER_AUTO_STARTING_VREFIN_EN} {1} + set_instance_parameter_value emif_fm_0 {PHY_DDRT_USER_CK_DEEMPHASIS_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_DDRT_USER_CK_IO_STD_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_DDRT_USER_CK_MODE_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_DDRT_USER_CK_SLEW_RATE_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_DDRT_USER_DATA_IN_MODE_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_DDRT_USER_DATA_IO_STD_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_DDRT_USER_DATA_OUT_DEEMPHASIS_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_DDRT_USER_DATA_OUT_MODE_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_DDRT_USER_DATA_OUT_SLEW_RATE_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_DDRT_USER_DLL_CORE_UPDN_EN} {0} + set_instance_parameter_value emif_fm_0 {PHY_DDRT_USER_PERIODIC_OCT_RECAL_ENUM} {PERIODIC_OCT_RECAL_AUTO} + set_instance_parameter_value emif_fm_0 {PHY_DDRT_USER_PING_PONG_EN} {0} + set_instance_parameter_value emif_fm_0 {PHY_DDRT_USER_PLL_REF_CLK_IO_STD_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_DDRT_USER_REF_CLK_FREQ_MHZ} {-1.0} + set_instance_parameter_value emif_fm_0 {PHY_DDRT_USER_RZQ_IO_STD_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_DDRT_USER_STARTING_VREFIN} {70.0} + set_instance_parameter_value emif_fm_0 {PHY_DDRT_USE_OLD_SMBUS_MULTICOL} {0} + set_instance_parameter_value emif_fm_0 {PHY_LPDDR3_CONFIG_ENUM} {CONFIG_PHY_AND_HARD_CTRL} + set_instance_parameter_value emif_fm_0 {PHY_LPDDR3_CORE_CLKS_SHARING_ENUM} {CORE_CLKS_SHARING_DISABLED} + set_instance_parameter_value emif_fm_0 {PHY_LPDDR3_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT} {0} + set_instance_parameter_value emif_fm_0 {PHY_LPDDR3_DEFAULT_IO} {1} + set_instance_parameter_value emif_fm_0 {PHY_LPDDR3_DEFAULT_REF_CLK_FREQ} {1} + set_instance_parameter_value emif_fm_0 {PHY_LPDDR3_HPS_ENABLE_EARLY_RELEASE} {0} + set_instance_parameter_value emif_fm_0 {PHY_LPDDR3_IO_VOLTAGE} {1.2} + set_instance_parameter_value emif_fm_0 {PHY_LPDDR3_MEM_CLK_FREQ_MHZ} {800.0} + set_instance_parameter_value emif_fm_0 {PHY_LPDDR3_MIMIC_HPS_EMIF} {0} + set_instance_parameter_value emif_fm_0 {PHY_LPDDR3_RATE_ENUM} {RATE_QUARTER} + set_instance_parameter_value emif_fm_0 {PHY_LPDDR3_REF_CLK_JITTER_PS} {10.0} + set_instance_parameter_value emif_fm_0 {PHY_LPDDR3_USER_AC_DEEMPHASIS_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_LPDDR3_USER_AC_IO_STD_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_LPDDR3_USER_AC_MODE_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_LPDDR3_USER_AC_SLEW_RATE_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_LPDDR3_USER_AUTO_STARTING_VREFIN_EN} {1} + set_instance_parameter_value emif_fm_0 {PHY_LPDDR3_USER_CK_DEEMPHASIS_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_LPDDR3_USER_CK_IO_STD_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_LPDDR3_USER_CK_MODE_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_LPDDR3_USER_CK_SLEW_RATE_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_LPDDR3_USER_DATA_IN_MODE_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_LPDDR3_USER_DATA_IO_STD_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_LPDDR3_USER_DATA_OUT_DEEMPHASIS_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_LPDDR3_USER_DATA_OUT_MODE_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_LPDDR3_USER_DATA_OUT_SLEW_RATE_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_LPDDR3_USER_DLL_CORE_UPDN_EN} {0} + set_instance_parameter_value emif_fm_0 {PHY_LPDDR3_USER_PERIODIC_OCT_RECAL_ENUM} {PERIODIC_OCT_RECAL_AUTO} + set_instance_parameter_value emif_fm_0 {PHY_LPDDR3_USER_PING_PONG_EN} {0} + set_instance_parameter_value emif_fm_0 {PHY_LPDDR3_USER_PLL_REF_CLK_IO_STD_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_LPDDR3_USER_REF_CLK_FREQ_MHZ} {-1.0} + set_instance_parameter_value emif_fm_0 {PHY_LPDDR3_USER_RZQ_IO_STD_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_LPDDR3_USER_STARTING_VREFIN} {70.0} + set_instance_parameter_value emif_fm_0 {PHY_QDR2_CONFIG_ENUM} {CONFIG_PHY_AND_SOFT_CTRL} + set_instance_parameter_value emif_fm_0 {PHY_QDR2_CORE_CLKS_SHARING_ENUM} {CORE_CLKS_SHARING_DISABLED} + set_instance_parameter_value emif_fm_0 {PHY_QDR2_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT} {0} + set_instance_parameter_value emif_fm_0 {PHY_QDR2_DEFAULT_IO} {1} + set_instance_parameter_value emif_fm_0 {PHY_QDR2_DEFAULT_REF_CLK_FREQ} {1} + set_instance_parameter_value emif_fm_0 {PHY_QDR2_HPS_ENABLE_EARLY_RELEASE} {0} + set_instance_parameter_value emif_fm_0 {PHY_QDR2_IO_VOLTAGE} {1.5} + set_instance_parameter_value emif_fm_0 {PHY_QDR2_MEM_CLK_FREQ_MHZ} {633.333} + set_instance_parameter_value emif_fm_0 {PHY_QDR2_MIMIC_HPS_EMIF} {0} + set_instance_parameter_value emif_fm_0 {PHY_QDR2_RATE_ENUM} {RATE_HALF} + set_instance_parameter_value emif_fm_0 {PHY_QDR2_REF_CLK_JITTER_PS} {10.0} + set_instance_parameter_value emif_fm_0 {PHY_QDR2_USER_AC_DEEMPHASIS_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_QDR2_USER_AC_IO_STD_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_QDR2_USER_AC_MODE_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_QDR2_USER_AC_SLEW_RATE_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_QDR2_USER_AUTO_STARTING_VREFIN_EN} {1} + set_instance_parameter_value emif_fm_0 {PHY_QDR2_USER_CK_DEEMPHASIS_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_QDR2_USER_CK_IO_STD_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_QDR2_USER_CK_MODE_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_QDR2_USER_CK_SLEW_RATE_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_QDR2_USER_DATA_IN_MODE_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_QDR2_USER_DATA_IO_STD_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_QDR2_USER_DATA_OUT_DEEMPHASIS_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_QDR2_USER_DATA_OUT_MODE_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_QDR2_USER_DATA_OUT_SLEW_RATE_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_QDR2_USER_DLL_CORE_UPDN_EN} {0} + set_instance_parameter_value emif_fm_0 {PHY_QDR2_USER_PERIODIC_OCT_RECAL_ENUM} {PERIODIC_OCT_RECAL_AUTO} + set_instance_parameter_value emif_fm_0 {PHY_QDR2_USER_PING_PONG_EN} {0} + set_instance_parameter_value emif_fm_0 {PHY_QDR2_USER_PLL_REF_CLK_IO_STD_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_QDR2_USER_REF_CLK_FREQ_MHZ} {-1.0} + set_instance_parameter_value emif_fm_0 {PHY_QDR2_USER_RZQ_IO_STD_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_QDR2_USER_STARTING_VREFIN} {70.0} + set_instance_parameter_value emif_fm_0 {PHY_QDR4_CONFIG_ENUM} {CONFIG_PHY_AND_SOFT_CTRL} + set_instance_parameter_value emif_fm_0 {PHY_QDR4_CORE_CLKS_SHARING_ENUM} {CORE_CLKS_SHARING_DISABLED} + set_instance_parameter_value emif_fm_0 {PHY_QDR4_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT} {0} + set_instance_parameter_value emif_fm_0 {PHY_QDR4_DEFAULT_IO} {1} + set_instance_parameter_value emif_fm_0 {PHY_QDR4_DEFAULT_REF_CLK_FREQ} {1} + set_instance_parameter_value emif_fm_0 {PHY_QDR4_HPS_ENABLE_EARLY_RELEASE} {0} + set_instance_parameter_value emif_fm_0 {PHY_QDR4_IO_VOLTAGE} {1.2} + set_instance_parameter_value emif_fm_0 {PHY_QDR4_MEM_CLK_FREQ_MHZ} {1066.667} + set_instance_parameter_value emif_fm_0 {PHY_QDR4_MIMIC_HPS_EMIF} {0} + set_instance_parameter_value emif_fm_0 {PHY_QDR4_RATE_ENUM} {RATE_QUARTER} + set_instance_parameter_value emif_fm_0 {PHY_QDR4_REF_CLK_JITTER_PS} {10.0} + set_instance_parameter_value emif_fm_0 {PHY_QDR4_USER_AC_DEEMPHASIS_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_QDR4_USER_AC_IO_STD_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_QDR4_USER_AC_MODE_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_QDR4_USER_AC_SLEW_RATE_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_QDR4_USER_AUTO_STARTING_VREFIN_EN} {1} + set_instance_parameter_value emif_fm_0 {PHY_QDR4_USER_CK_DEEMPHASIS_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_QDR4_USER_CK_IO_STD_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_QDR4_USER_CK_MODE_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_QDR4_USER_CK_SLEW_RATE_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_QDR4_USER_DATA_IN_MODE_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_QDR4_USER_DATA_IO_STD_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_QDR4_USER_DATA_OUT_DEEMPHASIS_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_QDR4_USER_DATA_OUT_MODE_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_QDR4_USER_DATA_OUT_SLEW_RATE_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_QDR4_USER_DLL_CORE_UPDN_EN} {1} + set_instance_parameter_value emif_fm_0 {PHY_QDR4_USER_PERIODIC_OCT_RECAL_ENUM} {PERIODIC_OCT_RECAL_AUTO} + set_instance_parameter_value emif_fm_0 {PHY_QDR4_USER_PING_PONG_EN} {0} + set_instance_parameter_value emif_fm_0 {PHY_QDR4_USER_PLL_REF_CLK_IO_STD_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_QDR4_USER_REF_CLK_FREQ_MHZ} {-1.0} + set_instance_parameter_value emif_fm_0 {PHY_QDR4_USER_RZQ_IO_STD_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_QDR4_USER_STARTING_VREFIN} {70.0} + set_instance_parameter_value emif_fm_0 {PHY_RLD2_CONFIG_ENUM} {CONFIG_PHY_AND_SOFT_CTRL} + set_instance_parameter_value emif_fm_0 {PHY_RLD2_CORE_CLKS_SHARING_ENUM} {CORE_CLKS_SHARING_DISABLED} + set_instance_parameter_value emif_fm_0 {PHY_RLD2_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT} {0} + set_instance_parameter_value emif_fm_0 {PHY_RLD2_DEFAULT_IO} {1} + set_instance_parameter_value emif_fm_0 {PHY_RLD2_DEFAULT_REF_CLK_FREQ} {1} + set_instance_parameter_value emif_fm_0 {PHY_RLD2_HPS_ENABLE_EARLY_RELEASE} {0} + set_instance_parameter_value emif_fm_0 {PHY_RLD2_IO_VOLTAGE} {1.8} + set_instance_parameter_value emif_fm_0 {PHY_RLD2_MEM_CLK_FREQ_MHZ} {533.333} + set_instance_parameter_value emif_fm_0 {PHY_RLD2_MIMIC_HPS_EMIF} {0} + set_instance_parameter_value emif_fm_0 {PHY_RLD2_RATE_ENUM} {RATE_HALF} + set_instance_parameter_value emif_fm_0 {PHY_RLD2_REF_CLK_JITTER_PS} {10.0} + set_instance_parameter_value emif_fm_0 {PHY_RLD2_USER_AC_DEEMPHASIS_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_RLD2_USER_AC_IO_STD_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_RLD2_USER_AC_MODE_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_RLD2_USER_AC_SLEW_RATE_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_RLD2_USER_AUTO_STARTING_VREFIN_EN} {1} + set_instance_parameter_value emif_fm_0 {PHY_RLD2_USER_CK_DEEMPHASIS_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_RLD2_USER_CK_IO_STD_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_RLD2_USER_CK_MODE_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_RLD2_USER_CK_SLEW_RATE_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_RLD2_USER_DATA_IN_MODE_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_RLD2_USER_DATA_IO_STD_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_RLD2_USER_DATA_OUT_DEEMPHASIS_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_RLD2_USER_DATA_OUT_MODE_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_RLD2_USER_DATA_OUT_SLEW_RATE_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_RLD2_USER_DLL_CORE_UPDN_EN} {0} + set_instance_parameter_value emif_fm_0 {PHY_RLD2_USER_PERIODIC_OCT_RECAL_ENUM} {PERIODIC_OCT_RECAL_AUTO} + set_instance_parameter_value emif_fm_0 {PHY_RLD2_USER_PING_PONG_EN} {0} + set_instance_parameter_value emif_fm_0 {PHY_RLD2_USER_PLL_REF_CLK_IO_STD_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_RLD2_USER_REF_CLK_FREQ_MHZ} {-1.0} + set_instance_parameter_value emif_fm_0 {PHY_RLD2_USER_RZQ_IO_STD_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_RLD2_USER_STARTING_VREFIN} {70.0} + set_instance_parameter_value emif_fm_0 {PHY_RLD3_CONFIG_ENUM} {CONFIG_PHY_ONLY} + set_instance_parameter_value emif_fm_0 {PHY_RLD3_CORE_CLKS_SHARING_ENUM} {CORE_CLKS_SHARING_DISABLED} + set_instance_parameter_value emif_fm_0 {PHY_RLD3_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT} {0} + set_instance_parameter_value emif_fm_0 {PHY_RLD3_DEFAULT_IO} {1} + set_instance_parameter_value emif_fm_0 {PHY_RLD3_DEFAULT_REF_CLK_FREQ} {1} + set_instance_parameter_value emif_fm_0 {PHY_RLD3_HPS_ENABLE_EARLY_RELEASE} {0} + set_instance_parameter_value emif_fm_0 {PHY_RLD3_IO_VOLTAGE} {1.2} + set_instance_parameter_value emif_fm_0 {PHY_RLD3_MEM_CLK_FREQ_MHZ} {1066.667} + set_instance_parameter_value emif_fm_0 {PHY_RLD3_MIMIC_HPS_EMIF} {0} + set_instance_parameter_value emif_fm_0 {PHY_RLD3_RATE_ENUM} {RATE_QUARTER} + set_instance_parameter_value emif_fm_0 {PHY_RLD3_REF_CLK_JITTER_PS} {10.0} + set_instance_parameter_value emif_fm_0 {PHY_RLD3_USER_AC_DEEMPHASIS_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_RLD3_USER_AC_IO_STD_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_RLD3_USER_AC_MODE_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_RLD3_USER_AC_SLEW_RATE_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_RLD3_USER_AUTO_STARTING_VREFIN_EN} {1} + set_instance_parameter_value emif_fm_0 {PHY_RLD3_USER_CK_DEEMPHASIS_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_RLD3_USER_CK_IO_STD_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_RLD3_USER_CK_MODE_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_RLD3_USER_CK_SLEW_RATE_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_RLD3_USER_DATA_IN_MODE_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_RLD3_USER_DATA_IO_STD_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_RLD3_USER_DATA_OUT_DEEMPHASIS_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_RLD3_USER_DATA_OUT_MODE_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_RLD3_USER_DATA_OUT_SLEW_RATE_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_RLD3_USER_DLL_CORE_UPDN_EN} {0} + set_instance_parameter_value emif_fm_0 {PHY_RLD3_USER_PERIODIC_OCT_RECAL_ENUM} {PERIODIC_OCT_RECAL_AUTO} + set_instance_parameter_value emif_fm_0 {PHY_RLD3_USER_PING_PONG_EN} {0} + set_instance_parameter_value emif_fm_0 {PHY_RLD3_USER_PLL_REF_CLK_IO_STD_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_RLD3_USER_REF_CLK_FREQ_MHZ} {-1.0} + set_instance_parameter_value emif_fm_0 {PHY_RLD3_USER_RZQ_IO_STD_ENUM} {unset} + set_instance_parameter_value emif_fm_0 {PHY_RLD3_USER_STARTING_VREFIN} {70.0} + set_instance_parameter_value emif_fm_0 {PLL_ADD_EXTRA_CLKS} {0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_0} {50.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_1} {50.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_2} {50.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_3} {50.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_4} {50.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_5} {50.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_6} {50.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_7} {50.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_8} {50.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_0} {50.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_1} {50.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_2} {50.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_3} {50.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_4} {50.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_5} {50.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_6} {50.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_7} {50.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_8} {50.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_0} {0.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_1} {0.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_2} {0.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_3} {0.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_4} {0.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_5} {0.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_6} {0.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_7} {0.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_8} {0.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_0} {0.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_1} {0.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_2} {0.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_3} {0.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_4} {0.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_5} {0.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_6} {0.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_7} {0.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_8} {0.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_0} {0.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_1} {0.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_2} {0.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_3} {0.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_4} {0.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_5} {0.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_6} {0.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_7} {0.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_8} {0.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_0} {50.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_1} {50.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_2} {50.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_3} {50.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_4} {50.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_5} {50.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_6} {50.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_7} {50.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_8} {50.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_0} {0.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_1} {0.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_2} {0.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_3} {0.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_4} {0.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_5} {0.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_6} {0.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_7} {0.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_8} {0.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_DESIRED_PHASE_GUI_0} {0.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_DESIRED_PHASE_GUI_1} {0.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_DESIRED_PHASE_GUI_2} {0.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_DESIRED_PHASE_GUI_3} {0.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_DESIRED_PHASE_GUI_4} {0.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_DESIRED_PHASE_GUI_5} {0.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_DESIRED_PHASE_GUI_6} {0.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_DESIRED_PHASE_GUI_7} {0.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_DESIRED_PHASE_GUI_8} {0.0} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_0} {ps} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_1} {ps} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_2} {ps} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_3} {ps} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_4} {ps} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_5} {ps} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_6} {ps} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_7} {ps} + set_instance_parameter_value emif_fm_0 {PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_8} {ps} + set_instance_parameter_value emif_fm_0 {PLL_USER_NUM_OF_EXTRA_CLKS} {0} + set_instance_parameter_value emif_fm_0 {PROTOCOL_ENUM} {PROTOCOL_DDR4} + set_instance_parameter_value emif_fm_0 {SHORT_QSYS_INTERFACE_NAMES} {1} + set_instance_property emif_fm_0 AUTO_EXPORT true + + # add wirelevel expressions + + # preserve ports for debug + + # add the exports + set_interface_property local_reset_req EXPORT_OF emif_fm_0.local_reset_req + set_interface_property local_reset_status EXPORT_OF emif_fm_0.local_reset_status + set_interface_property pll_ref_clk EXPORT_OF emif_fm_0.pll_ref_clk + set_interface_property pll_locked EXPORT_OF emif_fm_0.pll_locked + set_interface_property oct EXPORT_OF emif_fm_0.oct + set_interface_property mem EXPORT_OF emif_fm_0.mem + set_interface_property status EXPORT_OF emif_fm_0.status + set_interface_property emif_calbus EXPORT_OF emif_fm_0.emif_calbus + set_interface_property emif_calbus_clk EXPORT_OF emif_fm_0.emif_calbus_clk + set_interface_property emif_usr_reset_n EXPORT_OF emif_fm_0.emif_usr_reset_n + set_interface_property emif_usr_clk EXPORT_OF emif_fm_0.emif_usr_clk + set_interface_property ctrl_ecc_user_interrupt_0 EXPORT_OF emif_fm_0.ctrl_ecc_user_interrupt_0 + set_interface_property ctrl_amm_0 EXPORT_OF emif_fm_0.ctrl_amm_0 + + # set values for exposed HDL parameters + + # set the the module properties + set_module_property BONUS_DATA { + + + + + +} + set_module_property FILE {ed_synth_emif_fm_0.ip} + set_module_property GENERATION_ID {0x00000000} + set_module_property NAME {ed_synth_emif_fm_0} + + # save the system + sync_sysinfo_parameters + save_system ed_synth_emif_fm_0 +} + +proc do_set_exported_interface_sysinfo_parameters {} { +} + +# create all the systems, from bottom up +do_create_ed_synth_emif_fm_0 + +# set system info parameters on exported interface, from bottom up +do_set_exported_interface_sysinfo_parameters diff --git a/corev_apu/altera/ip/emif_cal.tcl b/corev_apu/altera/ip/emif_cal.tcl new file mode 100644 index 0000000000..97f7a6f426 --- /dev/null +++ b/corev_apu/altera/ip/emif_cal.tcl @@ -0,0 +1,66 @@ +# Quartus Pro License required to use this file +package require -exact qsys 24.1 + +# create the system "emif_cal" +proc do_create_emif_cal {} { + # create the system + create_system emif_cal + set_project_property BOARD {default} + set_project_property DEVICE {AGFB014R24B2E2V} + set_project_property DEVICE_FAMILY {Agilex 7} + set_project_property HIDE_FROM_IP_CATALOG {true} + set_use_testbench_naming_pattern 0 {} + + # add HDL parameters + + # add the components + add_instance emif_cal_0 altera_emif_cal 2.7.4 + set_instance_parameter_value emif_cal_0 {AXM_ID_NUM} {0} + set_instance_parameter_value emif_cal_0 {DIAG_ENABLE_JTAG_UART} {0} + set_instance_parameter_value emif_cal_0 {DIAG_EXPORT_SEQ_AVALON_SLAVE} {CAL_DEBUG_EXPORT_MODE_DISABLED} + set_instance_parameter_value emif_cal_0 {DIAG_EXPORT_VJI} {0} + set_instance_parameter_value emif_cal_0 {DIAG_EXTRA_CONFIGS} {} + set_instance_parameter_value emif_cal_0 {DIAG_SIM_CAL_MODE_ENUM} {SIM_CAL_MODE_SKIP} + set_instance_parameter_value emif_cal_0 {DIAG_SIM_VERBOSE} {0} + set_instance_parameter_value emif_cal_0 {DIAG_SYNTH_FOR_SIM} {0} + set_instance_parameter_value emif_cal_0 {ENABLE_DDRT} {0} + set_instance_parameter_value emif_cal_0 {NUM_CALBUS_INTERFACE} {1} + set_instance_parameter_value emif_cal_0 {PHY_DDRT_EXPORT_CLK_STP_IF} {0} + set_instance_parameter_value emif_cal_0 {SHORT_QSYS_INTERFACE_NAMES} {1} + set_instance_property emif_cal_0 AUTO_EXPORT true + + # add wirelevel expressions + + # preserve ports for debug + + # add the exports + set_interface_property emif_calbus_0 EXPORT_OF emif_cal_0.emif_calbus_0 + set_interface_property emif_calbus_clk EXPORT_OF emif_cal_0.emif_calbus_clk + + # set values for exposed HDL parameters + + # set the the module properties + set_module_property BONUS_DATA { + + + + + +} + set_module_property FILE {emif_cal.ip} + set_module_property GENERATION_ID {0x00000000} + set_module_property NAME {emif_cal} + + # save the system + sync_sysinfo_parameters + save_system emif_cal +} + +proc do_set_exported_interface_sysinfo_parameters {} { +} + +# create all the systems, from bottom up +do_create_emif_cal + +# set system info parameters on exported interface, from bottom up +do_set_exported_interface_sysinfo_parameters diff --git a/corev_apu/altera/ip/iddr_intel.tcl b/corev_apu/altera/ip/iddr_intel.tcl new file mode 100644 index 0000000000..5dfcca21f8 --- /dev/null +++ b/corev_apu/altera/ip/iddr_intel.tcl @@ -0,0 +1,74 @@ +# Quartus Pro License required to use this file +package require -exact qsys 24.1 + +# create the system "iddr_intel" +proc do_create_iddr_intel {} { + # create the system + create_system iddr_intel + set_project_property BOARD {default} + set_project_property DEVICE {AGFB014R24B2E2V} + set_project_property DEVICE_FAMILY {Agilex 7} + set_project_property HIDE_FROM_IP_CATALOG {true} + set_use_testbench_naming_pattern 0 {} + + # add HDL parameters + + # add the components + add_instance gpio_0 altera_gpio 22.1.0 + set_instance_parameter_value gpio_0 {EXT_DRIVER_PARAM} {0} + set_instance_parameter_value gpio_0 {GENERATE_SDC_FILE} {0} + set_instance_parameter_value gpio_0 {IP_MIGRATE_PORT_MAP_FILE} {altddio_bidir_port_map.csv} + set_instance_parameter_value gpio_0 {PIN_TYPE_GUI} {Input} + set_instance_parameter_value gpio_0 {SIZE} {1} + set_instance_parameter_value gpio_0 {gui_areset_mode} {None} + set_instance_parameter_value gpio_0 {gui_bus_hold} {0} + set_instance_parameter_value gpio_0 {gui_ddio_with_delay} {0} + set_instance_parameter_value gpio_0 {gui_diff_buff} {0} + set_instance_parameter_value gpio_0 {gui_enable_cke} {0} + set_instance_parameter_value gpio_0 {gui_enable_migratable_port_names} {0} + set_instance_parameter_value gpio_0 {gui_enable_termination_ports} {0} + set_instance_parameter_value gpio_0 {gui_hr_logic} {0} + set_instance_parameter_value gpio_0 {gui_io_reg_mode} {DDIO} + set_instance_parameter_value gpio_0 {gui_open_drain} {0} + set_instance_parameter_value gpio_0 {gui_pseudo_diff} {0} + set_instance_parameter_value gpio_0 {gui_separate_io_clks} {0} + set_instance_parameter_value gpio_0 {gui_sreset_mode} {None} + set_instance_parameter_value gpio_0 {gui_use_oe} {0} + set_instance_property gpio_0 AUTO_EXPORT true + + # add wirelevel expressions + + # preserve ports for debug + + # add the exports + set_interface_property ck EXPORT_OF gpio_0.ck + set_interface_property dout EXPORT_OF gpio_0.dout + set_interface_property pad_in EXPORT_OF gpio_0.pad_in + + # set values for exposed HDL parameters + + # set the the module properties + set_module_property BONUS_DATA { + + + + + +} + set_module_property FILE {iddr_intel.ip} + set_module_property GENERATION_ID {0x00000000} + set_module_property NAME {iddr_intel} + + # save the system + sync_sysinfo_parameters + save_system iddr_intel +} + +proc do_set_exported_interface_sysinfo_parameters {} { +} + +# create all the systems, from bottom up +do_create_iddr_intel + +# set system info parameters on exported interface, from bottom up +do_set_exported_interface_sysinfo_parameters diff --git a/corev_apu/altera/ip/interconnect.tcl b/corev_apu/altera/ip/interconnect.tcl new file mode 100644 index 0000000000..2cc81bd0b5 --- /dev/null +++ b/corev_apu/altera/ip/interconnect.tcl @@ -0,0 +1,2523 @@ +# Quartus Pro License required to use this file +package require -exact qsys 24.1 + +# create the system "interconnect" +proc do_create_interconnect {} { + # create the system + create_system interconnect + set_project_property BOARD {default} + set_project_property DEVICE {AGFB014R24B2E2V} + set_project_property DEVICE_FAMILY {Agilex 7} + set_project_property HIDE_FROM_IP_CATALOG {false} + set_use_testbench_naming_pattern 0 {} + + # add HDL parameters + + # add the components + add_component axi_bridge_0 ip/interconnect/interconnect_axi_bridge_0.ip altera_axi_bridge axi_bridge_0 19.4.0 + load_component axi_bridge_0 + set_component_parameter_value ACE_LITE_SUPPORT {0} + set_component_parameter_value ADDR_WIDTH {64} + set_component_parameter_value AXI_VERSION {AXI4} + set_component_parameter_value BACKPRESSURE_DURING_RESET {0} + set_component_parameter_value COMBINED_ACCEPTANCE_CAPABILITY {16} + set_component_parameter_value COMBINED_ISSUING_CAPABILITY {16} + set_component_parameter_value DATA_WIDTH {64} + set_component_parameter_value ENABLE_CONCURRENT_SUBORDINATE_ACCESS {0} + set_component_parameter_value ENABLE_OOO {0} + set_component_parameter_value M0_ID_WIDTH {8} + set_component_parameter_value NO_REPEATED_IDS_BETWEEN_SUBORDINATES {0} + set_component_parameter_value READ_ACCEPTANCE_CAPABILITY {16} + set_component_parameter_value READ_ADDR_USER_WIDTH {32} + set_component_parameter_value READ_DATA_REORDERING_DEPTH {1} + set_component_parameter_value READ_DATA_USER_WIDTH {32} + set_component_parameter_value READ_ISSUING_CAPABILITY {16} + set_component_parameter_value S0_ID_WIDTH {8} + set_component_parameter_value SYNC_RESET {0} + set_component_parameter_value USE_M0_ARBURST {1} + set_component_parameter_value USE_M0_ARCACHE {1} + set_component_parameter_value USE_M0_ARID {1} + set_component_parameter_value USE_M0_ARLEN {1} + set_component_parameter_value USE_M0_ARLOCK {1} + set_component_parameter_value USE_M0_ARQOS {0} + set_component_parameter_value USE_M0_ARREGION {0} + set_component_parameter_value USE_M0_ARSIZE {1} + set_component_parameter_value USE_M0_ARUSER {0} + set_component_parameter_value USE_M0_AWBURST {1} + set_component_parameter_value USE_M0_AWCACHE {1} + set_component_parameter_value USE_M0_AWID {1} + set_component_parameter_value USE_M0_AWLEN {1} + set_component_parameter_value USE_M0_AWLOCK {1} + set_component_parameter_value USE_M0_AWQOS {0} + set_component_parameter_value USE_M0_AWREGION {0} + set_component_parameter_value USE_M0_AWSIZE {1} + set_component_parameter_value USE_M0_AWUSER {0} + set_component_parameter_value USE_M0_BID {1} + set_component_parameter_value USE_M0_BRESP {1} + set_component_parameter_value USE_M0_BUSER {0} + set_component_parameter_value USE_M0_RID {1} + set_component_parameter_value USE_M0_RLAST {1} + set_component_parameter_value USE_M0_RRESP {1} + set_component_parameter_value USE_M0_RUSER {0} + set_component_parameter_value USE_M0_WSTRB {1} + set_component_parameter_value USE_M0_WUSER {0} + set_component_parameter_value USE_PIPELINE {1} + set_component_parameter_value USE_S0_ARCACHE {1} + set_component_parameter_value USE_S0_ARLOCK {1} + set_component_parameter_value USE_S0_ARPROT {1} + set_component_parameter_value USE_S0_ARQOS {0} + set_component_parameter_value USE_S0_ARREGION {0} + set_component_parameter_value USE_S0_ARUSER {0} + set_component_parameter_value USE_S0_AWCACHE {1} + set_component_parameter_value USE_S0_AWLOCK {1} + set_component_parameter_value USE_S0_AWPROT {1} + set_component_parameter_value USE_S0_AWQOS {0} + set_component_parameter_value USE_S0_AWREGION {0} + set_component_parameter_value USE_S0_AWUSER {0} + set_component_parameter_value USE_S0_BRESP {1} + set_component_parameter_value USE_S0_BUSER {0} + set_component_parameter_value USE_S0_RRESP {1} + set_component_parameter_value USE_S0_RUSER {0} + set_component_parameter_value USE_S0_WLAST {1} + set_component_parameter_value USE_S0_WUSER {0} + set_component_parameter_value WRITE_ACCEPTANCE_CAPABILITY {16} + set_component_parameter_value WRITE_ADDR_USER_WIDTH {32} + set_component_parameter_value WRITE_DATA_USER_WIDTH {32} + set_component_parameter_value WRITE_ISSUING_CAPABILITY {16} + set_component_parameter_value WRITE_RESP_USER_WIDTH {32} + set_component_project_property HIDE_FROM_IP_CATALOG {false} + save_component + load_instantiation axi_bridge_0 + remove_instantiation_interfaces_and_ports + set_instantiation_assignment_value embeddedsw.dts.compatible {simple-bus} + set_instantiation_assignment_value embeddedsw.dts.group {bridge} + set_instantiation_assignment_value embeddedsw.dts.name {bridge} + set_instantiation_assignment_value embeddedsw.dts.vendor {altr} + add_instantiation_interface clk clock INPUT + set_instantiation_interface_parameter_value clk clockRate {0} + set_instantiation_interface_parameter_value clk externallyDriven {false} + set_instantiation_interface_parameter_value clk ptfSchematicName {} + add_instantiation_interface_port clk aclk clk 1 STD_LOGIC Input + add_instantiation_interface clk_reset reset INPUT + set_instantiation_interface_parameter_value clk_reset associatedClock {clk} + set_instantiation_interface_parameter_value clk_reset synchronousEdges {DEASSERT} + add_instantiation_interface_port clk_reset aresetn reset_n 1 STD_LOGIC Input + add_instantiation_interface s0 axi4 INPUT + set_instantiation_interface_parameter_value s0 associatedClock {clk} + set_instantiation_interface_parameter_value s0 associatedReset {clk_reset} + set_instantiation_interface_parameter_value s0 bridgesToMaster {m0} + set_instantiation_interface_parameter_value s0 combinedAcceptanceCapability {16} + set_instantiation_interface_parameter_value s0 dfhFeatureGuid {0} + set_instantiation_interface_parameter_value s0 dfhFeatureId {35} + set_instantiation_interface_parameter_value s0 dfhFeatureMajorVersion {0} + set_instantiation_interface_parameter_value s0 dfhFeatureMinorVersion {0} + set_instantiation_interface_parameter_value s0 dfhFeatureType {3} + set_instantiation_interface_parameter_value s0 dfhGroupId {0} + set_instantiation_interface_parameter_value s0 dfhParameterData {} + set_instantiation_interface_parameter_value s0 dfhParameterDataLength {} + set_instantiation_interface_parameter_value s0 dfhParameterId {} + set_instantiation_interface_parameter_value s0 dfhParameterName {} + set_instantiation_interface_parameter_value s0 dfhParameterVersion {} + set_instantiation_interface_parameter_value s0 maximumOutstandingReads {1} + set_instantiation_interface_parameter_value s0 maximumOutstandingTransactions {1} + set_instantiation_interface_parameter_value s0 maximumOutstandingWrites {1} + set_instantiation_interface_parameter_value s0 poison {false} + set_instantiation_interface_parameter_value s0 readAcceptanceCapability {16} + set_instantiation_interface_parameter_value s0 readDataReorderingDepth {1} + set_instantiation_interface_parameter_value s0 traceSignals {false} + set_instantiation_interface_parameter_value s0 trustzoneAware {true} + set_instantiation_interface_parameter_value s0 uniqueIdSupport {false} + set_instantiation_interface_parameter_value s0 wakeupSignals {false} + set_instantiation_interface_parameter_value s0 writeAcceptanceCapability {16} + set_instantiation_interface_sysinfo_parameter_value s0 address_map {} + set_instantiation_interface_sysinfo_parameter_value s0 address_width {} + set_instantiation_interface_sysinfo_parameter_value s0 max_slave_data_width {} + add_instantiation_interface_port s0 s0_awid awid 8 STD_LOGIC_VECTOR Input + add_instantiation_interface_port s0 s0_awaddr awaddr 64 STD_LOGIC_VECTOR Input + add_instantiation_interface_port s0 s0_awlen awlen 8 STD_LOGIC_VECTOR Input + add_instantiation_interface_port s0 s0_awsize awsize 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port s0 s0_awburst awburst 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port s0 s0_awlock awlock 1 STD_LOGIC_VECTOR Input + add_instantiation_interface_port s0 s0_awcache awcache 4 STD_LOGIC_VECTOR Input + add_instantiation_interface_port s0 s0_awprot awprot 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port s0 s0_awvalid awvalid 1 STD_LOGIC Input + add_instantiation_interface_port s0 s0_awready awready 1 STD_LOGIC Output + add_instantiation_interface_port s0 s0_wdata wdata 64 STD_LOGIC_VECTOR Input + add_instantiation_interface_port s0 s0_wstrb wstrb 8 STD_LOGIC_VECTOR Input + add_instantiation_interface_port s0 s0_wlast wlast 1 STD_LOGIC Input + add_instantiation_interface_port s0 s0_wvalid wvalid 1 STD_LOGIC Input + add_instantiation_interface_port s0 s0_wready wready 1 STD_LOGIC Output + add_instantiation_interface_port s0 s0_bid bid 8 STD_LOGIC_VECTOR Output + add_instantiation_interface_port s0 s0_bresp bresp 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port s0 s0_bvalid bvalid 1 STD_LOGIC Output + add_instantiation_interface_port s0 s0_bready bready 1 STD_LOGIC Input + add_instantiation_interface_port s0 s0_arid arid 8 STD_LOGIC_VECTOR Input + add_instantiation_interface_port s0 s0_araddr araddr 64 STD_LOGIC_VECTOR Input + add_instantiation_interface_port s0 s0_arlen arlen 8 STD_LOGIC_VECTOR Input + add_instantiation_interface_port s0 s0_arsize arsize 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port s0 s0_arburst arburst 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port s0 s0_arlock arlock 1 STD_LOGIC_VECTOR Input + add_instantiation_interface_port s0 s0_arcache arcache 4 STD_LOGIC_VECTOR Input + add_instantiation_interface_port s0 s0_arprot arprot 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port s0 s0_arvalid arvalid 1 STD_LOGIC Input + add_instantiation_interface_port s0 s0_arready arready 1 STD_LOGIC Output + add_instantiation_interface_port s0 s0_rid rid 8 STD_LOGIC_VECTOR Output + add_instantiation_interface_port s0 s0_rdata rdata 64 STD_LOGIC_VECTOR Output + add_instantiation_interface_port s0 s0_rresp rresp 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port s0 s0_rlast rlast 1 STD_LOGIC Output + add_instantiation_interface_port s0 s0_rvalid rvalid 1 STD_LOGIC Output + add_instantiation_interface_port s0 s0_rready rready 1 STD_LOGIC Input + add_instantiation_interface m0 axi4 OUTPUT + set_instantiation_interface_parameter_value m0 associatedClock {clk} + set_instantiation_interface_parameter_value m0 associatedReset {clk_reset} + set_instantiation_interface_parameter_value m0 combinedIssuingCapability {16} + set_instantiation_interface_parameter_value m0 issuesFIXEDBursts {true} + set_instantiation_interface_parameter_value m0 issuesINCRBursts {true} + set_instantiation_interface_parameter_value m0 issuesWRAPBursts {true} + set_instantiation_interface_parameter_value m0 maximumOutstandingReads {1} + set_instantiation_interface_parameter_value m0 maximumOutstandingTransactions {1} + set_instantiation_interface_parameter_value m0 maximumOutstandingWrites {1} + set_instantiation_interface_parameter_value m0 poison {false} + set_instantiation_interface_parameter_value m0 readIssuingCapability {16} + set_instantiation_interface_parameter_value m0 traceSignals {false} + set_instantiation_interface_parameter_value m0 trustzoneAware {true} + set_instantiation_interface_parameter_value m0 uniqueIdSupport {false} + set_instantiation_interface_parameter_value m0 wakeupSignals {false} + set_instantiation_interface_parameter_value m0 writeIssuingCapability {16} + add_instantiation_interface_port m0 m0_awid awid 8 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 m0_awaddr awaddr 64 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 m0_awlen awlen 8 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 m0_awsize awsize 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 m0_awburst awburst 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 m0_awlock awlock 1 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 m0_awcache awcache 4 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 m0_awprot awprot 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 m0_awvalid awvalid 1 STD_LOGIC Output + add_instantiation_interface_port m0 m0_awready awready 1 STD_LOGIC Input + add_instantiation_interface_port m0 m0_wdata wdata 64 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 m0_wstrb wstrb 8 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 m0_wlast wlast 1 STD_LOGIC Output + add_instantiation_interface_port m0 m0_wvalid wvalid 1 STD_LOGIC Output + add_instantiation_interface_port m0 m0_wready wready 1 STD_LOGIC Input + add_instantiation_interface_port m0 m0_bid bid 8 STD_LOGIC_VECTOR Input + add_instantiation_interface_port m0 m0_bresp bresp 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port m0 m0_bvalid bvalid 1 STD_LOGIC Input + add_instantiation_interface_port m0 m0_bready bready 1 STD_LOGIC Output + add_instantiation_interface_port m0 m0_arid arid 8 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 m0_araddr araddr 64 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 m0_arlen arlen 8 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 m0_arsize arsize 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 m0_arburst arburst 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 m0_arlock arlock 1 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 m0_arcache arcache 4 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 m0_arprot arprot 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 m0_arvalid arvalid 1 STD_LOGIC Output + add_instantiation_interface_port m0 m0_arready arready 1 STD_LOGIC Input + add_instantiation_interface_port m0 m0_rid rid 8 STD_LOGIC_VECTOR Input + add_instantiation_interface_port m0 m0_rdata rdata 64 STD_LOGIC_VECTOR Input + add_instantiation_interface_port m0 m0_rresp rresp 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port m0 m0_rlast rlast 1 STD_LOGIC Input + add_instantiation_interface_port m0 m0_rvalid rvalid 1 STD_LOGIC Input + add_instantiation_interface_port m0 m0_rready rready 1 STD_LOGIC Output + save_instantiation + add_component axi_bridge_1 ip/interconnect/interconnect_axi_bridge_0.ip altera_axi_bridge axi_bridge_0 19.4.0 + load_component axi_bridge_1 + set_component_parameter_value ACE_LITE_SUPPORT {0} + set_component_parameter_value ADDR_WIDTH {64} + set_component_parameter_value AXI_VERSION {AXI4} + set_component_parameter_value BACKPRESSURE_DURING_RESET {0} + set_component_parameter_value COMBINED_ACCEPTANCE_CAPABILITY {16} + set_component_parameter_value COMBINED_ISSUING_CAPABILITY {16} + set_component_parameter_value DATA_WIDTH {64} + set_component_parameter_value ENABLE_CONCURRENT_SUBORDINATE_ACCESS {0} + set_component_parameter_value ENABLE_OOO {0} + set_component_parameter_value M0_ID_WIDTH {8} + set_component_parameter_value NO_REPEATED_IDS_BETWEEN_SUBORDINATES {0} + set_component_parameter_value READ_ACCEPTANCE_CAPABILITY {16} + set_component_parameter_value READ_ADDR_USER_WIDTH {32} + set_component_parameter_value READ_DATA_REORDERING_DEPTH {1} + set_component_parameter_value READ_DATA_USER_WIDTH {32} + set_component_parameter_value READ_ISSUING_CAPABILITY {16} + set_component_parameter_value S0_ID_WIDTH {8} + set_component_parameter_value SYNC_RESET {0} + set_component_parameter_value USE_M0_ARBURST {1} + set_component_parameter_value USE_M0_ARCACHE {1} + set_component_parameter_value USE_M0_ARID {1} + set_component_parameter_value USE_M0_ARLEN {1} + set_component_parameter_value USE_M0_ARLOCK {1} + set_component_parameter_value USE_M0_ARQOS {0} + set_component_parameter_value USE_M0_ARREGION {0} + set_component_parameter_value USE_M0_ARSIZE {1} + set_component_parameter_value USE_M0_ARUSER {0} + set_component_parameter_value USE_M0_AWBURST {1} + set_component_parameter_value USE_M0_AWCACHE {1} + set_component_parameter_value USE_M0_AWID {1} + set_component_parameter_value USE_M0_AWLEN {1} + set_component_parameter_value USE_M0_AWLOCK {1} + set_component_parameter_value USE_M0_AWQOS {0} + set_component_parameter_value USE_M0_AWREGION {0} + set_component_parameter_value USE_M0_AWSIZE {1} + set_component_parameter_value USE_M0_AWUSER {0} + set_component_parameter_value USE_M0_BID {1} + set_component_parameter_value USE_M0_BRESP {1} + set_component_parameter_value USE_M0_BUSER {0} + set_component_parameter_value USE_M0_RID {1} + set_component_parameter_value USE_M0_RLAST {1} + set_component_parameter_value USE_M0_RRESP {1} + set_component_parameter_value USE_M0_RUSER {0} + set_component_parameter_value USE_M0_WSTRB {1} + set_component_parameter_value USE_M0_WUSER {0} + set_component_parameter_value USE_PIPELINE {1} + set_component_parameter_value USE_S0_ARCACHE {1} + set_component_parameter_value USE_S0_ARLOCK {1} + set_component_parameter_value USE_S0_ARPROT {1} + set_component_parameter_value USE_S0_ARQOS {0} + set_component_parameter_value USE_S0_ARREGION {0} + set_component_parameter_value USE_S0_ARUSER {0} + set_component_parameter_value USE_S0_AWCACHE {1} + set_component_parameter_value USE_S0_AWLOCK {1} + set_component_parameter_value USE_S0_AWPROT {1} + set_component_parameter_value USE_S0_AWQOS {0} + set_component_parameter_value USE_S0_AWREGION {0} + set_component_parameter_value USE_S0_AWUSER {0} + set_component_parameter_value USE_S0_BRESP {1} + set_component_parameter_value USE_S0_BUSER {0} + set_component_parameter_value USE_S0_RRESP {1} + set_component_parameter_value USE_S0_RUSER {0} + set_component_parameter_value USE_S0_WLAST {1} + set_component_parameter_value USE_S0_WUSER {0} + set_component_parameter_value WRITE_ACCEPTANCE_CAPABILITY {16} + set_component_parameter_value WRITE_ADDR_USER_WIDTH {32} + set_component_parameter_value WRITE_DATA_USER_WIDTH {32} + set_component_parameter_value WRITE_ISSUING_CAPABILITY {16} + set_component_parameter_value WRITE_RESP_USER_WIDTH {32} + set_component_project_property HIDE_FROM_IP_CATALOG {false} + save_component + load_instantiation axi_bridge_1 + remove_instantiation_interfaces_and_ports + set_instantiation_assignment_value embeddedsw.dts.compatible {simple-bus} + set_instantiation_assignment_value embeddedsw.dts.group {bridge} + set_instantiation_assignment_value embeddedsw.dts.name {bridge} + set_instantiation_assignment_value embeddedsw.dts.vendor {altr} + add_instantiation_interface clk clock INPUT + set_instantiation_interface_parameter_value clk clockRate {0} + set_instantiation_interface_parameter_value clk externallyDriven {false} + set_instantiation_interface_parameter_value clk ptfSchematicName {} + add_instantiation_interface_port clk aclk clk 1 STD_LOGIC Input + add_instantiation_interface clk_reset reset INPUT + set_instantiation_interface_parameter_value clk_reset associatedClock {clk} + set_instantiation_interface_parameter_value clk_reset synchronousEdges {DEASSERT} + add_instantiation_interface_port clk_reset aresetn reset_n 1 STD_LOGIC Input + add_instantiation_interface s0 axi4 INPUT + set_instantiation_interface_parameter_value s0 associatedClock {clk} + set_instantiation_interface_parameter_value s0 associatedReset {clk_reset} + set_instantiation_interface_parameter_value s0 bridgesToMaster {m0} + set_instantiation_interface_parameter_value s0 combinedAcceptanceCapability {16} + set_instantiation_interface_parameter_value s0 dfhFeatureGuid {0} + set_instantiation_interface_parameter_value s0 dfhFeatureId {35} + set_instantiation_interface_parameter_value s0 dfhFeatureMajorVersion {0} + set_instantiation_interface_parameter_value s0 dfhFeatureMinorVersion {0} + set_instantiation_interface_parameter_value s0 dfhFeatureType {3} + set_instantiation_interface_parameter_value s0 dfhGroupId {0} + set_instantiation_interface_parameter_value s0 dfhParameterData {} + set_instantiation_interface_parameter_value s0 dfhParameterDataLength {} + set_instantiation_interface_parameter_value s0 dfhParameterId {} + set_instantiation_interface_parameter_value s0 dfhParameterName {} + set_instantiation_interface_parameter_value s0 dfhParameterVersion {} + set_instantiation_interface_parameter_value s0 maximumOutstandingReads {1} + set_instantiation_interface_parameter_value s0 maximumOutstandingTransactions {1} + set_instantiation_interface_parameter_value s0 maximumOutstandingWrites {1} + set_instantiation_interface_parameter_value s0 poison {false} + set_instantiation_interface_parameter_value s0 readAcceptanceCapability {16} + set_instantiation_interface_parameter_value s0 readDataReorderingDepth {1} + set_instantiation_interface_parameter_value s0 traceSignals {false} + set_instantiation_interface_parameter_value s0 trustzoneAware {true} + set_instantiation_interface_parameter_value s0 uniqueIdSupport {false} + set_instantiation_interface_parameter_value s0 wakeupSignals {false} + set_instantiation_interface_parameter_value s0 writeAcceptanceCapability {16} + set_instantiation_interface_sysinfo_parameter_value s0 address_map {} + set_instantiation_interface_sysinfo_parameter_value s0 address_width {} + set_instantiation_interface_sysinfo_parameter_value s0 max_slave_data_width {} + add_instantiation_interface_port s0 s0_awid awid 8 STD_LOGIC_VECTOR Input + add_instantiation_interface_port s0 s0_awaddr awaddr 64 STD_LOGIC_VECTOR Input + add_instantiation_interface_port s0 s0_awlen awlen 8 STD_LOGIC_VECTOR Input + add_instantiation_interface_port s0 s0_awsize awsize 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port s0 s0_awburst awburst 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port s0 s0_awlock awlock 1 STD_LOGIC_VECTOR Input + add_instantiation_interface_port s0 s0_awcache awcache 4 STD_LOGIC_VECTOR Input + add_instantiation_interface_port s0 s0_awprot awprot 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port s0 s0_awvalid awvalid 1 STD_LOGIC Input + add_instantiation_interface_port s0 s0_awready awready 1 STD_LOGIC Output + add_instantiation_interface_port s0 s0_wdata wdata 64 STD_LOGIC_VECTOR Input + add_instantiation_interface_port s0 s0_wstrb wstrb 8 STD_LOGIC_VECTOR Input + add_instantiation_interface_port s0 s0_wlast wlast 1 STD_LOGIC Input + add_instantiation_interface_port s0 s0_wvalid wvalid 1 STD_LOGIC Input + add_instantiation_interface_port s0 s0_wready wready 1 STD_LOGIC Output + add_instantiation_interface_port s0 s0_bid bid 8 STD_LOGIC_VECTOR Output + add_instantiation_interface_port s0 s0_bresp bresp 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port s0 s0_bvalid bvalid 1 STD_LOGIC Output + add_instantiation_interface_port s0 s0_bready bready 1 STD_LOGIC Input + add_instantiation_interface_port s0 s0_arid arid 8 STD_LOGIC_VECTOR Input + add_instantiation_interface_port s0 s0_araddr araddr 64 STD_LOGIC_VECTOR Input + add_instantiation_interface_port s0 s0_arlen arlen 8 STD_LOGIC_VECTOR Input + add_instantiation_interface_port s0 s0_arsize arsize 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port s0 s0_arburst arburst 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port s0 s0_arlock arlock 1 STD_LOGIC_VECTOR Input + add_instantiation_interface_port s0 s0_arcache arcache 4 STD_LOGIC_VECTOR Input + add_instantiation_interface_port s0 s0_arprot arprot 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port s0 s0_arvalid arvalid 1 STD_LOGIC Input + add_instantiation_interface_port s0 s0_arready arready 1 STD_LOGIC Output + add_instantiation_interface_port s0 s0_rid rid 8 STD_LOGIC_VECTOR Output + add_instantiation_interface_port s0 s0_rdata rdata 64 STD_LOGIC_VECTOR Output + add_instantiation_interface_port s0 s0_rresp rresp 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port s0 s0_rlast rlast 1 STD_LOGIC Output + add_instantiation_interface_port s0 s0_rvalid rvalid 1 STD_LOGIC Output + add_instantiation_interface_port s0 s0_rready rready 1 STD_LOGIC Input + add_instantiation_interface m0 axi4 OUTPUT + set_instantiation_interface_parameter_value m0 associatedClock {clk} + set_instantiation_interface_parameter_value m0 associatedReset {clk_reset} + set_instantiation_interface_parameter_value m0 combinedIssuingCapability {16} + set_instantiation_interface_parameter_value m0 issuesFIXEDBursts {true} + set_instantiation_interface_parameter_value m0 issuesINCRBursts {true} + set_instantiation_interface_parameter_value m0 issuesWRAPBursts {true} + set_instantiation_interface_parameter_value m0 maximumOutstandingReads {1} + set_instantiation_interface_parameter_value m0 maximumOutstandingTransactions {1} + set_instantiation_interface_parameter_value m0 maximumOutstandingWrites {1} + set_instantiation_interface_parameter_value m0 poison {false} + set_instantiation_interface_parameter_value m0 readIssuingCapability {16} + set_instantiation_interface_parameter_value m0 traceSignals {false} + set_instantiation_interface_parameter_value m0 trustzoneAware {true} + set_instantiation_interface_parameter_value m0 uniqueIdSupport {false} + set_instantiation_interface_parameter_value m0 wakeupSignals {false} + set_instantiation_interface_parameter_value m0 writeIssuingCapability {16} + add_instantiation_interface_port m0 m0_awid awid 8 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 m0_awaddr awaddr 64 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 m0_awlen awlen 8 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 m0_awsize awsize 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 m0_awburst awburst 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 m0_awlock awlock 1 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 m0_awcache awcache 4 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 m0_awprot awprot 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 m0_awvalid awvalid 1 STD_LOGIC Output + add_instantiation_interface_port m0 m0_awready awready 1 STD_LOGIC Input + add_instantiation_interface_port m0 m0_wdata wdata 64 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 m0_wstrb wstrb 8 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 m0_wlast wlast 1 STD_LOGIC Output + add_instantiation_interface_port m0 m0_wvalid wvalid 1 STD_LOGIC Output + add_instantiation_interface_port m0 m0_wready wready 1 STD_LOGIC Input + add_instantiation_interface_port m0 m0_bid bid 8 STD_LOGIC_VECTOR Input + add_instantiation_interface_port m0 m0_bresp bresp 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port m0 m0_bvalid bvalid 1 STD_LOGIC Input + add_instantiation_interface_port m0 m0_bready bready 1 STD_LOGIC Output + add_instantiation_interface_port m0 m0_arid arid 8 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 m0_araddr araddr 64 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 m0_arlen arlen 8 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 m0_arsize arsize 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 m0_arburst arburst 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 m0_arlock arlock 1 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 m0_arcache arcache 4 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 m0_arprot arprot 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 m0_arvalid arvalid 1 STD_LOGIC Output + add_instantiation_interface_port m0 m0_arready arready 1 STD_LOGIC Input + add_instantiation_interface_port m0 m0_rid rid 8 STD_LOGIC_VECTOR Input + add_instantiation_interface_port m0 m0_rdata rdata 64 STD_LOGIC_VECTOR Input + add_instantiation_interface_port m0 m0_rresp rresp 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port m0 m0_rlast rlast 1 STD_LOGIC Input + add_instantiation_interface_port m0 m0_rvalid rvalid 1 STD_LOGIC Input + add_instantiation_interface_port m0 m0_rready rready 1 STD_LOGIC Output + save_instantiation + add_component emif_cal_0 intel/emif_cal.ip altera_emif_cal emif_cal_0 2.7.4 + load_component emif_cal_0 + set_component_parameter_value AXM_ID_NUM {0} + set_component_parameter_value DIAG_ENABLE_JTAG_UART {0} + set_component_parameter_value DIAG_EXPORT_SEQ_AVALON_SLAVE {CAL_DEBUG_EXPORT_MODE_DISABLED} + set_component_parameter_value DIAG_EXPORT_VJI {0} + set_component_parameter_value DIAG_EXTRA_CONFIGS {} + set_component_parameter_value DIAG_SIM_CAL_MODE_ENUM {SIM_CAL_MODE_SKIP} + set_component_parameter_value DIAG_SIM_VERBOSE {0} + set_component_parameter_value DIAG_SYNTH_FOR_SIM {0} + set_component_parameter_value ENABLE_DDRT {0} + set_component_parameter_value NUM_CALBUS_INTERFACE {1} + set_component_parameter_value PHY_DDRT_EXPORT_CLK_STP_IF {0} + set_component_parameter_value SHORT_QSYS_INTERFACE_NAMES {1} + set_component_project_property HIDE_FROM_IP_CATALOG {true} + save_component + load_instantiation emif_cal_0 + remove_instantiation_interfaces_and_ports + add_instantiation_interface emif_calbus_0 conduit INPUT + set_instantiation_interface_parameter_value emif_calbus_0 associatedClock {emif_calbus_clk} + set_instantiation_interface_parameter_value emif_calbus_0 associatedReset {} + set_instantiation_interface_parameter_value emif_calbus_0 prSafe {false} + add_instantiation_interface_port emif_calbus_0 calbus_read_0 calbus_read 1 STD_LOGIC Output + add_instantiation_interface_port emif_calbus_0 calbus_write_0 calbus_write 1 STD_LOGIC Output + add_instantiation_interface_port emif_calbus_0 calbus_address_0 calbus_address 20 STD_LOGIC_VECTOR Output + add_instantiation_interface_port emif_calbus_0 calbus_wdata_0 calbus_wdata 32 STD_LOGIC_VECTOR Output + add_instantiation_interface_port emif_calbus_0 calbus_rdata_0 calbus_rdata 32 STD_LOGIC_VECTOR Input + add_instantiation_interface_port emif_calbus_0 calbus_seq_param_tbl_0 calbus_seq_param_tbl 4096 STD_LOGIC_VECTOR Input + add_instantiation_interface emif_calbus_clk clock OUTPUT + set_instantiation_interface_parameter_value emif_calbus_clk associatedDirectClock {} + set_instantiation_interface_parameter_value emif_calbus_clk clockRate {0} + set_instantiation_interface_parameter_value emif_calbus_clk clockRateKnown {false} + set_instantiation_interface_parameter_value emif_calbus_clk externallyDriven {false} + set_instantiation_interface_parameter_value emif_calbus_clk ptfSchematicName {} + set_instantiation_interface_sysinfo_parameter_value emif_calbus_clk clock_rate {0} + add_instantiation_interface_port emif_calbus_clk calbus_clk clk 1 STD_LOGIC Output + save_instantiation + add_component emif_fm_0 intel/ed_synth_emif_fm_0.ip altera_emif_fm emif_fm_0 2.7.4 + load_component emif_fm_0 + set_component_parameter_value BOARD_DDR3_AC_TO_CK_SKEW_NS {0.0} + set_component_parameter_value BOARD_DDR3_BRD_SKEW_WITHIN_AC_NS {0.02} + set_component_parameter_value BOARD_DDR3_BRD_SKEW_WITHIN_DQS_NS {0.02} + set_component_parameter_value BOARD_DDR3_DQS_TO_CK_SKEW_NS {0.02} + set_component_parameter_value BOARD_DDR3_IS_SKEW_WITHIN_AC_DESKEWED {1} + set_component_parameter_value BOARD_DDR3_IS_SKEW_WITHIN_DQS_DESKEWED {0} + set_component_parameter_value BOARD_DDR3_MAX_CK_DELAY_NS {0.6} + set_component_parameter_value BOARD_DDR3_MAX_DQS_DELAY_NS {0.6} + set_component_parameter_value BOARD_DDR3_PKG_BRD_SKEW_WITHIN_AC_NS {0.02} + set_component_parameter_value BOARD_DDR3_PKG_BRD_SKEW_WITHIN_DQS_NS {0.02} + set_component_parameter_value BOARD_DDR3_SKEW_BETWEEN_DIMMS_NS {0.05} + set_component_parameter_value BOARD_DDR3_SKEW_BETWEEN_DQS_NS {0.02} + set_component_parameter_value BOARD_DDR3_USER_AC_ISI_NS {0.0} + set_component_parameter_value BOARD_DDR3_USER_AC_SLEW_RATE {2.0} + set_component_parameter_value BOARD_DDR3_USER_CK_SLEW_RATE {4.0} + set_component_parameter_value BOARD_DDR3_USER_RCLK_ISI_NS {0.0} + set_component_parameter_value BOARD_DDR3_USER_RCLK_SLEW_RATE {5.0} + set_component_parameter_value BOARD_DDR3_USER_RDATA_ISI_NS {0.0} + set_component_parameter_value BOARD_DDR3_USER_RDATA_SLEW_RATE {2.5} + set_component_parameter_value BOARD_DDR3_USER_WCLK_ISI_NS {0.0} + set_component_parameter_value BOARD_DDR3_USER_WCLK_SLEW_RATE {4.0} + set_component_parameter_value BOARD_DDR3_USER_WDATA_ISI_NS {0.0} + set_component_parameter_value BOARD_DDR3_USER_WDATA_SLEW_RATE {2.0} + set_component_parameter_value BOARD_DDR3_USE_DEFAULT_ISI_VALUES {1} + set_component_parameter_value BOARD_DDR3_USE_DEFAULT_SLEW_RATES {1} + set_component_parameter_value BOARD_DDR4_AC_TO_CK_SKEW_NS {0.0} + set_component_parameter_value BOARD_DDR4_BRD_SKEW_WITHIN_AC_NS {0.02} + set_component_parameter_value BOARD_DDR4_BRD_SKEW_WITHIN_DQS_NS {0.02} + set_component_parameter_value BOARD_DDR4_DQS_TO_CK_SKEW_NS {0.02} + set_component_parameter_value BOARD_DDR4_IS_SKEW_WITHIN_AC_DESKEWED {0} + set_component_parameter_value BOARD_DDR4_IS_SKEW_WITHIN_DQS_DESKEWED {1} + set_component_parameter_value BOARD_DDR4_MAX_CK_DELAY_NS {0.6} + set_component_parameter_value BOARD_DDR4_MAX_DQS_DELAY_NS {0.6} + set_component_parameter_value BOARD_DDR4_PKG_BRD_SKEW_WITHIN_AC_NS {0.02} + set_component_parameter_value BOARD_DDR4_PKG_BRD_SKEW_WITHIN_DQS_NS {0.02} + set_component_parameter_value BOARD_DDR4_SKEW_BETWEEN_DIMMS_NS {0.05} + set_component_parameter_value BOARD_DDR4_SKEW_BETWEEN_DQS_NS {0.02} + set_component_parameter_value BOARD_DDR4_USER_AC_ISI_NS {0.0} + set_component_parameter_value BOARD_DDR4_USER_AC_SLEW_RATE {2.0} + set_component_parameter_value BOARD_DDR4_USER_CK_SLEW_RATE {4.0} + set_component_parameter_value BOARD_DDR4_USER_RCLK_ISI_NS {0.0} + set_component_parameter_value BOARD_DDR4_USER_RCLK_SLEW_RATE {8.0} + set_component_parameter_value BOARD_DDR4_USER_RDATA_ISI_NS {0.0} + set_component_parameter_value BOARD_DDR4_USER_RDATA_SLEW_RATE {4.0} + set_component_parameter_value BOARD_DDR4_USER_WCLK_ISI_NS {0.0} + set_component_parameter_value BOARD_DDR4_USER_WCLK_SLEW_RATE {4.0} + set_component_parameter_value BOARD_DDR4_USER_WDATA_ISI_NS {0.0} + set_component_parameter_value BOARD_DDR4_USER_WDATA_SLEW_RATE {2.0} + set_component_parameter_value BOARD_DDR4_USE_DEFAULT_ISI_VALUES {1} + set_component_parameter_value BOARD_DDR4_USE_DEFAULT_SLEW_RATES {1} + set_component_parameter_value BOARD_DDRT_AC_TO_CK_SKEW_NS {0.0} + set_component_parameter_value BOARD_DDRT_BRD_SKEW_WITHIN_AC_NS {0.02} + set_component_parameter_value BOARD_DDRT_BRD_SKEW_WITHIN_DQS_NS {0.02} + set_component_parameter_value BOARD_DDRT_DQS_TO_CK_SKEW_NS {0.02} + set_component_parameter_value BOARD_DDRT_IS_SKEW_WITHIN_AC_DESKEWED {0} + set_component_parameter_value BOARD_DDRT_IS_SKEW_WITHIN_DQS_DESKEWED {1} + set_component_parameter_value BOARD_DDRT_MAX_CK_DELAY_NS {0.6} + set_component_parameter_value BOARD_DDRT_MAX_DQS_DELAY_NS {0.6} + set_component_parameter_value BOARD_DDRT_PKG_BRD_SKEW_WITHIN_AC_NS {0.02} + set_component_parameter_value BOARD_DDRT_PKG_BRD_SKEW_WITHIN_DQS_NS {0.02} + set_component_parameter_value BOARD_DDRT_SKEW_BETWEEN_DIMMS_NS {0.05} + set_component_parameter_value BOARD_DDRT_SKEW_BETWEEN_DQS_NS {0.02} + set_component_parameter_value BOARD_DDRT_USER_AC_ISI_NS {0.0} + set_component_parameter_value BOARD_DDRT_USER_AC_SLEW_RATE {2.0} + set_component_parameter_value BOARD_DDRT_USER_CK_SLEW_RATE {4.0} + set_component_parameter_value BOARD_DDRT_USER_RCLK_ISI_NS {0.0} + set_component_parameter_value BOARD_DDRT_USER_RCLK_SLEW_RATE {8.0} + set_component_parameter_value BOARD_DDRT_USER_RDATA_ISI_NS {0.0} + set_component_parameter_value BOARD_DDRT_USER_RDATA_SLEW_RATE {4.0} + set_component_parameter_value BOARD_DDRT_USER_WCLK_ISI_NS {0.0} + set_component_parameter_value BOARD_DDRT_USER_WCLK_SLEW_RATE {4.0} + set_component_parameter_value BOARD_DDRT_USER_WDATA_ISI_NS {0.0} + set_component_parameter_value BOARD_DDRT_USER_WDATA_SLEW_RATE {2.0} + set_component_parameter_value BOARD_DDRT_USE_DEFAULT_ISI_VALUES {1} + set_component_parameter_value BOARD_DDRT_USE_DEFAULT_SLEW_RATES {1} + set_component_parameter_value BOARD_LPDDR3_AC_TO_CK_SKEW_NS {0.0} + set_component_parameter_value BOARD_LPDDR3_BRD_SKEW_WITHIN_AC_NS {0.02} + set_component_parameter_value BOARD_LPDDR3_BRD_SKEW_WITHIN_DQS_NS {0.02} + set_component_parameter_value BOARD_LPDDR3_DQS_TO_CK_SKEW_NS {0.02} + set_component_parameter_value BOARD_LPDDR3_IS_SKEW_WITHIN_AC_DESKEWED {1} + set_component_parameter_value BOARD_LPDDR3_IS_SKEW_WITHIN_DQS_DESKEWED {0} + set_component_parameter_value BOARD_LPDDR3_MAX_CK_DELAY_NS {0.6} + set_component_parameter_value BOARD_LPDDR3_MAX_DQS_DELAY_NS {0.6} + set_component_parameter_value BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_AC_NS {0.02} + set_component_parameter_value BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_DQS_NS {0.02} + set_component_parameter_value BOARD_LPDDR3_SKEW_BETWEEN_DIMMS_NS {0.05} + set_component_parameter_value BOARD_LPDDR3_SKEW_BETWEEN_DQS_NS {0.02} + set_component_parameter_value BOARD_LPDDR3_USER_AC_ISI_NS {0.0} + set_component_parameter_value BOARD_LPDDR3_USER_AC_SLEW_RATE {2.0} + set_component_parameter_value BOARD_LPDDR3_USER_CK_SLEW_RATE {4.0} + set_component_parameter_value BOARD_LPDDR3_USER_RCLK_ISI_NS {0.0} + set_component_parameter_value BOARD_LPDDR3_USER_RCLK_SLEW_RATE {4.0} + set_component_parameter_value BOARD_LPDDR3_USER_RDATA_ISI_NS {0.0} + set_component_parameter_value BOARD_LPDDR3_USER_RDATA_SLEW_RATE {2.0} + set_component_parameter_value BOARD_LPDDR3_USER_WCLK_ISI_NS {0.0} + set_component_parameter_value BOARD_LPDDR3_USER_WCLK_SLEW_RATE {4.0} + set_component_parameter_value BOARD_LPDDR3_USER_WDATA_ISI_NS {0.0} + set_component_parameter_value BOARD_LPDDR3_USER_WDATA_SLEW_RATE {2.0} + set_component_parameter_value BOARD_LPDDR3_USE_DEFAULT_ISI_VALUES {1} + set_component_parameter_value BOARD_LPDDR3_USE_DEFAULT_SLEW_RATES {1} + set_component_parameter_value BOARD_QDR2_AC_TO_K_SKEW_NS {0.0} + set_component_parameter_value BOARD_QDR2_BRD_SKEW_WITHIN_AC_NS {0.02} + set_component_parameter_value BOARD_QDR2_BRD_SKEW_WITHIN_D_NS {0.02} + set_component_parameter_value BOARD_QDR2_BRD_SKEW_WITHIN_Q_NS {0.02} + set_component_parameter_value BOARD_QDR2_IS_SKEW_WITHIN_AC_DESKEWED {1} + set_component_parameter_value BOARD_QDR2_IS_SKEW_WITHIN_D_DESKEWED {0} + set_component_parameter_value BOARD_QDR2_IS_SKEW_WITHIN_Q_DESKEWED {0} + set_component_parameter_value BOARD_QDR2_MAX_K_DELAY_NS {0.6} + set_component_parameter_value BOARD_QDR2_PKG_BRD_SKEW_WITHIN_AC_NS {0.02} + set_component_parameter_value BOARD_QDR2_PKG_BRD_SKEW_WITHIN_D_NS {0.02} + set_component_parameter_value BOARD_QDR2_PKG_BRD_SKEW_WITHIN_Q_NS {0.02} + set_component_parameter_value BOARD_QDR2_USER_AC_ISI_NS {0.0} + set_component_parameter_value BOARD_QDR2_USER_AC_SLEW_RATE {2.0} + set_component_parameter_value BOARD_QDR2_USER_K_SLEW_RATE {4.0} + set_component_parameter_value BOARD_QDR2_USER_RCLK_ISI_NS {0.0} + set_component_parameter_value BOARD_QDR2_USER_RCLK_SLEW_RATE {4.0} + set_component_parameter_value BOARD_QDR2_USER_RDATA_ISI_NS {0.0} + set_component_parameter_value BOARD_QDR2_USER_RDATA_SLEW_RATE {2.0} + set_component_parameter_value BOARD_QDR2_USER_WCLK_ISI_NS {0.0} + set_component_parameter_value BOARD_QDR2_USER_WDATA_ISI_NS {0.0} + set_component_parameter_value BOARD_QDR2_USER_WDATA_SLEW_RATE {2.0} + set_component_parameter_value BOARD_QDR2_USE_DEFAULT_ISI_VALUES {1} + set_component_parameter_value BOARD_QDR2_USE_DEFAULT_SLEW_RATES {1} + set_component_parameter_value BOARD_QDR4_AC_TO_CK_SKEW_NS {0.0} + set_component_parameter_value BOARD_QDR4_BRD_SKEW_WITHIN_AC_NS {0.02} + set_component_parameter_value BOARD_QDR4_BRD_SKEW_WITHIN_QK_NS {0.02} + set_component_parameter_value BOARD_QDR4_DK_TO_CK_SKEW_NS {-0.02} + set_component_parameter_value BOARD_QDR4_IS_SKEW_WITHIN_AC_DESKEWED {1} + set_component_parameter_value BOARD_QDR4_IS_SKEW_WITHIN_QK_DESKEWED {1} + set_component_parameter_value BOARD_QDR4_MAX_CK_DELAY_NS {0.6} + set_component_parameter_value BOARD_QDR4_MAX_DK_DELAY_NS {0.6} + set_component_parameter_value BOARD_QDR4_PKG_BRD_SKEW_WITHIN_AC_NS {0.02} + set_component_parameter_value BOARD_QDR4_PKG_BRD_SKEW_WITHIN_QK_NS {0.02} + set_component_parameter_value BOARD_QDR4_SKEW_BETWEEN_DIMMS_NS {0.05} + set_component_parameter_value BOARD_QDR4_SKEW_BETWEEN_DK_NS {0.02} + set_component_parameter_value BOARD_QDR4_USER_AC_ISI_NS {0.0} + set_component_parameter_value BOARD_QDR4_USER_AC_SLEW_RATE {2.0} + set_component_parameter_value BOARD_QDR4_USER_CK_SLEW_RATE {4.0} + set_component_parameter_value BOARD_QDR4_USER_RCLK_ISI_NS {0.0} + set_component_parameter_value BOARD_QDR4_USER_RCLK_SLEW_RATE {5.0} + set_component_parameter_value BOARD_QDR4_USER_RDATA_ISI_NS {0.0} + set_component_parameter_value BOARD_QDR4_USER_RDATA_SLEW_RATE {2.5} + set_component_parameter_value BOARD_QDR4_USER_WCLK_ISI_NS {0.0} + set_component_parameter_value BOARD_QDR4_USER_WCLK_SLEW_RATE {4.0} + set_component_parameter_value BOARD_QDR4_USER_WDATA_ISI_NS {0.0} + set_component_parameter_value BOARD_QDR4_USER_WDATA_SLEW_RATE {2.0} + set_component_parameter_value BOARD_QDR4_USE_DEFAULT_ISI_VALUES {1} + set_component_parameter_value BOARD_QDR4_USE_DEFAULT_SLEW_RATES {1} + set_component_parameter_value BOARD_RLD3_AC_TO_CK_SKEW_NS {0.0} + set_component_parameter_value BOARD_RLD3_BRD_SKEW_WITHIN_AC_NS {0.02} + set_component_parameter_value BOARD_RLD3_BRD_SKEW_WITHIN_QK_NS {0.02} + set_component_parameter_value BOARD_RLD3_DK_TO_CK_SKEW_NS {-0.02} + set_component_parameter_value BOARD_RLD3_IS_SKEW_WITHIN_AC_DESKEWED {1} + set_component_parameter_value BOARD_RLD3_IS_SKEW_WITHIN_QK_DESKEWED {0} + set_component_parameter_value BOARD_RLD3_MAX_CK_DELAY_NS {0.6} + set_component_parameter_value BOARD_RLD3_MAX_DK_DELAY_NS {0.6} + set_component_parameter_value BOARD_RLD3_PKG_BRD_SKEW_WITHIN_AC_NS {0.02} + set_component_parameter_value BOARD_RLD3_PKG_BRD_SKEW_WITHIN_QK_NS {0.02} + set_component_parameter_value BOARD_RLD3_SKEW_BETWEEN_DIMMS_NS {0.05} + set_component_parameter_value BOARD_RLD3_SKEW_BETWEEN_DK_NS {0.02} + set_component_parameter_value BOARD_RLD3_USER_AC_ISI_NS {0.0} + set_component_parameter_value BOARD_RLD3_USER_AC_SLEW_RATE {2.0} + set_component_parameter_value BOARD_RLD3_USER_CK_SLEW_RATE {4.0} + set_component_parameter_value BOARD_RLD3_USER_RCLK_ISI_NS {0.0} + set_component_parameter_value BOARD_RLD3_USER_RCLK_SLEW_RATE {7.0} + set_component_parameter_value BOARD_RLD3_USER_RDATA_ISI_NS {0.0} + set_component_parameter_value BOARD_RLD3_USER_RDATA_SLEW_RATE {3.5} + set_component_parameter_value BOARD_RLD3_USER_WCLK_ISI_NS {0.0} + set_component_parameter_value BOARD_RLD3_USER_WCLK_SLEW_RATE {4.0} + set_component_parameter_value BOARD_RLD3_USER_WDATA_ISI_NS {0.0} + set_component_parameter_value BOARD_RLD3_USER_WDATA_SLEW_RATE {2.0} + set_component_parameter_value BOARD_RLD3_USE_DEFAULT_ISI_VALUES {1} + set_component_parameter_value BOARD_RLD3_USE_DEFAULT_SLEW_RATES {1} + set_component_parameter_value CTRL_DDR3_ADDR_ORDER_ENUM {DDR3_CTRL_ADDR_ORDER_CS_R_B_C} + set_component_parameter_value CTRL_DDR3_AUTO_POWER_DOWN_CYCS {32} + set_component_parameter_value CTRL_DDR3_AUTO_POWER_DOWN_EN {0} + set_component_parameter_value CTRL_DDR3_AUTO_PRECHARGE_EN {0} + set_component_parameter_value CTRL_DDR3_AVL_PROTOCOL_ENUM {CTRL_AVL_PROTOCOL_MM} + set_component_parameter_value CTRL_DDR3_ECC_AUTO_CORRECTION_EN {0} + set_component_parameter_value CTRL_DDR3_ECC_EN {0} + set_component_parameter_value CTRL_DDR3_ECC_READDATAERROR_EN {1} + set_component_parameter_value CTRL_DDR3_ECC_STATUS_EN {0} + set_component_parameter_value CTRL_DDR3_MMR_EN {0} + set_component_parameter_value CTRL_DDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS {0} + set_component_parameter_value CTRL_DDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS {0} + set_component_parameter_value CTRL_DDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS {0} + set_component_parameter_value CTRL_DDR3_REORDER_EN {1} + set_component_parameter_value CTRL_DDR3_SELF_REFRESH_EN {0} + set_component_parameter_value CTRL_DDR3_STARVE_LIMIT {10} + set_component_parameter_value CTRL_DDR3_USER_PRIORITY_EN {0} + set_component_parameter_value CTRL_DDR3_USER_REFRESH_EN {0} + set_component_parameter_value CTRL_DDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS {0} + set_component_parameter_value CTRL_DDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS {0} + set_component_parameter_value CTRL_DDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS {0} + set_component_parameter_value CTRL_DDR4_ADDR_ORDER_ENUM {DDR4_CTRL_ADDR_ORDER_CS_R_B_C_BG} + set_component_parameter_value CTRL_DDR4_AUTO_POWER_DOWN_CYCS {32} + set_component_parameter_value CTRL_DDR4_AUTO_POWER_DOWN_EN {0} + set_component_parameter_value CTRL_DDR4_AUTO_PRECHARGE_EN {0} + set_component_parameter_value CTRL_DDR4_AVL_PROTOCOL_ENUM {CTRL_AVL_PROTOCOL_MM} + set_component_parameter_value CTRL_DDR4_ECC_AUTO_CORRECTION_EN {0} + set_component_parameter_value CTRL_DDR4_ECC_EN {1} + set_component_parameter_value CTRL_DDR4_ECC_READDATAERROR_EN {0} + set_component_parameter_value CTRL_DDR4_ECC_STATUS_EN {0} + set_component_parameter_value CTRL_DDR4_MAJOR_MODE_EN {0} + set_component_parameter_value CTRL_DDR4_MMR_EN {0} + set_component_parameter_value CTRL_DDR4_POST_REFRESH_EN {1} + set_component_parameter_value CTRL_DDR4_POST_REFRESH_LOWER_LIMIT {0} + set_component_parameter_value CTRL_DDR4_POST_REFRESH_UPPER_LIMIT {2} + set_component_parameter_value CTRL_DDR4_PRE_REFRESH_EN {0} + set_component_parameter_value CTRL_DDR4_PRE_REFRESH_UPPER_LIMIT {1} + set_component_parameter_value CTRL_DDR4_RD_TO_RD_DIFF_CHIP_DELTA_CYCS {0} + set_component_parameter_value CTRL_DDR4_RD_TO_WR_DIFF_CHIP_DELTA_CYCS {0} + set_component_parameter_value CTRL_DDR4_RD_TO_WR_SAME_CHIP_DELTA_CYCS {0} + set_component_parameter_value CTRL_DDR4_REORDER_EN {1} + set_component_parameter_value CTRL_DDR4_SELF_REFRESH_EN {0} + set_component_parameter_value CTRL_DDR4_STARVE_LIMIT {10} + set_component_parameter_value CTRL_DDR4_USER_PRIORITY_EN {0} + set_component_parameter_value CTRL_DDR4_USER_REFRESH_EN {0} + set_component_parameter_value CTRL_DDR4_WR_TO_RD_DIFF_CHIP_DELTA_CYCS {0} + set_component_parameter_value CTRL_DDR4_WR_TO_RD_SAME_CHIP_DELTA_CYCS {0} + set_component_parameter_value CTRL_DDR4_WR_TO_WR_DIFF_CHIP_DELTA_CYCS {0} + set_component_parameter_value CTRL_DDRT_ADDR_INTERLEAVING {COARSE} + set_component_parameter_value CTRL_DDRT_ADDR_ORDER_ENUM {DDRT_CTRL_ADDR_ORDER_CS_R_B_C_BG} + set_component_parameter_value CTRL_DDRT_AUTO_POWER_DOWN_CYCS {32} + set_component_parameter_value CTRL_DDRT_AUTO_POWER_DOWN_EN {0} + set_component_parameter_value CTRL_DDRT_AUTO_PRECHARGE_EN {0} + set_component_parameter_value CTRL_DDRT_AVL_PROTOCOL_ENUM {CTRL_AVL_PROTOCOL_MM} + set_component_parameter_value CTRL_DDRT_DIMM_DENSITY {128} + set_component_parameter_value CTRL_DDRT_DIMM_VIRAL_FLOW_EN {0} + set_component_parameter_value CTRL_DDRT_ECC_AUTO_CORRECTION_EN {0} + set_component_parameter_value CTRL_DDRT_ECC_EN {0} + set_component_parameter_value CTRL_DDRT_ECC_READDATAERROR_EN {1} + set_component_parameter_value CTRL_DDRT_ECC_STATUS_EN {1} + set_component_parameter_value CTRL_DDRT_ERR_INJECT_EN {0} + set_component_parameter_value CTRL_DDRT_ERR_REPLAY_EN {0} + set_component_parameter_value CTRL_DDRT_EXT_ERR_INJECT_EN {0} + set_component_parameter_value CTRL_DDRT_GNT_TO_GNT_DIFF_CHIP_DELTA_CYCS {0} + set_component_parameter_value CTRL_DDRT_GNT_TO_WR_DIFF_CHIP_DELTA_CYCS {1} + set_component_parameter_value CTRL_DDRT_GNT_TO_WR_SAME_CHIP_DELTA_CYCS {1} + set_component_parameter_value CTRL_DDRT_HOST_VIRAL_FLOW_EN {0} + set_component_parameter_value CTRL_DDRT_MMR_EN {0} + set_component_parameter_value CTRL_DDRT_NUM_OF_AXIS_ID {1} + set_component_parameter_value CTRL_DDRT_PARITY_CMD_EN {0} + set_component_parameter_value CTRL_DDRT_PMM_ADR_FLOW_EN {0} + set_component_parameter_value CTRL_DDRT_PMM_WPQ_FLUSH_EN {0} + set_component_parameter_value CTRL_DDRT_POISON_DETECTION_EN {0} + set_component_parameter_value CTRL_DDRT_PORT_AFI_C_WIDTH {2} + set_component_parameter_value CTRL_DDRT_RD_TO_RD_DIFF_CHIP_DELTA_CYCS {0} + set_component_parameter_value CTRL_DDRT_RD_TO_WR_DIFF_CHIP_DELTA_CYCS {0} + set_component_parameter_value CTRL_DDRT_RD_TO_WR_SAME_CHIP_DELTA_CYCS {0} + set_component_parameter_value CTRL_DDRT_REORDER_EN {1} + set_component_parameter_value CTRL_DDRT_SELF_REFRESH_EN {0} + set_component_parameter_value CTRL_DDRT_STARVE_LIMIT {10} + set_component_parameter_value CTRL_DDRT_UPI_EN {0} + set_component_parameter_value CTRL_DDRT_UPI_ID_WIDTH {8} + set_component_parameter_value CTRL_DDRT_USER_PRIORITY_EN {0} + set_component_parameter_value CTRL_DDRT_USER_REFRESH_EN {0} + set_component_parameter_value CTRL_DDRT_WR_ACK_POLICY {POSTED} + set_component_parameter_value CTRL_DDRT_WR_TO_GNT_DIFF_CHIP_DELTA_CYCS {0} + set_component_parameter_value CTRL_DDRT_WR_TO_GNT_SAME_CHIP_DELTA_CYCS {0} + set_component_parameter_value CTRL_DDRT_WR_TO_RD_DIFF_CHIP_DELTA_CYCS {0} + set_component_parameter_value CTRL_DDRT_WR_TO_RD_SAME_CHIP_DELTA_CYCS {0} + set_component_parameter_value CTRL_DDRT_WR_TO_WR_DIFF_CHIP_DELTA_CYCS {0} + set_component_parameter_value CTRL_DDRT_ZQ_INTERVAL_MS {3} + set_component_parameter_value CTRL_LPDDR3_ADDR_ORDER_ENUM {LPDDR3_CTRL_ADDR_ORDER_CS_R_B_C} + set_component_parameter_value CTRL_LPDDR3_AUTO_POWER_DOWN_CYCS {32} + set_component_parameter_value CTRL_LPDDR3_AUTO_POWER_DOWN_EN {0} + set_component_parameter_value CTRL_LPDDR3_AUTO_PRECHARGE_EN {0} + set_component_parameter_value CTRL_LPDDR3_AVL_PROTOCOL_ENUM {CTRL_AVL_PROTOCOL_MM} + set_component_parameter_value CTRL_LPDDR3_MMR_EN {0} + set_component_parameter_value CTRL_LPDDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS {0} + set_component_parameter_value CTRL_LPDDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS {0} + set_component_parameter_value CTRL_LPDDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS {0} + set_component_parameter_value CTRL_LPDDR3_REORDER_EN {1} + set_component_parameter_value CTRL_LPDDR3_SELF_REFRESH_EN {0} + set_component_parameter_value CTRL_LPDDR3_STARVE_LIMIT {10} + set_component_parameter_value CTRL_LPDDR3_USER_PRIORITY_EN {0} + set_component_parameter_value CTRL_LPDDR3_USER_REFRESH_EN {0} + set_component_parameter_value CTRL_LPDDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS {0} + set_component_parameter_value CTRL_LPDDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS {0} + set_component_parameter_value CTRL_LPDDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS {0} + set_component_parameter_value CTRL_QDR2_AVL_ENABLE_POWER_OF_TWO_BUS {0} + set_component_parameter_value CTRL_QDR2_AVL_MAX_BURST_COUNT {4} + set_component_parameter_value CTRL_QDR2_AVL_PROTOCOL_ENUM {CTRL_AVL_PROTOCOL_MM} + set_component_parameter_value CTRL_QDR4_ADD_RAW_TURNAROUND_DELAY_CYC {0} + set_component_parameter_value CTRL_QDR4_ADD_WAR_TURNAROUND_DELAY_CYC {0} + set_component_parameter_value CTRL_QDR4_AVL_ENABLE_POWER_OF_TWO_BUS {0} + set_component_parameter_value CTRL_QDR4_AVL_MAX_BURST_COUNT {4} + set_component_parameter_value CTRL_QDR4_AVL_PROTOCOL_ENUM {CTRL_AVL_PROTOCOL_MM} + set_component_parameter_value CTRL_QDR4_DEF_RAW_TURNAROUND_DELAY_CYC {4} + set_component_parameter_value CTRL_RLD2_AVL_PROTOCOL_ENUM {CTRL_AVL_PROTOCOL_MM} + set_component_parameter_value CTRL_RLD3_ADDR_ORDER_ENUM {RLD3_CTRL_ADDR_ORDER_CS_R_B_C} + set_component_parameter_value CTRL_RLD3_AVL_PROTOCOL_ENUM {CTRL_AVL_PROTOCOL_MM} + set_component_parameter_value DIAG_ADD_READY_PIPELINE {1} + set_component_parameter_value DIAG_BOARD_DELAY_CONFIG_STR {} + set_component_parameter_value DIAG_DB_RESET_AUTO_RELEASE {avl_release} + set_component_parameter_value DIAG_DDR3_ABSTRACT_PHY {0} + set_component_parameter_value DIAG_DDR3_AC_PARITY_ERR {0} + set_component_parameter_value DIAG_DDR3_CAL_ADDR0 {0} + set_component_parameter_value DIAG_DDR3_CAL_ADDR1 {8} + set_component_parameter_value DIAG_DDR3_CAL_ENABLE_MICRON_AP {0} + set_component_parameter_value DIAG_DDR3_CAL_ENABLE_NON_DES {0} + set_component_parameter_value DIAG_DDR3_CAL_FULL_CAL_ON_RESET {1} + set_component_parameter_value DIAG_DDR3_CA_DESKEW_EN {1} + set_component_parameter_value DIAG_DDR3_CA_LEVEL_EN {1} + set_component_parameter_value DIAG_DDR3_DISABLE_AFI_P2C_REGISTERS {0} + set_component_parameter_value DIAG_DDR3_EFFICIENCY_MONITOR {EFFMON_MODE_DISABLED} + set_component_parameter_value DIAG_DDR3_ENABLE_DEFAULT_MODE {0} + set_component_parameter_value DIAG_DDR3_ENABLE_USER_MODE {1} + set_component_parameter_value DIAG_DDR3_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN {1} + set_component_parameter_value DIAG_DDR3_EXPORT_SEQ_AVALON_MASTER {0} + set_component_parameter_value DIAG_DDR3_EXPORT_SEQ_AVALON_SLAVE {CAL_DEBUG_EXPORT_MODE_DISABLED} + set_component_parameter_value DIAG_DDR3_EXPORT_TG_CFG_AVALON_SLAVE {TG_CFG_AMM_EXPORT_MODE_EXPORT} + set_component_parameter_value DIAG_DDR3_EX_DESIGN_ISSP_EN {1} + set_component_parameter_value DIAG_DDR3_EX_DESIGN_NUM_OF_SLAVES {1} + set_component_parameter_value DIAG_DDR3_EX_DESIGN_SEPARATE_RZQS {1} + set_component_parameter_value DIAG_DDR3_INTERFACE_ID {0} + set_component_parameter_value DIAG_DDR3_SEPARATE_READ_WRITE_ITFS {0} + set_component_parameter_value DIAG_DDR3_SIM_CAL_MODE_ENUM {SIM_CAL_MODE_SKIP} + set_component_parameter_value DIAG_DDR3_SIM_VERBOSE {1} + set_component_parameter_value DIAG_DDR3_TG2_TEST_DURATION {SHORT} + set_component_parameter_value DIAG_DDR3_USER_SIM_MEMORY_PRELOAD {0} + set_component_parameter_value DIAG_DDR3_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE {EMIF_PRI_PRELOAD.txt} + set_component_parameter_value DIAG_DDR3_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE {EMIF_SEC_PRELOAD.txt} + set_component_parameter_value DIAG_DDR3_USER_USE_SIM_MEMORY_VALIDATION_TG {1} + set_component_parameter_value DIAG_DDR3_USE_NEW_EFFMON_S10 {0} + set_component_parameter_value DIAG_DDR3_USE_TG_AVL_2 {0} + set_component_parameter_value DIAG_DDR3_USE_TG_HBM {0} + set_component_parameter_value DIAG_DDR4_ABSTRACT_PHY {0} + set_component_parameter_value DIAG_DDR4_AC_PARITY_ERR {0} + set_component_parameter_value DIAG_DDR4_CAL_ADDR0 {0} + set_component_parameter_value DIAG_DDR4_CAL_ADDR1 {8} + set_component_parameter_value DIAG_DDR4_CAL_ENABLE_NON_DES {0} + set_component_parameter_value DIAG_DDR4_CAL_FULL_CAL_ON_RESET {1} + set_component_parameter_value DIAG_DDR4_DISABLE_AFI_P2C_REGISTERS {0} + set_component_parameter_value DIAG_DDR4_EFFICIENCY_MONITOR {EFFMON_MODE_DISABLED} + set_component_parameter_value DIAG_DDR4_ENABLE_DEFAULT_MODE {0} + set_component_parameter_value DIAG_DDR4_ENABLE_USER_MODE {1} + set_component_parameter_value DIAG_DDR4_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN {1} + set_component_parameter_value DIAG_DDR4_EXPORT_SEQ_AVALON_MASTER {0} + set_component_parameter_value DIAG_DDR4_EXPORT_SEQ_AVALON_SLAVE {CAL_DEBUG_EXPORT_MODE_JTAG} + set_component_parameter_value DIAG_DDR4_EXPORT_TG_CFG_AVALON_SLAVE {TG_CFG_AMM_EXPORT_MODE_EXPORT} + set_component_parameter_value DIAG_DDR4_EX_DESIGN_ISSP_EN {1} + set_component_parameter_value DIAG_DDR4_EX_DESIGN_NUM_OF_SLAVES {1} + set_component_parameter_value DIAG_DDR4_EX_DESIGN_SEPARATE_RZQS {1} + set_component_parameter_value DIAG_DDR4_INTERFACE_ID {0} + set_component_parameter_value DIAG_DDR4_SEPARATE_READ_WRITE_ITFS {0} + set_component_parameter_value DIAG_DDR4_SIM_CAL_MODE_ENUM {SIM_CAL_MODE_SKIP} + set_component_parameter_value DIAG_DDR4_SIM_VERBOSE {1} + set_component_parameter_value DIAG_DDR4_SKIP_AC_PARITY_CHECK {0} + set_component_parameter_value DIAG_DDR4_SKIP_CA_DESKEW {0} + set_component_parameter_value DIAG_DDR4_SKIP_CA_LEVEL {0} + set_component_parameter_value DIAG_DDR4_SKIP_VREF_CAL {0} + set_component_parameter_value DIAG_DDR4_TG2_TEST_DURATION {SHORT} + set_component_parameter_value DIAG_DDR4_USER_SIM_MEMORY_PRELOAD {0} + set_component_parameter_value DIAG_DDR4_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE {EMIF_PRI_PRELOAD.txt} + set_component_parameter_value DIAG_DDR4_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE {EMIF_SEC_PRELOAD.txt} + set_component_parameter_value DIAG_DDR4_USER_USE_SIM_MEMORY_VALIDATION_TG {1} + set_component_parameter_value DIAG_DDR4_USE_NEW_EFFMON_S10 {0} + set_component_parameter_value DIAG_DDR4_USE_TG_AVL_2 {0} + set_component_parameter_value DIAG_DDR4_USE_TG_HBM {0} + set_component_parameter_value DIAG_DDRT_ABSTRACT_PHY {0} + set_component_parameter_value DIAG_DDRT_AC_PARITY_ERR {0} + set_component_parameter_value DIAG_DDRT_CAL_ADDR0 {0} + set_component_parameter_value DIAG_DDRT_CAL_ADDR1 {8} + set_component_parameter_value DIAG_DDRT_CAL_ENABLE_NON_DES {0} + set_component_parameter_value DIAG_DDRT_CAL_FULL_CAL_ON_RESET {1} + set_component_parameter_value DIAG_DDRT_DISABLE_AFI_P2C_REGISTERS {0} + set_component_parameter_value DIAG_DDRT_EFFICIENCY_MONITOR {EFFMON_MODE_DISABLED} + set_component_parameter_value DIAG_DDRT_EFF_TEST {0} + set_component_parameter_value DIAG_DDRT_ENABLE_DEFAULT_MODE {0} + set_component_parameter_value DIAG_DDRT_ENABLE_DRIVER_MARGINING {0} + set_component_parameter_value DIAG_DDRT_ENABLE_ENHANCED_TESTING {0} + set_component_parameter_value DIAG_DDRT_ENABLE_USER_MODE {1} + set_component_parameter_value DIAG_DDRT_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN {1} + set_component_parameter_value DIAG_DDRT_EXPORT_SEQ_AVALON_MASTER {0} + set_component_parameter_value DIAG_DDRT_EXPORT_SEQ_AVALON_SLAVE {CAL_DEBUG_EXPORT_MODE_DISABLED} + set_component_parameter_value DIAG_DDRT_EXPORT_TG_CFG_AVALON_SLAVE {TG_CFG_AMM_EXPORT_MODE_JTAG} + set_component_parameter_value DIAG_DDRT_EX_DESIGN_ISSP_EN {1} + set_component_parameter_value DIAG_DDRT_EX_DESIGN_NUM_OF_SLAVES {1} + set_component_parameter_value DIAG_DDRT_EX_DESIGN_SEPARATE_RZQS {1} + set_component_parameter_value DIAG_DDRT_INTERFACE_ID {0} + set_component_parameter_value DIAG_DDRT_SEPARATE_READ_WRITE_ITFS {0} + set_component_parameter_value DIAG_DDRT_SIM_CAL_MODE_ENUM {SIM_CAL_MODE_SKIP} + set_component_parameter_value DIAG_DDRT_SIM_VERBOSE {1} + set_component_parameter_value DIAG_DDRT_SKIP_CA_DESKEW {0} + set_component_parameter_value DIAG_DDRT_SKIP_CA_LEVEL {0} + set_component_parameter_value DIAG_DDRT_SKIP_VREF_CAL {0} + set_component_parameter_value DIAG_DDRT_TG2_TEST_DURATION {SHORT} + set_component_parameter_value DIAG_DDRT_USER_SIM_MEMORY_PRELOAD {0} + set_component_parameter_value DIAG_DDRT_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE {EMIF_PRI_PRELOAD.txt} + set_component_parameter_value DIAG_DDRT_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE {EMIF_SEC_PRELOAD.txt} + set_component_parameter_value DIAG_DDRT_USER_USE_SIM_MEMORY_VALIDATION_TG {1} + set_component_parameter_value DIAG_DDRT_USE_NEW_EFFMON_S10 {0} + set_component_parameter_value DIAG_DDRT_USE_TG_AVL_2 {1} + set_component_parameter_value DIAG_DDRT_USE_TG_HBM {0} + set_component_parameter_value DIAG_ECLIPSE_DEBUG {0} + set_component_parameter_value DIAG_ENABLE_HPS_EMIF_DEBUG {0} + set_component_parameter_value DIAG_ENABLE_JTAG_UART {0} + set_component_parameter_value DIAG_ENABLE_JTAG_UART_HEX {0} + set_component_parameter_value DIAG_EXPORT_PLL_LOCKED {1} + set_component_parameter_value DIAG_EXPORT_PLL_REF_CLK_OUT {0} + set_component_parameter_value DIAG_EXPORT_VJI {0} + set_component_parameter_value DIAG_EXPOSE_DFT_SIGNALS {0} + set_component_parameter_value DIAG_EXPOSE_EARLY_READY {0} + set_component_parameter_value DIAG_EXPOSE_RD_TYPE {0} + set_component_parameter_value DIAG_EXTRA_CONFIGS {} + set_component_parameter_value DIAG_EXT_DOCS {0} + set_component_parameter_value DIAG_EX_DESIGN_ADD_TEST_EMIFS {} + set_component_parameter_value DIAG_EX_DESIGN_SEPARATE_RESETS {0} + set_component_parameter_value DIAG_FAST_SIM_OVERRIDE {FAST_SIM_OVERRIDE_DEFAULT} + set_component_parameter_value DIAG_HMC_HRC {auto} + set_component_parameter_value DIAG_LPDDR3_ABSTRACT_PHY {0} + set_component_parameter_value DIAG_LPDDR3_AC_PARITY_ERR {0} + set_component_parameter_value DIAG_LPDDR3_DISABLE_AFI_P2C_REGISTERS {0} + set_component_parameter_value DIAG_LPDDR3_EFFICIENCY_MONITOR {EFFMON_MODE_DISABLED} + set_component_parameter_value DIAG_LPDDR3_ENABLE_DEFAULT_MODE {0} + set_component_parameter_value DIAG_LPDDR3_ENABLE_USER_MODE {1} + set_component_parameter_value DIAG_LPDDR3_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN {1} + set_component_parameter_value DIAG_LPDDR3_EXPORT_SEQ_AVALON_MASTER {0} + set_component_parameter_value DIAG_LPDDR3_EXPORT_SEQ_AVALON_SLAVE {CAL_DEBUG_EXPORT_MODE_DISABLED} + set_component_parameter_value DIAG_LPDDR3_EXPORT_TG_CFG_AVALON_SLAVE {TG_CFG_AMM_EXPORT_MODE_EXPORT} + set_component_parameter_value DIAG_LPDDR3_EX_DESIGN_ISSP_EN {1} + set_component_parameter_value DIAG_LPDDR3_EX_DESIGN_NUM_OF_SLAVES {1} + set_component_parameter_value DIAG_LPDDR3_EX_DESIGN_SEPARATE_RZQS {1} + set_component_parameter_value DIAG_LPDDR3_INTERFACE_ID {0} + set_component_parameter_value DIAG_LPDDR3_SEPARATE_READ_WRITE_ITFS {0} + set_component_parameter_value DIAG_LPDDR3_SIM_CAL_MODE_ENUM {SIM_CAL_MODE_SKIP} + set_component_parameter_value DIAG_LPDDR3_SIM_VERBOSE {1} + set_component_parameter_value DIAG_LPDDR3_SKIP_CA_DESKEW {0} + set_component_parameter_value DIAG_LPDDR3_SKIP_CA_LEVEL {0} + set_component_parameter_value DIAG_LPDDR3_TG2_TEST_DURATION {SHORT} + set_component_parameter_value DIAG_LPDDR3_USER_SIM_MEMORY_PRELOAD {0} + set_component_parameter_value DIAG_LPDDR3_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE {EMIF_PRI_PRELOAD.txt} + set_component_parameter_value DIAG_LPDDR3_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE {EMIF_SEC_PRELOAD.txt} + set_component_parameter_value DIAG_LPDDR3_USER_USE_SIM_MEMORY_VALIDATION_TG {1} + set_component_parameter_value DIAG_LPDDR3_USE_NEW_EFFMON_S10 {0} + set_component_parameter_value DIAG_LPDDR3_USE_TG_AVL_2 {0} + set_component_parameter_value DIAG_LPDDR3_USE_TG_HBM {0} + set_component_parameter_value DIAG_QDR2_ABSTRACT_PHY {0} + set_component_parameter_value DIAG_QDR2_AC_PARITY_ERR {0} + set_component_parameter_value DIAG_QDR2_DISABLE_AFI_P2C_REGISTERS {0} + set_component_parameter_value DIAG_QDR2_EFFICIENCY_MONITOR {EFFMON_MODE_DISABLED} + set_component_parameter_value DIAG_QDR2_ENABLE_DEFAULT_MODE {0} + set_component_parameter_value DIAG_QDR2_ENABLE_USER_MODE {1} + set_component_parameter_value DIAG_QDR2_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN {1} + set_component_parameter_value DIAG_QDR2_EXPORT_SEQ_AVALON_MASTER {0} + set_component_parameter_value DIAG_QDR2_EXPORT_SEQ_AVALON_SLAVE {CAL_DEBUG_EXPORT_MODE_DISABLED} + set_component_parameter_value DIAG_QDR2_EXPORT_TG_CFG_AVALON_SLAVE {TG_CFG_AMM_EXPORT_MODE_EXPORT} + set_component_parameter_value DIAG_QDR2_EX_DESIGN_ISSP_EN {1} + set_component_parameter_value DIAG_QDR2_EX_DESIGN_NUM_OF_SLAVES {1} + set_component_parameter_value DIAG_QDR2_EX_DESIGN_SEPARATE_RZQS {1} + set_component_parameter_value DIAG_QDR2_INTERFACE_ID {0} + set_component_parameter_value DIAG_QDR2_SEPARATE_READ_WRITE_ITFS {0} + set_component_parameter_value DIAG_QDR2_SIM_CAL_MODE_ENUM {SIM_CAL_MODE_SKIP} + set_component_parameter_value DIAG_QDR2_SIM_VERBOSE {1} + set_component_parameter_value DIAG_QDR2_TG2_TEST_DURATION {SHORT} + set_component_parameter_value DIAG_QDR2_USER_SIM_MEMORY_PRELOAD {0} + set_component_parameter_value DIAG_QDR2_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE {EMIF_PRI_PRELOAD.txt} + set_component_parameter_value DIAG_QDR2_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE {EMIF_SEC_PRELOAD.txt} + set_component_parameter_value DIAG_QDR2_USER_USE_SIM_MEMORY_VALIDATION_TG {1} + set_component_parameter_value DIAG_QDR2_USE_NEW_EFFMON_S10 {0} + set_component_parameter_value DIAG_QDR2_USE_TG_AVL_2 {0} + set_component_parameter_value DIAG_QDR2_USE_TG_HBM {0} + set_component_parameter_value DIAG_QDR4_ABSTRACT_PHY {0} + set_component_parameter_value DIAG_QDR4_AC_PARITY_ERR {0} + set_component_parameter_value DIAG_QDR4_DISABLE_AFI_P2C_REGISTERS {0} + set_component_parameter_value DIAG_QDR4_EFFICIENCY_MONITOR {EFFMON_MODE_DISABLED} + set_component_parameter_value DIAG_QDR4_ENABLE_DEFAULT_MODE {0} + set_component_parameter_value DIAG_QDR4_ENABLE_USER_MODE {1} + set_component_parameter_value DIAG_QDR4_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN {1} + set_component_parameter_value DIAG_QDR4_EXPORT_SEQ_AVALON_MASTER {0} + set_component_parameter_value DIAG_QDR4_EXPORT_SEQ_AVALON_SLAVE {CAL_DEBUG_EXPORT_MODE_DISABLED} + set_component_parameter_value DIAG_QDR4_EXPORT_TG_CFG_AVALON_SLAVE {TG_CFG_AMM_EXPORT_MODE_EXPORT} + set_component_parameter_value DIAG_QDR4_EX_DESIGN_ISSP_EN {1} + set_component_parameter_value DIAG_QDR4_EX_DESIGN_NUM_OF_SLAVES {1} + set_component_parameter_value DIAG_QDR4_EX_DESIGN_SEPARATE_RZQS {1} + set_component_parameter_value DIAG_QDR4_INTERFACE_ID {0} + set_component_parameter_value DIAG_QDR4_SEPARATE_READ_WRITE_ITFS {0} + set_component_parameter_value DIAG_QDR4_SIM_CAL_MODE_ENUM {SIM_CAL_MODE_SKIP} + set_component_parameter_value DIAG_QDR4_SIM_VERBOSE {1} + set_component_parameter_value DIAG_QDR4_SKIP_VREF_CAL {0} + set_component_parameter_value DIAG_QDR4_TG2_TEST_DURATION {SHORT} + set_component_parameter_value DIAG_QDR4_USER_SIM_MEMORY_PRELOAD {0} + set_component_parameter_value DIAG_QDR4_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE {EMIF_PRI_PRELOAD.txt} + set_component_parameter_value DIAG_QDR4_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE {EMIF_SEC_PRELOAD.txt} + set_component_parameter_value DIAG_QDR4_USER_USE_SIM_MEMORY_VALIDATION_TG {1} + set_component_parameter_value DIAG_QDR4_USE_NEW_EFFMON_S10 {0} + set_component_parameter_value DIAG_QDR4_USE_TG_AVL_2 {0} + set_component_parameter_value DIAG_QDR4_USE_TG_HBM {0} + set_component_parameter_value DIAG_RLD2_ABSTRACT_PHY {0} + set_component_parameter_value DIAG_RLD2_AC_PARITY_ERR {0} + set_component_parameter_value DIAG_RLD2_DISABLE_AFI_P2C_REGISTERS {0} + set_component_parameter_value DIAG_RLD2_EFFICIENCY_MONITOR {EFFMON_MODE_DISABLED} + set_component_parameter_value DIAG_RLD2_ENABLE_DEFAULT_MODE {0} + set_component_parameter_value DIAG_RLD2_ENABLE_USER_MODE {1} + set_component_parameter_value DIAG_RLD2_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN {1} + set_component_parameter_value DIAG_RLD2_EXPORT_SEQ_AVALON_MASTER {0} + set_component_parameter_value DIAG_RLD2_EXPORT_SEQ_AVALON_SLAVE {CAL_DEBUG_EXPORT_MODE_DISABLED} + set_component_parameter_value DIAG_RLD2_EXPORT_TG_CFG_AVALON_SLAVE {TG_CFG_AMM_EXPORT_MODE_EXPORT} + set_component_parameter_value DIAG_RLD2_EX_DESIGN_ISSP_EN {1} + set_component_parameter_value DIAG_RLD2_EX_DESIGN_NUM_OF_SLAVES {1} + set_component_parameter_value DIAG_RLD2_EX_DESIGN_SEPARATE_RZQS {1} + set_component_parameter_value DIAG_RLD2_INTERFACE_ID {0} + set_component_parameter_value DIAG_RLD2_SEPARATE_READ_WRITE_ITFS {0} + set_component_parameter_value DIAG_RLD2_SIM_CAL_MODE_ENUM {SIM_CAL_MODE_SKIP} + set_component_parameter_value DIAG_RLD2_SIM_VERBOSE {1} + set_component_parameter_value DIAG_RLD2_TG2_TEST_DURATION {SHORT} + set_component_parameter_value DIAG_RLD2_USER_SIM_MEMORY_PRELOAD {0} + set_component_parameter_value DIAG_RLD2_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE {EMIF_PRI_PRELOAD.txt} + set_component_parameter_value DIAG_RLD2_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE {EMIF_SEC_PRELOAD.txt} + set_component_parameter_value DIAG_RLD2_USER_USE_SIM_MEMORY_VALIDATION_TG {1} + set_component_parameter_value DIAG_RLD2_USE_NEW_EFFMON_S10 {0} + set_component_parameter_value DIAG_RLD2_USE_TG_AVL_2 {0} + set_component_parameter_value DIAG_RLD2_USE_TG_HBM {0} + set_component_parameter_value DIAG_RLD3_ABSTRACT_PHY {0} + set_component_parameter_value DIAG_RLD3_AC_PARITY_ERR {0} + set_component_parameter_value DIAG_RLD3_CA_DESKEW_EN {1} + set_component_parameter_value DIAG_RLD3_CA_LEVEL_EN {1} + set_component_parameter_value DIAG_RLD3_DISABLE_AFI_P2C_REGISTERS {0} + set_component_parameter_value DIAG_RLD3_EFFICIENCY_MONITOR {EFFMON_MODE_DISABLED} + set_component_parameter_value DIAG_RLD3_ENABLE_DEFAULT_MODE {0} + set_component_parameter_value DIAG_RLD3_ENABLE_USER_MODE {1} + set_component_parameter_value DIAG_RLD3_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN {1} + set_component_parameter_value DIAG_RLD3_EXPORT_SEQ_AVALON_MASTER {0} + set_component_parameter_value DIAG_RLD3_EXPORT_SEQ_AVALON_SLAVE {CAL_DEBUG_EXPORT_MODE_DISABLED} + set_component_parameter_value DIAG_RLD3_EXPORT_TG_CFG_AVALON_SLAVE {TG_CFG_AMM_EXPORT_MODE_EXPORT} + set_component_parameter_value DIAG_RLD3_EX_DESIGN_ISSP_EN {1} + set_component_parameter_value DIAG_RLD3_EX_DESIGN_NUM_OF_SLAVES {1} + set_component_parameter_value DIAG_RLD3_EX_DESIGN_SEPARATE_RZQS {1} + set_component_parameter_value DIAG_RLD3_INTERFACE_ID {0} + set_component_parameter_value DIAG_RLD3_SEPARATE_READ_WRITE_ITFS {0} + set_component_parameter_value DIAG_RLD3_SIM_CAL_MODE_ENUM {SIM_CAL_MODE_SKIP} + set_component_parameter_value DIAG_RLD3_SIM_VERBOSE {1} + set_component_parameter_value DIAG_RLD3_TG2_TEST_DURATION {SHORT} + set_component_parameter_value DIAG_RLD3_USER_SIM_MEMORY_PRELOAD {0} + set_component_parameter_value DIAG_RLD3_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE {EMIF_PRI_PRELOAD.txt} + set_component_parameter_value DIAG_RLD3_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE {EMIF_SEC_PRELOAD.txt} + set_component_parameter_value DIAG_RLD3_USER_USE_SIM_MEMORY_VALIDATION_TG {1} + set_component_parameter_value DIAG_RLD3_USE_NEW_EFFMON_S10 {0} + set_component_parameter_value DIAG_RLD3_USE_TG_AVL_2 {0} + set_component_parameter_value DIAG_RLD3_USE_TG_HBM {0} + set_component_parameter_value DIAG_RS232_UART_BAUDRATE {57600} + set_component_parameter_value DIAG_SEQ_RESET_AUTO_RELEASE {avl} + set_component_parameter_value DIAG_SIM_REGTEST_MODE {0} + set_component_parameter_value DIAG_SOFT_NIOS_CLOCK_FREQUENCY {100} + set_component_parameter_value DIAG_SOFT_NIOS_MODE {SOFT_NIOS_MODE_DISABLED} + set_component_parameter_value DIAG_SYNTH_FOR_SIM {0} + set_component_parameter_value DIAG_TG_AVL_2_NUM_CFG_INTERFACES {0} + set_component_parameter_value DIAG_TIMING_REGTEST_MODE {0} + set_component_parameter_value DIAG_USE_BOARD_DELAY_MODEL {0} + set_component_parameter_value DIAG_USE_RS232_UART {0} + set_component_parameter_value DIAG_VERBOSE_IOAUX {0} + set_component_parameter_value EMIF_0_CONN_TO_CALIP {CALIP_0} + set_component_parameter_value EMIF_0_REF_CLK_SHARING {EXPORTED} + set_component_parameter_value EMIF_0_STORED_PARAM {} + set_component_parameter_value EMIF_10_CONN_TO_CALIP {CALIP_0} + set_component_parameter_value EMIF_10_REF_CLK_SHARING {EXPORTED} + set_component_parameter_value EMIF_10_STORED_PARAM {} + set_component_parameter_value EMIF_11_CONN_TO_CALIP {CALIP_0} + set_component_parameter_value EMIF_11_REF_CLK_SHARING {EXPORTED} + set_component_parameter_value EMIF_11_STORED_PARAM {} + set_component_parameter_value EMIF_12_CONN_TO_CALIP {CALIP_0} + set_component_parameter_value EMIF_12_REF_CLK_SHARING {EXPORTED} + set_component_parameter_value EMIF_12_STORED_PARAM {} + set_component_parameter_value EMIF_13_CONN_TO_CALIP {CALIP_0} + set_component_parameter_value EMIF_13_REF_CLK_SHARING {EXPORTED} + set_component_parameter_value EMIF_13_STORED_PARAM {} + set_component_parameter_value EMIF_14_CONN_TO_CALIP {CALIP_0} + set_component_parameter_value EMIF_14_REF_CLK_SHARING {EXPORTED} + set_component_parameter_value EMIF_14_STORED_PARAM {} + set_component_parameter_value EMIF_15_CONN_TO_CALIP {CALIP_0} + set_component_parameter_value EMIF_15_REF_CLK_SHARING {EXPORTED} + set_component_parameter_value EMIF_15_STORED_PARAM {} + set_component_parameter_value EMIF_1_CONN_TO_CALIP {CALIP_0} + set_component_parameter_value EMIF_1_REF_CLK_SHARING {EXPORTED} + set_component_parameter_value EMIF_1_STORED_PARAM {} + set_component_parameter_value EMIF_2_CONN_TO_CALIP {CALIP_0} + set_component_parameter_value EMIF_2_REF_CLK_SHARING {EXPORTED} + set_component_parameter_value EMIF_2_STORED_PARAM {} + set_component_parameter_value EMIF_3_CONN_TO_CALIP {CALIP_0} + set_component_parameter_value EMIF_3_REF_CLK_SHARING {EXPORTED} + set_component_parameter_value EMIF_3_STORED_PARAM {} + set_component_parameter_value EMIF_4_CONN_TO_CALIP {CALIP_0} + set_component_parameter_value EMIF_4_REF_CLK_SHARING {EXPORTED} + set_component_parameter_value EMIF_4_STORED_PARAM {} + set_component_parameter_value EMIF_5_CONN_TO_CALIP {CALIP_0} + set_component_parameter_value EMIF_5_REF_CLK_SHARING {EXPORTED} + set_component_parameter_value EMIF_5_STORED_PARAM {} + set_component_parameter_value EMIF_6_CONN_TO_CALIP {CALIP_0} + set_component_parameter_value EMIF_6_REF_CLK_SHARING {EXPORTED} + set_component_parameter_value EMIF_6_STORED_PARAM {} + set_component_parameter_value EMIF_7_CONN_TO_CALIP {CALIP_0} + set_component_parameter_value EMIF_7_REF_CLK_SHARING {EXPORTED} + set_component_parameter_value EMIF_7_STORED_PARAM {} + set_component_parameter_value EMIF_8_CONN_TO_CALIP {CALIP_0} + set_component_parameter_value EMIF_8_REF_CLK_SHARING {EXPORTED} + set_component_parameter_value EMIF_8_STORED_PARAM {} + set_component_parameter_value EMIF_9_CONN_TO_CALIP {CALIP_0} + set_component_parameter_value EMIF_9_REF_CLK_SHARING {EXPORTED} + set_component_parameter_value EMIF_9_STORED_PARAM {} + set_component_parameter_value EX_DESIGN_GUI_DDR3_GEN_BSI {0} + set_component_parameter_value EX_DESIGN_GUI_DDR3_GEN_CDC {0} + set_component_parameter_value EX_DESIGN_GUI_DDR3_GEN_SIM {1} + set_component_parameter_value EX_DESIGN_GUI_DDR3_GEN_SYNTH {1} + set_component_parameter_value EX_DESIGN_GUI_DDR3_HDL_FORMAT {HDL_FORMAT_VERILOG} + set_component_parameter_value EX_DESIGN_GUI_DDR3_PREV_PRESET {TARGET_DEV_KIT_NONE} + set_component_parameter_value EX_DESIGN_GUI_DDR3_SEL_DESIGN {AVAIL_EX_DESIGNS_GEN_DESIGN} + set_component_parameter_value EX_DESIGN_GUI_DDR3_TARGET_DEV_KIT {TARGET_DEV_KIT_NONE} + set_component_parameter_value EX_DESIGN_GUI_DDR4_GEN_BSI {0} + set_component_parameter_value EX_DESIGN_GUI_DDR4_GEN_CDC {0} + set_component_parameter_value EX_DESIGN_GUI_DDR4_GEN_SIM {1} + set_component_parameter_value EX_DESIGN_GUI_DDR4_GEN_SYNTH {1} + set_component_parameter_value EX_DESIGN_GUI_DDR4_HDL_FORMAT {HDL_FORMAT_VERILOG} + set_component_parameter_value EX_DESIGN_GUI_DDR4_PREV_PRESET {TARGET_DEV_KIT_NONE} + set_component_parameter_value EX_DESIGN_GUI_DDR4_SEL_DESIGN {AVAIL_EX_DESIGNS_GEN_DESIGN} + set_component_parameter_value EX_DESIGN_GUI_DDR4_TARGET_DEV_KIT {TARGET_DEV_KIT_NONE} + set_component_parameter_value EX_DESIGN_GUI_DDRT_GEN_BSI {0} + set_component_parameter_value EX_DESIGN_GUI_DDRT_GEN_CDC {0} + set_component_parameter_value EX_DESIGN_GUI_DDRT_GEN_SIM {1} + set_component_parameter_value EX_DESIGN_GUI_DDRT_GEN_SYNTH {1} + set_component_parameter_value EX_DESIGN_GUI_DDRT_HDL_FORMAT {HDL_FORMAT_VERILOG} + set_component_parameter_value EX_DESIGN_GUI_DDRT_PREV_PRESET {TARGET_DEV_KIT_NONE} + set_component_parameter_value EX_DESIGN_GUI_DDRT_SEL_DESIGN {AVAIL_EX_DESIGNS_GEN_DESIGN} + set_component_parameter_value EX_DESIGN_GUI_DDRT_TARGET_DEV_KIT {TARGET_DEV_KIT_NONE} + set_component_parameter_value EX_DESIGN_GUI_LPDDR3_GEN_BSI {0} + set_component_parameter_value EX_DESIGN_GUI_LPDDR3_GEN_CDC {0} + set_component_parameter_value EX_DESIGN_GUI_LPDDR3_GEN_SIM {1} + set_component_parameter_value EX_DESIGN_GUI_LPDDR3_GEN_SYNTH {1} + set_component_parameter_value EX_DESIGN_GUI_LPDDR3_HDL_FORMAT {HDL_FORMAT_VERILOG} + set_component_parameter_value EX_DESIGN_GUI_LPDDR3_PREV_PRESET {TARGET_DEV_KIT_NONE} + set_component_parameter_value EX_DESIGN_GUI_LPDDR3_SEL_DESIGN {AVAIL_EX_DESIGNS_GEN_DESIGN} + set_component_parameter_value EX_DESIGN_GUI_LPDDR3_TARGET_DEV_KIT {TARGET_DEV_KIT_NONE} + set_component_parameter_value EX_DESIGN_GUI_QDR2_GEN_BSI {0} + set_component_parameter_value EX_DESIGN_GUI_QDR2_GEN_CDC {0} + set_component_parameter_value EX_DESIGN_GUI_QDR2_GEN_SIM {1} + set_component_parameter_value EX_DESIGN_GUI_QDR2_GEN_SYNTH {1} + set_component_parameter_value EX_DESIGN_GUI_QDR2_HDL_FORMAT {HDL_FORMAT_VERILOG} + set_component_parameter_value EX_DESIGN_GUI_QDR2_PREV_PRESET {TARGET_DEV_KIT_NONE} + set_component_parameter_value EX_DESIGN_GUI_QDR2_SEL_DESIGN {AVAIL_EX_DESIGNS_GEN_DESIGN} + set_component_parameter_value EX_DESIGN_GUI_QDR2_TARGET_DEV_KIT {TARGET_DEV_KIT_NONE} + set_component_parameter_value EX_DESIGN_GUI_QDR4_GEN_BSI {0} + set_component_parameter_value EX_DESIGN_GUI_QDR4_GEN_CDC {0} + set_component_parameter_value EX_DESIGN_GUI_QDR4_GEN_SIM {1} + set_component_parameter_value EX_DESIGN_GUI_QDR4_GEN_SYNTH {1} + set_component_parameter_value EX_DESIGN_GUI_QDR4_HDL_FORMAT {HDL_FORMAT_VERILOG} + set_component_parameter_value EX_DESIGN_GUI_QDR4_PREV_PRESET {TARGET_DEV_KIT_NONE} + set_component_parameter_value EX_DESIGN_GUI_QDR4_SEL_DESIGN {AVAIL_EX_DESIGNS_GEN_DESIGN} + set_component_parameter_value EX_DESIGN_GUI_QDR4_TARGET_DEV_KIT {TARGET_DEV_KIT_NONE} + set_component_parameter_value EX_DESIGN_GUI_RLD2_GEN_BSI {0} + set_component_parameter_value EX_DESIGN_GUI_RLD2_GEN_CDC {0} + set_component_parameter_value EX_DESIGN_GUI_RLD2_GEN_SIM {1} + set_component_parameter_value EX_DESIGN_GUI_RLD2_GEN_SYNTH {1} + set_component_parameter_value EX_DESIGN_GUI_RLD2_HDL_FORMAT {HDL_FORMAT_VERILOG} + set_component_parameter_value EX_DESIGN_GUI_RLD2_PREV_PRESET {TARGET_DEV_KIT_NONE} + set_component_parameter_value EX_DESIGN_GUI_RLD2_SEL_DESIGN {AVAIL_EX_DESIGNS_GEN_DESIGN} + set_component_parameter_value EX_DESIGN_GUI_RLD2_TARGET_DEV_KIT {TARGET_DEV_KIT_NONE} + set_component_parameter_value EX_DESIGN_GUI_RLD3_GEN_BSI {0} + set_component_parameter_value EX_DESIGN_GUI_RLD3_GEN_CDC {0} + set_component_parameter_value EX_DESIGN_GUI_RLD3_GEN_SIM {1} + set_component_parameter_value EX_DESIGN_GUI_RLD3_GEN_SYNTH {1} + set_component_parameter_value EX_DESIGN_GUI_RLD3_HDL_FORMAT {HDL_FORMAT_VERILOG} + set_component_parameter_value EX_DESIGN_GUI_RLD3_PREV_PRESET {TARGET_DEV_KIT_NONE} + set_component_parameter_value EX_DESIGN_GUI_RLD3_SEL_DESIGN {AVAIL_EX_DESIGNS_GEN_DESIGN} + set_component_parameter_value EX_DESIGN_GUI_RLD3_TARGET_DEV_KIT {TARGET_DEV_KIT_NONE} + set_component_parameter_value INTERNAL_TESTING_MODE {0} + set_component_parameter_value IS_ED_SLAVE {0} + set_component_parameter_value MEM_DDR3_ALERT_N_DQS_GROUP {0} + set_component_parameter_value MEM_DDR3_ALERT_N_PLACEMENT_ENUM {DDR3_ALERT_N_PLACEMENT_AC_LANES} + set_component_parameter_value MEM_DDR3_ASR_ENUM {DDR3_ASR_MANUAL} + set_component_parameter_value MEM_DDR3_ATCL_ENUM {DDR3_ATCL_DISABLED} + set_component_parameter_value MEM_DDR3_BANK_ADDR_WIDTH {3} + set_component_parameter_value MEM_DDR3_BL_ENUM {DDR3_BL_BL8} + set_component_parameter_value MEM_DDR3_BT_ENUM {DDR3_BT_SEQUENTIAL} + set_component_parameter_value MEM_DDR3_CFG_GEN_DBE {0} + set_component_parameter_value MEM_DDR3_CFG_GEN_SBE {0} + set_component_parameter_value MEM_DDR3_CKE_PER_DIMM {1} + set_component_parameter_value MEM_DDR3_CK_WIDTH {1} + set_component_parameter_value MEM_DDR3_COL_ADDR_WIDTH {10} + set_component_parameter_value MEM_DDR3_DISCRETE_CS_WIDTH {1} + set_component_parameter_value MEM_DDR3_DISCRETE_MIRROR_ADDRESSING_EN {0} + set_component_parameter_value MEM_DDR3_DLL_EN {1} + set_component_parameter_value MEM_DDR3_DM_EN {1} + set_component_parameter_value MEM_DDR3_DQ_PER_DQS {8} + set_component_parameter_value MEM_DDR3_DQ_WIDTH {72} + set_component_parameter_value MEM_DDR3_DRV_STR_ENUM {DDR3_DRV_STR_RZQ_7} + set_component_parameter_value MEM_DDR3_FORMAT_ENUM {MEM_FORMAT_UDIMM} + set_component_parameter_value MEM_DDR3_HIDE_ADV_MR_SETTINGS {1} + set_component_parameter_value MEM_DDR3_LRDIMM_EXTENDED_CONFIG {000000000000000000} + set_component_parameter_value MEM_DDR3_MIRROR_ADDRESSING_EN {1} + set_component_parameter_value MEM_DDR3_NUM_OF_DIMMS {1} + set_component_parameter_value MEM_DDR3_PD_ENUM {DDR3_PD_OFF} + set_component_parameter_value MEM_DDR3_RANKS_PER_DIMM {1} + set_component_parameter_value MEM_DDR3_RDIMM_CONFIG {0000000000000000} + set_component_parameter_value MEM_DDR3_ROW_ADDR_WIDTH {15} + set_component_parameter_value MEM_DDR3_RTT_NOM_ENUM {DDR3_RTT_NOM_ODT_DISABLED} + set_component_parameter_value MEM_DDR3_RTT_WR_ENUM {DDR3_RTT_WR_RZQ_4} + set_component_parameter_value MEM_DDR3_R_ODT0_1X1 {off} + set_component_parameter_value MEM_DDR3_R_ODT0_2X2 {off off} + set_component_parameter_value MEM_DDR3_R_ODT0_4X2 {off off on on} + set_component_parameter_value MEM_DDR3_R_ODT0_4X4 {off off on off} + set_component_parameter_value MEM_DDR3_R_ODT1_2X2 {off off} + set_component_parameter_value MEM_DDR3_R_ODT1_4X2 {on on off off} + set_component_parameter_value MEM_DDR3_R_ODT1_4X4 {off off off on} + set_component_parameter_value MEM_DDR3_R_ODT2_4X4 {on off off off} + set_component_parameter_value MEM_DDR3_R_ODT3_4X4 {off on off off} + set_component_parameter_value MEM_DDR3_R_ODTN_1X1 {Rank\ 0} + set_component_parameter_value MEM_DDR3_R_ODTN_2X2 {Rank\ 0 Rank\ 1} + set_component_parameter_value MEM_DDR3_R_ODTN_4X2 {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} + set_component_parameter_value MEM_DDR3_R_ODTN_4X4 {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} + set_component_parameter_value MEM_DDR3_SPEEDBIN_ENUM {DDR3_SPEEDBIN_2133} + set_component_parameter_value MEM_DDR3_SRT_ENUM {DDR3_SRT_NORMAL} + set_component_parameter_value MEM_DDR3_TCL {14} + set_component_parameter_value MEM_DDR3_TDH_DC_MV {100} + set_component_parameter_value MEM_DDR3_TDH_PS {55} + set_component_parameter_value MEM_DDR3_TDQSCK_PS {180} + set_component_parameter_value MEM_DDR3_TDQSQ_PS {75} + set_component_parameter_value MEM_DDR3_TDQSS_CYC {0.27} + set_component_parameter_value MEM_DDR3_TDSH_CYC {0.18} + set_component_parameter_value MEM_DDR3_TDSS_CYC {0.18} + set_component_parameter_value MEM_DDR3_TDS_AC_MV {135} + set_component_parameter_value MEM_DDR3_TDS_PS {53} + set_component_parameter_value MEM_DDR3_TFAW_NS {25.0} + set_component_parameter_value MEM_DDR3_TIH_DC_MV {100} + set_component_parameter_value MEM_DDR3_TIH_PS {95} + set_component_parameter_value MEM_DDR3_TINIT_US {500} + set_component_parameter_value MEM_DDR3_TIS_AC_MV {135} + set_component_parameter_value MEM_DDR3_TIS_PS {60} + set_component_parameter_value MEM_DDR3_TMRD_CK_CYC {4} + set_component_parameter_value MEM_DDR3_TQH_CYC {0.38} + set_component_parameter_value MEM_DDR3_TQSH_CYC {0.4} + set_component_parameter_value MEM_DDR3_TRAS_NS {33.0} + set_component_parameter_value MEM_DDR3_TRCD_NS {13.09} + set_component_parameter_value MEM_DDR3_TREFI_US {7.8} + set_component_parameter_value MEM_DDR3_TRFC_NS {160.0} + set_component_parameter_value MEM_DDR3_TRP_NS {13.09} + set_component_parameter_value MEM_DDR3_TRRD_CYC {6} + set_component_parameter_value MEM_DDR3_TRTP_CYC {8} + set_component_parameter_value MEM_DDR3_TWLH_PS {125.0} + set_component_parameter_value MEM_DDR3_TWLS_PS {125.0} + set_component_parameter_value MEM_DDR3_TWR_NS {15.0} + set_component_parameter_value MEM_DDR3_TWTR_CYC {8} + set_component_parameter_value MEM_DDR3_USE_DEFAULT_ODT {1} + set_component_parameter_value MEM_DDR3_WTCL {10} + set_component_parameter_value MEM_DDR3_W_ODT0_1X1 {on} + set_component_parameter_value MEM_DDR3_W_ODT0_2X2 {on off} + set_component_parameter_value MEM_DDR3_W_ODT0_4X2 {off off on on} + set_component_parameter_value MEM_DDR3_W_ODT0_4X4 {on off on off} + set_component_parameter_value MEM_DDR3_W_ODT1_2X2 {off on} + set_component_parameter_value MEM_DDR3_W_ODT1_4X2 {on on off off} + set_component_parameter_value MEM_DDR3_W_ODT1_4X4 {off on off on} + set_component_parameter_value MEM_DDR3_W_ODT2_4X4 {on off on off} + set_component_parameter_value MEM_DDR3_W_ODT3_4X4 {off on off on} + set_component_parameter_value MEM_DDR3_W_ODTN_1X1 {Rank\ 0} + set_component_parameter_value MEM_DDR3_W_ODTN_2X2 {Rank\ 0 Rank\ 1} + set_component_parameter_value MEM_DDR3_W_ODTN_4X2 {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} + set_component_parameter_value MEM_DDR3_W_ODTN_4X4 {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} + set_component_parameter_value MEM_DDR4_AC_PARITY_LATENCY {DDR4_AC_PARITY_LATENCY_DISABLE} + set_component_parameter_value MEM_DDR4_AC_PERSISTENT_ERROR {0} + set_component_parameter_value MEM_DDR4_ALERT_N_AC_LANE {3} + set_component_parameter_value MEM_DDR4_ALERT_N_AC_PIN {8} + set_component_parameter_value MEM_DDR4_ALERT_N_DQS_GROUP {0} + set_component_parameter_value MEM_DDR4_ALERT_N_PLACEMENT_ENUM {DDR4_ALERT_N_PLACEMENT_FM_LANE3} + set_component_parameter_value MEM_DDR4_ALERT_PAR_EN {1} + set_component_parameter_value MEM_DDR4_ASR_ENUM {DDR4_ASR_MANUAL_NORMAL} + set_component_parameter_value MEM_DDR4_ATCL_ENUM {DDR4_ATCL_DISABLED} + set_component_parameter_value MEM_DDR4_BANK_ADDR_WIDTH {2} + set_component_parameter_value MEM_DDR4_BANK_GROUP_WIDTH {2} + set_component_parameter_value MEM_DDR4_BL_ENUM {DDR4_BL_BL8} + set_component_parameter_value MEM_DDR4_BT_ENUM {DDR4_BT_SEQUENTIAL} + set_component_parameter_value MEM_DDR4_CAL_MODE {0} + set_component_parameter_value MEM_DDR4_CFG_GEN_DBE {0} + set_component_parameter_value MEM_DDR4_CFG_GEN_SBE {0} + set_component_parameter_value MEM_DDR4_CHIP_ID_WIDTH {0} + set_component_parameter_value MEM_DDR4_CKE_PER_DIMM {1} + set_component_parameter_value MEM_DDR4_CK_WIDTH {1} + set_component_parameter_value MEM_DDR4_COL_ADDR_WIDTH {10} + set_component_parameter_value MEM_DDR4_DB_DQ_DRV_ENUM {DDR4_DB_DRV_STR_RZQ_7} + set_component_parameter_value MEM_DDR4_DB_RTT_NOM_ENUM {DDR4_DB_RTT_NOM_ODT_DISABLED} + set_component_parameter_value MEM_DDR4_DB_RTT_PARK_ENUM {DDR4_DB_RTT_PARK_ODT_DISABLED} + set_component_parameter_value MEM_DDR4_DB_RTT_WR_ENUM {DDR4_DB_RTT_WR_RZQ_3} + set_component_parameter_value MEM_DDR4_DEFAULT_VREFOUT {1} + set_component_parameter_value MEM_DDR4_DISCRETE_CS_WIDTH {1} + set_component_parameter_value MEM_DDR4_DISCRETE_MIRROR_ADDRESSING_EN {0} + set_component_parameter_value MEM_DDR4_DLL_EN {1} + set_component_parameter_value MEM_DDR4_DM_EN {1} + set_component_parameter_value MEM_DDR4_DQ_PER_DQS {8} + set_component_parameter_value MEM_DDR4_DQ_WIDTH {72} + set_component_parameter_value MEM_DDR4_DRV_STR_ENUM {DDR4_DRV_STR_RZQ_7} + set_component_parameter_value MEM_DDR4_FINE_GRANULARITY_REFRESH {DDR4_FINE_REFRESH_FIXED_1X} + set_component_parameter_value MEM_DDR4_FORMAT_ENUM {MEM_FORMAT_RDIMM} + set_component_parameter_value MEM_DDR4_GEARDOWN {DDR4_GEARDOWN_HR} + set_component_parameter_value MEM_DDR4_HIDE_ADV_MR_SETTINGS {1} + set_component_parameter_value MEM_DDR4_INTEL_DEFAULT_TERM {1} + set_component_parameter_value MEM_DDR4_INTERNAL_VREFDQ_MONITOR {0} + set_component_parameter_value MEM_DDR4_LRDIMM_ODT_LESS_BS {1} + set_component_parameter_value MEM_DDR4_LRDIMM_ODT_LESS_BS_PARK_OHM {240} + set_component_parameter_value MEM_DDR4_LRDIMM_VREFDQ_VALUE {} + set_component_parameter_value MEM_DDR4_MAX_POWERDOWN {0} + set_component_parameter_value MEM_DDR4_MIRROR_ADDRESSING_EN {1} + set_component_parameter_value MEM_DDR4_MPR_READ_FORMAT {DDR4_MPR_READ_FORMAT_SERIAL} + set_component_parameter_value MEM_DDR4_NUM_OF_DIMMS {1} + set_component_parameter_value MEM_DDR4_ODT_IN_POWERDOWN {1} + set_component_parameter_value MEM_DDR4_PER_DRAM_ADDR {0} + set_component_parameter_value MEM_DDR4_RANKS_PER_DIMM {1} + set_component_parameter_value MEM_DDR4_RCD_CA_IBT_ENUM {DDR4_RCD_CA_IBT_100} + set_component_parameter_value MEM_DDR4_RCD_CKE_IBT_ENUM {DDR4_RCD_CKE_IBT_100} + set_component_parameter_value MEM_DDR4_RCD_CS_IBT_ENUM {DDR4_RCD_CS_IBT_100} + set_component_parameter_value MEM_DDR4_RCD_ODT_IBT_ENUM {DDR4_RCD_ODT_IBT_100} + set_component_parameter_value MEM_DDR4_READ_DBI {1} + set_component_parameter_value MEM_DDR4_READ_PREAMBLE {2} + set_component_parameter_value MEM_DDR4_READ_PREAMBLE_TRAINING {0} + set_component_parameter_value MEM_DDR4_ROW_ADDR_WIDTH {16} + set_component_parameter_value MEM_DDR4_RTT_NOM_ENUM {DDR4_RTT_NOM_RZQ_4} + set_component_parameter_value MEM_DDR4_RTT_PARK {DDR4_RTT_PARK_ODT_DISABLED} + set_component_parameter_value MEM_DDR4_RTT_WR_ENUM {DDR4_RTT_WR_ODT_DISABLED} + set_component_parameter_value MEM_DDR4_R_ODT0_1X1 {off} + set_component_parameter_value MEM_DDR4_R_ODT0_2X2 {off off} + set_component_parameter_value MEM_DDR4_R_ODT0_4X2 {off off on on} + set_component_parameter_value MEM_DDR4_R_ODT0_4X4 {off off on off} + set_component_parameter_value MEM_DDR4_R_ODT1_2X2 {off off} + set_component_parameter_value MEM_DDR4_R_ODT1_4X2 {on on off off} + set_component_parameter_value MEM_DDR4_R_ODT1_4X4 {off off off on} + set_component_parameter_value MEM_DDR4_R_ODT2_4X4 {on off off off} + set_component_parameter_value MEM_DDR4_R_ODT3_4X4 {off on off off} + set_component_parameter_value MEM_DDR4_R_ODTN_1X1 {Rank\ 0} + set_component_parameter_value MEM_DDR4_R_ODTN_2X2 {Rank\ 0 Rank\ 1} + set_component_parameter_value MEM_DDR4_R_ODTN_4X2 {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} + set_component_parameter_value MEM_DDR4_R_ODTN_4X4 {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} + set_component_parameter_value MEM_DDR4_SELF_RFSH_ABORT {0} + set_component_parameter_value MEM_DDR4_SPD_133_RCD_DB_VENDOR_LSB {0} + set_component_parameter_value MEM_DDR4_SPD_134_RCD_DB_VENDOR_MSB {0} + set_component_parameter_value MEM_DDR4_SPD_135_RCD_REV {0} + set_component_parameter_value MEM_DDR4_SPD_137_RCD_CA_DRV {101} + set_component_parameter_value MEM_DDR4_SPD_138_RCD_CK_DRV {5} + set_component_parameter_value MEM_DDR4_SPD_139_DB_REV {0} + set_component_parameter_value MEM_DDR4_SPD_140_DRAM_VREFDQ_R0 {29} + set_component_parameter_value MEM_DDR4_SPD_141_DRAM_VREFDQ_R1 {29} + set_component_parameter_value MEM_DDR4_SPD_142_DRAM_VREFDQ_R2 {29} + set_component_parameter_value MEM_DDR4_SPD_143_DRAM_VREFDQ_R3 {29} + set_component_parameter_value MEM_DDR4_SPD_144_DB_VREFDQ {37} + set_component_parameter_value MEM_DDR4_SPD_145_DB_MDQ_DRV {21} + set_component_parameter_value MEM_DDR4_SPD_148_DRAM_DRV {0} + set_component_parameter_value MEM_DDR4_SPD_149_DRAM_RTT_WR_NOM {20} + set_component_parameter_value MEM_DDR4_SPD_152_DRAM_RTT_PARK {39} + set_component_parameter_value MEM_DDR4_SPD_155_DB_VREFDQ_RANGE {0} + set_component_parameter_value MEM_DDR4_SPEEDBIN_ENUM {DDR4_SPEEDBIN_2666} + set_component_parameter_value MEM_DDR4_TCCD_L_CYC {6} + set_component_parameter_value MEM_DDR4_TCCD_S_CYC {4} + set_component_parameter_value MEM_DDR4_TCL {21} + set_component_parameter_value MEM_DDR4_TDIVW_DJ_CYC {0.1} + set_component_parameter_value MEM_DDR4_TDIVW_TOTAL_UI {0.2} + set_component_parameter_value MEM_DDR4_TDQSCK_PS {175} + set_component_parameter_value MEM_DDR4_TDQSQ_PS {66} + set_component_parameter_value MEM_DDR4_TDQSQ_UI {0.14} + set_component_parameter_value MEM_DDR4_TDQSS_CYC {0.27} + set_component_parameter_value MEM_DDR4_TDSH_CYC {0.18} + set_component_parameter_value MEM_DDR4_TDSS_CYC {0.18} + set_component_parameter_value MEM_DDR4_TDVWP_UI {0.72} + set_component_parameter_value MEM_DDR4_TEMP_CONTROLLED_RFSH_ENA {0} + set_component_parameter_value MEM_DDR4_TEMP_CONTROLLED_RFSH_RANGE {DDR4_TEMP_CONTROLLED_RFSH_NORMAL} + set_component_parameter_value MEM_DDR4_TEMP_SENSOR_READOUT {0} + set_component_parameter_value MEM_DDR4_TFAW_DLR_CYC {16} + set_component_parameter_value MEM_DDR4_TFAW_NS {21.0} + set_component_parameter_value MEM_DDR4_TIH_DC_MV {75} + set_component_parameter_value MEM_DDR4_TIH_PS {87} + set_component_parameter_value MEM_DDR4_TINIT_US {500} + set_component_parameter_value MEM_DDR4_TIS_AC_MV {100} + set_component_parameter_value MEM_DDR4_TIS_PS {62} + set_component_parameter_value MEM_DDR4_TMRD_CK_CYC {8} + set_component_parameter_value MEM_DDR4_TQH_CYC {0.38} + set_component_parameter_value MEM_DDR4_TQH_UI {0.74} + set_component_parameter_value MEM_DDR4_TQSH_CYC {0.4} + set_component_parameter_value MEM_DDR4_TRAS_NS {32.0} + set_component_parameter_value MEM_DDR4_TRCD_NS {14.16} + set_component_parameter_value MEM_DDR4_TREFI_US {7.8} + set_component_parameter_value MEM_DDR4_TRFC_DLR_NS {90.0} + set_component_parameter_value MEM_DDR4_TRFC_NS {350.0} + set_component_parameter_value MEM_DDR4_TRP_NS {14.16} + set_component_parameter_value MEM_DDR4_TRRD_DLR_CYC {4} + set_component_parameter_value MEM_DDR4_TRRD_L_CYC {6} + set_component_parameter_value MEM_DDR4_TRRD_S_CYC {4} + set_component_parameter_value MEM_DDR4_TWLH_CYC {0.13} + set_component_parameter_value MEM_DDR4_TWLH_PS {0.0} + set_component_parameter_value MEM_DDR4_TWLS_CYC {0.13} + set_component_parameter_value MEM_DDR4_TWLS_PS {0.0} + set_component_parameter_value MEM_DDR4_TWR_NS {15.0} + set_component_parameter_value MEM_DDR4_TWTR_L_CYC {9} + set_component_parameter_value MEM_DDR4_TWTR_S_CYC {3} + set_component_parameter_value MEM_DDR4_USER_VREFDQ_TRAINING_RANGE {DDR4_VREFDQ_TRAINING_RANGE_1} + set_component_parameter_value MEM_DDR4_USER_VREFDQ_TRAINING_VALUE {56.0} + set_component_parameter_value MEM_DDR4_USE_DEFAULT_ODT {1} + set_component_parameter_value MEM_DDR4_VDIVW_TOTAL {130} + set_component_parameter_value MEM_DDR4_WRITE_CRC {0} + set_component_parameter_value MEM_DDR4_WRITE_DBI {0} + set_component_parameter_value MEM_DDR4_WRITE_PREAMBLE {1} + set_component_parameter_value MEM_DDR4_WTCL {16} + set_component_parameter_value MEM_DDR4_W_ODT0_1X1 {on} + set_component_parameter_value MEM_DDR4_W_ODT0_2X2 {on off} + set_component_parameter_value MEM_DDR4_W_ODT0_4X2 {off off on on} + set_component_parameter_value MEM_DDR4_W_ODT0_4X4 {on off on off} + set_component_parameter_value MEM_DDR4_W_ODT1_2X2 {off on} + set_component_parameter_value MEM_DDR4_W_ODT1_4X2 {on on off off} + set_component_parameter_value MEM_DDR4_W_ODT1_4X4 {off on off on} + set_component_parameter_value MEM_DDR4_W_ODT2_4X4 {on off on off} + set_component_parameter_value MEM_DDR4_W_ODT3_4X4 {off on off on} + set_component_parameter_value MEM_DDR4_W_ODTN_1X1 {Rank\ 0} + set_component_parameter_value MEM_DDR4_W_ODTN_2X2 {Rank\ 0 Rank\ 1} + set_component_parameter_value MEM_DDR4_W_ODTN_4X2 {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} + set_component_parameter_value MEM_DDR4_W_ODTN_4X4 {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} + set_component_parameter_value MEM_DDRT_AC_PARITY_LATENCY {DDRT_AC_PARITY_LATENCY_DISABLE} + set_component_parameter_value MEM_DDRT_AC_PERSISTENT_ERROR {0} + set_component_parameter_value MEM_DDRT_ALERT_N_AC_LANE {0} + set_component_parameter_value MEM_DDRT_ALERT_N_AC_PIN {0} + set_component_parameter_value MEM_DDRT_ALERT_N_DQS_GROUP {0} + set_component_parameter_value MEM_DDRT_ALERT_N_PLACEMENT_ENUM {DDRT_ALERT_N_PLACEMENT_AUTO} + set_component_parameter_value MEM_DDRT_ALERT_PAR_EN {1} + set_component_parameter_value MEM_DDRT_ASR_ENUM {DDRT_ASR_MANUAL_NORMAL} + set_component_parameter_value MEM_DDRT_ATCL_ENUM {DDRT_ATCL_DISABLED} + set_component_parameter_value MEM_DDRT_BANK_ADDR_WIDTH {2} + set_component_parameter_value MEM_DDRT_BANK_GROUP_WIDTH {2} + set_component_parameter_value MEM_DDRT_BL_ENUM {DDRT_BL_BL8} + set_component_parameter_value MEM_DDRT_BT_ENUM {DDRT_BT_SEQUENTIAL} + set_component_parameter_value MEM_DDRT_CAL_MODE {0} + set_component_parameter_value MEM_DDRT_CFG_GEN_DBE {0} + set_component_parameter_value MEM_DDRT_CFG_GEN_SBE {0} + set_component_parameter_value MEM_DDRT_CKE_PER_DIMM {1} + set_component_parameter_value MEM_DDRT_COL_ADDR_WIDTH {10} + set_component_parameter_value MEM_DDRT_DB_DQ_DRV_ENUM {DDRT_DB_DRV_STR_RZQ_7} + set_component_parameter_value MEM_DDRT_DB_RTT_NOM_ENUM {DDRT_DB_RTT_NOM_ODT_DISABLED} + set_component_parameter_value MEM_DDRT_DB_RTT_PARK_ENUM {DDRT_DB_RTT_PARK_ODT_DISABLED} + set_component_parameter_value MEM_DDRT_DB_RTT_WR_ENUM {DDRT_DB_RTT_WR_RZQ_4} + set_component_parameter_value MEM_DDRT_DEFAULT_ADDED_LATENCY {1} + set_component_parameter_value MEM_DDRT_DEFAULT_PREAMBLE {1} + set_component_parameter_value MEM_DDRT_DEFAULT_VREFOUT {1} + set_component_parameter_value MEM_DDRT_DISCRETE_CS_WIDTH {1} + set_component_parameter_value MEM_DDRT_DISCRETE_MIRROR_ADDRESSING_EN {0} + set_component_parameter_value MEM_DDRT_DLL_EN {1} + set_component_parameter_value MEM_DDRT_DM_EN {0} + set_component_parameter_value MEM_DDRT_DQ_PER_DQS {4} + set_component_parameter_value MEM_DDRT_DQ_WIDTH {72} + set_component_parameter_value MEM_DDRT_DRV_STR_ENUM {DDRT_DRV_STR_RZQ_7} + set_component_parameter_value MEM_DDRT_FINE_GRANULARITY_REFRESH {DDRT_FINE_REFRESH_FIXED_1X} + set_component_parameter_value MEM_DDRT_FORMAT_ENUM {MEM_FORMAT_LRDIMM} + set_component_parameter_value MEM_DDRT_GEARDOWN {DDRT_GEARDOWN_HR} + set_component_parameter_value MEM_DDRT_HIDE_ADV_MR_SETTINGS {1} + set_component_parameter_value MEM_DDRT_HIDE_LATENCY_SETTINGS {1} + set_component_parameter_value MEM_DDRT_I2C_DIMM_0_SA {0} + set_component_parameter_value MEM_DDRT_I2C_DIMM_1_SA {1} + set_component_parameter_value MEM_DDRT_I2C_DIMM_2_SA {2} + set_component_parameter_value MEM_DDRT_I2C_DIMM_3_SA {3} + set_component_parameter_value MEM_DDRT_INTERNAL_VREFDQ_MONITOR {0} + set_component_parameter_value MEM_DDRT_LRDIMM_ODT_LESS_BS {0} + set_component_parameter_value MEM_DDRT_LRDIMM_ODT_LESS_BS_PARK_OHM {240} + set_component_parameter_value MEM_DDRT_LRDIMM_VREFDQ_VALUE {} + set_component_parameter_value MEM_DDRT_MAX_POWERDOWN {0} + set_component_parameter_value MEM_DDRT_MIRROR_ADDRESSING_EN {1} + set_component_parameter_value MEM_DDRT_MPR_READ_FORMAT {DDRT_MPR_READ_FORMAT_SERIAL} + set_component_parameter_value MEM_DDRT_NUM_OF_DIMMS {1} + set_component_parameter_value MEM_DDRT_ODT_IN_POWERDOWN {1} + set_component_parameter_value MEM_DDRT_PARTIAL_WRITES {0} + set_component_parameter_value MEM_DDRT_PERSISTENT_MODE {1} + set_component_parameter_value MEM_DDRT_PER_DRAM_ADDR {0} + set_component_parameter_value MEM_DDRT_PWR_MODE {DDRT_PWR_MODE_12W} + set_component_parameter_value MEM_DDRT_RANKS_PER_DIMM {1} + set_component_parameter_value MEM_DDRT_RCD_CA_IBT_ENUM {DDRT_RCD_CA_IBT_100} + set_component_parameter_value MEM_DDRT_RCD_CKE_IBT_ENUM {DDRT_RCD_CKE_IBT_100} + set_component_parameter_value MEM_DDRT_RCD_CS_IBT_ENUM {DDRT_RCD_CS_IBT_100} + set_component_parameter_value MEM_DDRT_RCD_ODT_IBT_ENUM {DDRT_RCD_ODT_IBT_100} + set_component_parameter_value MEM_DDRT_READ_DBI {0} + set_component_parameter_value MEM_DDRT_READ_PREAMBLE_TRAINING {0} + set_component_parameter_value MEM_DDRT_ROW_ADDR_WIDTH {18} + set_component_parameter_value MEM_DDRT_RTT_NOM_ENUM {DDRT_RTT_NOM_RZQ_4} + set_component_parameter_value MEM_DDRT_RTT_PARK {DDRT_RTT_PARK_ODT_DISABLED} + set_component_parameter_value MEM_DDRT_RTT_WR_ENUM {DDRT_RTT_WR_ODT_DISABLED} + set_component_parameter_value MEM_DDRT_R_ODT0_1X1 {off} + set_component_parameter_value MEM_DDRT_R_ODT0_2X2 {off off} + set_component_parameter_value MEM_DDRT_R_ODT0_4X2 {off off on on} + set_component_parameter_value MEM_DDRT_R_ODT0_4X4 {off off off off} + set_component_parameter_value MEM_DDRT_R_ODT1_2X2 {off off} + set_component_parameter_value MEM_DDRT_R_ODT1_4X2 {on on off off} + set_component_parameter_value MEM_DDRT_R_ODT1_4X4 {off off on on} + set_component_parameter_value MEM_DDRT_R_ODT2_4X4 {off off off off} + set_component_parameter_value MEM_DDRT_R_ODT3_4X4 {on on off off} + set_component_parameter_value MEM_DDRT_R_ODTN_1X1 {Rank\ 0} + set_component_parameter_value MEM_DDRT_R_ODTN_2X2 {Rank\ 0 Rank\ 1} + set_component_parameter_value MEM_DDRT_R_ODTN_4X2 {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} + set_component_parameter_value MEM_DDRT_R_ODTN_4X4 {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} + set_component_parameter_value MEM_DDRT_SELF_RFSH_ABORT {0} + set_component_parameter_value MEM_DDRT_SPD_133_RCD_DB_VENDOR_LSB {0} + set_component_parameter_value MEM_DDRT_SPD_134_RCD_DB_VENDOR_MSB {0} + set_component_parameter_value MEM_DDRT_SPD_135_RCD_REV {0} + set_component_parameter_value MEM_DDRT_SPD_137_RCD_CA_DRV {85} + set_component_parameter_value MEM_DDRT_SPD_138_RCD_CK_DRV {5} + set_component_parameter_value MEM_DDRT_SPD_139_DB_REV {0} + set_component_parameter_value MEM_DDRT_SPD_140_DRAM_VREFDQ_R0 {29} + set_component_parameter_value MEM_DDRT_SPD_141_DRAM_VREFDQ_R1 {29} + set_component_parameter_value MEM_DDRT_SPD_142_DRAM_VREFDQ_R2 {29} + set_component_parameter_value MEM_DDRT_SPD_143_DRAM_VREFDQ_R3 {29} + set_component_parameter_value MEM_DDRT_SPD_144_DB_VREFDQ {25} + set_component_parameter_value MEM_DDRT_SPD_145_DB_MDQ_DRV {21} + set_component_parameter_value MEM_DDRT_SPD_148_DRAM_DRV {0} + set_component_parameter_value MEM_DDRT_SPD_149_DRAM_RTT_WR_NOM {20} + set_component_parameter_value MEM_DDRT_SPD_152_DRAM_RTT_PARK {39} + set_component_parameter_value MEM_DDRT_SPEEDBIN_ENUM {DDRT_SPEEDBIN_2400} + set_component_parameter_value MEM_DDRT_TCCD_L_CYC {6} + set_component_parameter_value MEM_DDRT_TCCD_S_CYC {4} + set_component_parameter_value MEM_DDRT_TCL {15} + set_component_parameter_value MEM_DDRT_TDIVW_DJ_CYC {0.1} + set_component_parameter_value MEM_DDRT_TDIVW_TOTAL_UI {0.2} + set_component_parameter_value MEM_DDRT_TDQSCK_PS {165} + set_component_parameter_value MEM_DDRT_TDQSQ_PS {66} + set_component_parameter_value MEM_DDRT_TDQSQ_UI {0.16} + set_component_parameter_value MEM_DDRT_TDQSS_CYC {0.27} + set_component_parameter_value MEM_DDRT_TDSH_CYC {0.18} + set_component_parameter_value MEM_DDRT_TDSS_CYC {0.18} + set_component_parameter_value MEM_DDRT_TDVWP_UI {0.72} + set_component_parameter_value MEM_DDRT_TEMP_CONTROLLED_RFSH_ENA {0} + set_component_parameter_value MEM_DDRT_TEMP_CONTROLLED_RFSH_RANGE {DDRT_TEMP_CONTROLLED_RFSH_NORMAL} + set_component_parameter_value MEM_DDRT_TEMP_SENSOR_READOUT {0} + set_component_parameter_value MEM_DDRT_TFAW_DLR_CYC {16} + set_component_parameter_value MEM_DDRT_TFAW_NS {21.0} + set_component_parameter_value MEM_DDRT_TIH_DC_MV {75} + set_component_parameter_value MEM_DDRT_TIH_PS {95} + set_component_parameter_value MEM_DDRT_TINIT_US {500} + set_component_parameter_value MEM_DDRT_TIS_AC_MV {100} + set_component_parameter_value MEM_DDRT_TIS_PS {60} + set_component_parameter_value MEM_DDRT_TMRD_CK_CYC {8} + set_component_parameter_value MEM_DDRT_TQH_CYC {0.38} + set_component_parameter_value MEM_DDRT_TQH_UI {0.76} + set_component_parameter_value MEM_DDRT_TQSH_CYC {0.38} + set_component_parameter_value MEM_DDRT_TRAS_NS {32.0} + set_component_parameter_value MEM_DDRT_TRCD_NS {15.0} + set_component_parameter_value MEM_DDRT_TREFI_US {7.8} + set_component_parameter_value MEM_DDRT_TRFC_DLR_NS {90.0} + set_component_parameter_value MEM_DDRT_TRFC_NS {260.0} + set_component_parameter_value MEM_DDRT_TRP_NS {15.0} + set_component_parameter_value MEM_DDRT_TRRD_DLR_CYC {4} + set_component_parameter_value MEM_DDRT_TRRD_L_CYC {6} + set_component_parameter_value MEM_DDRT_TRRD_S_CYC {4} + set_component_parameter_value MEM_DDRT_TWLH_CYC {0.13} + set_component_parameter_value MEM_DDRT_TWLH_PS {0.0} + set_component_parameter_value MEM_DDRT_TWLS_CYC {0.13} + set_component_parameter_value MEM_DDRT_TWLS_PS {0.0} + set_component_parameter_value MEM_DDRT_TWR_NS {15.0} + set_component_parameter_value MEM_DDRT_TWTR_L_CYC {9} + set_component_parameter_value MEM_DDRT_TWTR_S_CYC {3} + set_component_parameter_value MEM_DDRT_USER_READ_PREAMBLE {1} + set_component_parameter_value MEM_DDRT_USER_TCL_ADDED {0} + set_component_parameter_value MEM_DDRT_USER_VREFDQ_TRAINING_RANGE {DDRT_VREFDQ_TRAINING_RANGE_1} + set_component_parameter_value MEM_DDRT_USER_VREFDQ_TRAINING_VALUE {56.0} + set_component_parameter_value MEM_DDRT_USER_WRITE_PREAMBLE {1} + set_component_parameter_value MEM_DDRT_USER_WTCL_ADDED {6} + set_component_parameter_value MEM_DDRT_USE_DEFAULT_ODT {1} + set_component_parameter_value MEM_DDRT_VDIVW_TOTAL {136} + set_component_parameter_value MEM_DDRT_WRITE_CRC {0} + set_component_parameter_value MEM_DDRT_WRITE_DBI {0} + set_component_parameter_value MEM_DDRT_WTCL {18} + set_component_parameter_value MEM_DDRT_W_ODT0_1X1 {on} + set_component_parameter_value MEM_DDRT_W_ODT0_2X2 {on off} + set_component_parameter_value MEM_DDRT_W_ODT0_4X2 {off off on on} + set_component_parameter_value MEM_DDRT_W_ODT0_4X4 {on on off off} + set_component_parameter_value MEM_DDRT_W_ODT1_2X2 {off on} + set_component_parameter_value MEM_DDRT_W_ODT1_4X2 {on on off off} + set_component_parameter_value MEM_DDRT_W_ODT1_4X4 {off off on on} + set_component_parameter_value MEM_DDRT_W_ODT2_4X4 {off off on on} + set_component_parameter_value MEM_DDRT_W_ODT3_4X4 {on on off off} + set_component_parameter_value MEM_DDRT_W_ODTN_1X1 {Rank\ 0} + set_component_parameter_value MEM_DDRT_W_ODTN_2X2 {Rank\ 0 Rank\ 1} + set_component_parameter_value MEM_DDRT_W_ODTN_4X2 {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} + set_component_parameter_value MEM_DDRT_W_ODTN_4X4 {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} + set_component_parameter_value MEM_LPDDR3_BANK_ADDR_WIDTH {3} + set_component_parameter_value MEM_LPDDR3_BL {LPDDR3_BL_BL8} + set_component_parameter_value MEM_LPDDR3_CK_WIDTH {1} + set_component_parameter_value MEM_LPDDR3_COL_ADDR_WIDTH {10} + set_component_parameter_value MEM_LPDDR3_DATA_LATENCY {LPDDR3_DL_RL12_WL6} + set_component_parameter_value MEM_LPDDR3_DISCRETE_CS_WIDTH {1} + set_component_parameter_value MEM_LPDDR3_DM_EN {1} + set_component_parameter_value MEM_LPDDR3_DQODT {LPDDR3_DQODT_DISABLE} + set_component_parameter_value MEM_LPDDR3_DQ_WIDTH {32} + set_component_parameter_value MEM_LPDDR3_DRV_STR {LPDDR3_DRV_STR_40D_40U} + set_component_parameter_value MEM_LPDDR3_PDODT {LPDDR3_PDODT_DISABLED} + set_component_parameter_value MEM_LPDDR3_ROW_ADDR_WIDTH {15} + set_component_parameter_value MEM_LPDDR3_R_ODT0_1X1 {off} + set_component_parameter_value MEM_LPDDR3_R_ODT0_2X2 {off off} + set_component_parameter_value MEM_LPDDR3_R_ODT0_4X4 {off off off off} + set_component_parameter_value MEM_LPDDR3_R_ODT1_2X2 {off off} + set_component_parameter_value MEM_LPDDR3_R_ODT1_4X4 {off off off off} + set_component_parameter_value MEM_LPDDR3_R_ODT2_4X4 {off off off off} + set_component_parameter_value MEM_LPDDR3_R_ODT3_4X4 {off off off off} + set_component_parameter_value MEM_LPDDR3_R_ODTN_1X1 {Rank\ 0} + set_component_parameter_value MEM_LPDDR3_R_ODTN_2X2 {Rank\ 0 Rank\ 1} + set_component_parameter_value MEM_LPDDR3_R_ODTN_4X4 {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} + set_component_parameter_value MEM_LPDDR3_SPEEDBIN_ENUM {LPDDR3_SPEEDBIN_1600} + set_component_parameter_value MEM_LPDDR3_TDH_DC_MV {100} + set_component_parameter_value MEM_LPDDR3_TDH_PS {100} + set_component_parameter_value MEM_LPDDR3_TDQSCKDL {614} + set_component_parameter_value MEM_LPDDR3_TDQSQ_PS {135} + set_component_parameter_value MEM_LPDDR3_TDQSS_CYC {1.25} + set_component_parameter_value MEM_LPDDR3_TDSH_CYC {0.2} + set_component_parameter_value MEM_LPDDR3_TDSS_CYC {0.2} + set_component_parameter_value MEM_LPDDR3_TDS_AC_MV {150} + set_component_parameter_value MEM_LPDDR3_TDS_PS {75} + set_component_parameter_value MEM_LPDDR3_TFAW_NS {50.0} + set_component_parameter_value MEM_LPDDR3_TIH_DC_MV {100} + set_component_parameter_value MEM_LPDDR3_TIH_PS {100} + set_component_parameter_value MEM_LPDDR3_TINIT_US {500} + set_component_parameter_value MEM_LPDDR3_TIS_AC_MV {150} + set_component_parameter_value MEM_LPDDR3_TIS_PS {75} + set_component_parameter_value MEM_LPDDR3_TMRR_CK_CYC {4} + set_component_parameter_value MEM_LPDDR3_TMRW_CK_CYC {10} + set_component_parameter_value MEM_LPDDR3_TQH_CYC {0.38} + set_component_parameter_value MEM_LPDDR3_TQSH_CYC {0.38} + set_component_parameter_value MEM_LPDDR3_TRAS_NS {42.5} + set_component_parameter_value MEM_LPDDR3_TRCD_NS {18.0} + set_component_parameter_value MEM_LPDDR3_TREFI_US {3.9} + set_component_parameter_value MEM_LPDDR3_TRFC_NS {210.0} + set_component_parameter_value MEM_LPDDR3_TRP_NS {18.0} + set_component_parameter_value MEM_LPDDR3_TRRD_CYC {8} + set_component_parameter_value MEM_LPDDR3_TRTP_CYC {6} + set_component_parameter_value MEM_LPDDR3_TWLH_PS {175.0} + set_component_parameter_value MEM_LPDDR3_TWLS_PS {175.0} + set_component_parameter_value MEM_LPDDR3_TWR_NS {15.0} + set_component_parameter_value MEM_LPDDR3_TWTR_CYC {6} + set_component_parameter_value MEM_LPDDR3_USE_DEFAULT_ODT {1} + set_component_parameter_value MEM_LPDDR3_W_ODT0_1X1 {on} + set_component_parameter_value MEM_LPDDR3_W_ODT0_2X2 {on on} + set_component_parameter_value MEM_LPDDR3_W_ODT0_4X4 {on on on on} + set_component_parameter_value MEM_LPDDR3_W_ODT1_2X2 {off off} + set_component_parameter_value MEM_LPDDR3_W_ODT1_4X4 {off off off off} + set_component_parameter_value MEM_LPDDR3_W_ODT2_4X4 {off off off off} + set_component_parameter_value MEM_LPDDR3_W_ODT3_4X4 {off off off off} + set_component_parameter_value MEM_LPDDR3_W_ODTN_1X1 {Rank\ 0} + set_component_parameter_value MEM_LPDDR3_W_ODTN_2X2 {Rank\ 0 Rank\ 1} + set_component_parameter_value MEM_LPDDR3_W_ODTN_4X4 {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} + set_component_parameter_value MEM_QDR2_ADDR_WIDTH {19} + set_component_parameter_value MEM_QDR2_BL {4} + set_component_parameter_value MEM_QDR2_BWS_EN {1} + set_component_parameter_value MEM_QDR2_DATA_PER_DEVICE {36} + set_component_parameter_value MEM_QDR2_INTERNAL_JITTER_NS {0.08} + set_component_parameter_value MEM_QDR2_SPEEDBIN_ENUM {QDR2_SPEEDBIN_633} + set_component_parameter_value MEM_QDR2_TCCQO_NS {0.45} + set_component_parameter_value MEM_QDR2_TCQDOH_NS {-0.09} + set_component_parameter_value MEM_QDR2_TCQD_NS {0.09} + set_component_parameter_value MEM_QDR2_TCQH_NS {0.71} + set_component_parameter_value MEM_QDR2_THA_NS {0.18} + set_component_parameter_value MEM_QDR2_THD_NS {0.18} + set_component_parameter_value MEM_QDR2_TRL_CYC {2.5} + set_component_parameter_value MEM_QDR2_TSA_NS {0.23} + set_component_parameter_value MEM_QDR2_TSD_NS {0.23} + set_component_parameter_value MEM_QDR2_WIDTH_EXPANDED {0} + set_component_parameter_value MEM_QDR4_AC_ODT_MODE_ENUM {QDR4_ODT_25_PCT} + set_component_parameter_value MEM_QDR4_ADDR_INV_ENA {0} + set_component_parameter_value MEM_QDR4_ADDR_WIDTH {21} + set_component_parameter_value MEM_QDR4_CK_ODT_MODE_ENUM {QDR4_ODT_25_PCT} + set_component_parameter_value MEM_QDR4_DATA_INV_ENA {1} + set_component_parameter_value MEM_QDR4_DATA_ODT_MODE_ENUM {QDR4_ODT_25_PCT} + set_component_parameter_value MEM_QDR4_DQ_PER_PORT_PER_DEVICE {36} + set_component_parameter_value MEM_QDR4_MEM_TYPE_ENUM {MEM_XP} + set_component_parameter_value MEM_QDR4_PD_OUTPUT_DRIVE_MODE_ENUM {QDR4_OUTPUT_DRIVE_25_PCT} + set_component_parameter_value MEM_QDR4_PU_OUTPUT_DRIVE_MODE_ENUM {QDR4_OUTPUT_DRIVE_25_PCT} + set_component_parameter_value MEM_QDR4_SKIP_ODT_SWEEPING {1} + set_component_parameter_value MEM_QDR4_SPEEDBIN_ENUM {QDR4_SPEEDBIN_2133} + set_component_parameter_value MEM_QDR4_TASH_PS {170} + set_component_parameter_value MEM_QDR4_TCKDK_MAX_PS {150} + set_component_parameter_value MEM_QDR4_TCKDK_MIN_PS {-150} + set_component_parameter_value MEM_QDR4_TCKQK_MAX_PS {225} + set_component_parameter_value MEM_QDR4_TCSH_PS {170} + set_component_parameter_value MEM_QDR4_TISH_PS {150} + set_component_parameter_value MEM_QDR4_TQH_CYC {0.4} + set_component_parameter_value MEM_QDR4_TQKQ_MAX_PS {75} + set_component_parameter_value MEM_QDR4_USE_ADDR_PARITY {0} + set_component_parameter_value MEM_QDR4_WIDTH_EXPANDED {0} + set_component_parameter_value MEM_RLD2_ADDR_WIDTH {21} + set_component_parameter_value MEM_RLD2_BANK_ADDR_WIDTH {3} + set_component_parameter_value MEM_RLD2_BL {4} + set_component_parameter_value MEM_RLD2_CONFIG_ENUM {RLD2_CONFIG_TRC_8_TRL_8_TWL_9} + set_component_parameter_value MEM_RLD2_DM_EN {1} + set_component_parameter_value MEM_RLD2_DQ_PER_DEVICE {9} + set_component_parameter_value MEM_RLD2_DRIVE_IMPEDENCE_ENUM {RLD2_DRIVE_IMPEDENCE_INTERNAL_50} + set_component_parameter_value MEM_RLD2_ODT_MODE_ENUM {RLD2_ODT_ON} + set_component_parameter_value MEM_RLD2_REFRESH_INTERVAL_US {0.24} + set_component_parameter_value MEM_RLD2_SPEEDBIN_ENUM {RLD2_SPEEDBIN_18} + set_component_parameter_value MEM_RLD2_TAH_NS {0.3} + set_component_parameter_value MEM_RLD2_TAS_NS {0.3} + set_component_parameter_value MEM_RLD2_TCKDK_MAX_NS {0.3} + set_component_parameter_value MEM_RLD2_TCKDK_MIN_NS {-0.3} + set_component_parameter_value MEM_RLD2_TCKH_CYC {0.45} + set_component_parameter_value MEM_RLD2_TCKQK_MAX_NS {0.2} + set_component_parameter_value MEM_RLD2_TDH_NS {0.17} + set_component_parameter_value MEM_RLD2_TDS_NS {0.17} + set_component_parameter_value MEM_RLD2_TQKH_HCYC {0.9} + set_component_parameter_value MEM_RLD2_TQKQ_MAX_NS {0.12} + set_component_parameter_value MEM_RLD2_TQKQ_MIN_NS {-0.12} + set_component_parameter_value MEM_RLD2_WIDTH_EXPANDED {0} + set_component_parameter_value MEM_RLD3_ADDR_WIDTH {20} + set_component_parameter_value MEM_RLD3_AREF_PROTOCOL_ENUM {RLD3_AREF_BAC} + set_component_parameter_value MEM_RLD3_BANK_ADDR_WIDTH {4} + set_component_parameter_value MEM_RLD3_BL {2} + set_component_parameter_value MEM_RLD3_DATA_LATENCY_MODE_ENUM {RLD3_DL_RL16_WL17} + set_component_parameter_value MEM_RLD3_DEPTH_EXPANDED {0} + set_component_parameter_value MEM_RLD3_DM_EN {1} + set_component_parameter_value MEM_RLD3_DQ_PER_DEVICE {36} + set_component_parameter_value MEM_RLD3_ODT_MODE_ENUM {RLD3_ODT_40} + set_component_parameter_value MEM_RLD3_OUTPUT_DRIVE_MODE_ENUM {RLD3_OUTPUT_DRIVE_40} + set_component_parameter_value MEM_RLD3_SPEEDBIN_ENUM {RLD3_SPEEDBIN_093E} + set_component_parameter_value MEM_RLD3_TCKDK_MAX_CYC {0.27} + set_component_parameter_value MEM_RLD3_TCKDK_MIN_CYC {-0.27} + set_component_parameter_value MEM_RLD3_TCKQK_MAX_PS {135} + set_component_parameter_value MEM_RLD3_TDH_DC_MV {100} + set_component_parameter_value MEM_RLD3_TDH_PS {5} + set_component_parameter_value MEM_RLD3_TDS_AC_MV {150} + set_component_parameter_value MEM_RLD3_TDS_PS {-30} + set_component_parameter_value MEM_RLD3_TIH_DC_MV {100} + set_component_parameter_value MEM_RLD3_TIH_PS {65} + set_component_parameter_value MEM_RLD3_TIS_AC_MV {150} + set_component_parameter_value MEM_RLD3_TIS_PS {85} + set_component_parameter_value MEM_RLD3_TQH_CYC {0.38} + set_component_parameter_value MEM_RLD3_TQKQ_MAX_PS {75} + set_component_parameter_value MEM_RLD3_T_RC_MODE_ENUM {RLD3_TRC_9} + set_component_parameter_value MEM_RLD3_WIDTH_EXPANDED {0} + set_component_parameter_value MEM_RLD3_WRITE_PROTOCOL_ENUM {RLD3_WRITE_1BANK} + set_component_parameter_value NUM_IPS {1} + set_component_parameter_value PHY_DDR3_CAL_ADDR0 {0} + set_component_parameter_value PHY_DDR3_CAL_ADDR1 {8} + set_component_parameter_value PHY_DDR3_CAL_ENABLE_NON_DES {0} + set_component_parameter_value PHY_DDR3_CONFIG_ENUM {CONFIG_PHY_AND_HARD_CTRL} + set_component_parameter_value PHY_DDR3_CORE_CLKS_SHARING_ENUM {CORE_CLKS_SHARING_DISABLED} + set_component_parameter_value PHY_DDR3_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT {0} + set_component_parameter_value PHY_DDR3_DEFAULT_IO {1} + set_component_parameter_value PHY_DDR3_DEFAULT_REF_CLK_FREQ {1} + set_component_parameter_value PHY_DDR3_HPS_ENABLE_EARLY_RELEASE {0} + set_component_parameter_value PHY_DDR3_IO_VOLTAGE {1.5} + set_component_parameter_value PHY_DDR3_MEM_CLK_FREQ_MHZ {1066.667} + set_component_parameter_value PHY_DDR3_MIMIC_HPS_EMIF {0} + set_component_parameter_value PHY_DDR3_RATE_ENUM {RATE_QUARTER} + set_component_parameter_value PHY_DDR3_REF_CLK_JITTER_PS {10.0} + set_component_parameter_value PHY_DDR3_USER_AC_DEEMPHASIS_ENUM {unset} + set_component_parameter_value PHY_DDR3_USER_AC_IO_STD_ENUM {unset} + set_component_parameter_value PHY_DDR3_USER_AC_MODE_ENUM {unset} + set_component_parameter_value PHY_DDR3_USER_AC_SLEW_RATE_ENUM {unset} + set_component_parameter_value PHY_DDR3_USER_AUTO_STARTING_VREFIN_EN {1} + set_component_parameter_value PHY_DDR3_USER_CK_DEEMPHASIS_ENUM {unset} + set_component_parameter_value PHY_DDR3_USER_CK_IO_STD_ENUM {unset} + set_component_parameter_value PHY_DDR3_USER_CK_MODE_ENUM {unset} + set_component_parameter_value PHY_DDR3_USER_CK_SLEW_RATE_ENUM {unset} + set_component_parameter_value PHY_DDR3_USER_DATA_IN_MODE_ENUM {unset} + set_component_parameter_value PHY_DDR3_USER_DATA_IO_STD_ENUM {unset} + set_component_parameter_value PHY_DDR3_USER_DATA_OUT_DEEMPHASIS_ENUM {unset} + set_component_parameter_value PHY_DDR3_USER_DATA_OUT_MODE_ENUM {unset} + set_component_parameter_value PHY_DDR3_USER_DATA_OUT_SLEW_RATE_ENUM {unset} + set_component_parameter_value PHY_DDR3_USER_DLL_CORE_UPDN_EN {1} + set_component_parameter_value PHY_DDR3_USER_PERIODIC_OCT_RECAL_ENUM {PERIODIC_OCT_RECAL_AUTO} + set_component_parameter_value PHY_DDR3_USER_PING_PONG_EN {0} + set_component_parameter_value PHY_DDR3_USER_PLL_REF_CLK_IO_STD_ENUM {unset} + set_component_parameter_value PHY_DDR3_USER_REF_CLK_FREQ_MHZ {-1.0} + set_component_parameter_value PHY_DDR3_USER_RZQ_IO_STD_ENUM {unset} + set_component_parameter_value PHY_DDR3_USER_STARTING_VREFIN {70.0} + set_component_parameter_value PHY_DDR4_ALLOW_72_DQ_WIDTH {0} + set_component_parameter_value PHY_DDR4_CONFIG_ENUM {CONFIG_PHY_AND_HARD_CTRL} + set_component_parameter_value PHY_DDR4_CORE_CLKS_SHARING_ENUM {CORE_CLKS_SHARING_DISABLED} + set_component_parameter_value PHY_DDR4_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT {0} + set_component_parameter_value PHY_DDR4_DEFAULT_IO {0} + set_component_parameter_value PHY_DDR4_DEFAULT_REF_CLK_FREQ {0} + set_component_parameter_value PHY_DDR4_HPS_ENABLE_EARLY_RELEASE {0} + set_component_parameter_value PHY_DDR4_IO_VOLTAGE {1.2} + set_component_parameter_value PHY_DDR4_MEM_CLK_FREQ_MHZ {1200.0} + set_component_parameter_value PHY_DDR4_MIMIC_HPS_EMIF {0} + set_component_parameter_value PHY_DDR4_RATE_ENUM {RATE_QUARTER} + set_component_parameter_value PHY_DDR4_REF_CLK_JITTER_PS {10.0} + set_component_parameter_value PHY_DDR4_USER_AC_DEEMPHASIS_ENUM {unset} + set_component_parameter_value PHY_DDR4_USER_AC_IO_STD_ENUM {IO_STD_SSTL_12} + set_component_parameter_value PHY_DDR4_USER_AC_MODE_ENUM {OUT_OCT_40_CAL} + set_component_parameter_value PHY_DDR4_USER_AC_SLEW_RATE_ENUM {unset} + set_component_parameter_value PHY_DDR4_USER_AUTO_STARTING_VREFIN_EN {1} + set_component_parameter_value PHY_DDR4_USER_CK_DEEMPHASIS_ENUM {unset} + set_component_parameter_value PHY_DDR4_USER_CK_IO_STD_ENUM {IO_STD_SSTL_12} + set_component_parameter_value PHY_DDR4_USER_CK_MODE_ENUM {OUT_OCT_40_CAL} + set_component_parameter_value PHY_DDR4_USER_CK_SLEW_RATE_ENUM {unset} + set_component_parameter_value PHY_DDR4_USER_CLAMSHELL_EN {0} + set_component_parameter_value PHY_DDR4_USER_DATA_IN_MODE_ENUM {IN_OCT_60_CAL} + set_component_parameter_value PHY_DDR4_USER_DATA_IO_STD_ENUM {IO_STD_POD_12} + set_component_parameter_value PHY_DDR4_USER_DATA_OUT_DEEMPHASIS_ENUM {unset} + set_component_parameter_value PHY_DDR4_USER_DATA_OUT_MODE_ENUM {OUT_OCT_40_CAL} + set_component_parameter_value PHY_DDR4_USER_DATA_OUT_SLEW_RATE_ENUM {unset} + set_component_parameter_value PHY_DDR4_USER_DLL_CORE_UPDN_EN {1} + set_component_parameter_value PHY_DDR4_USER_PERIODIC_OCT_RECAL_ENUM {PERIODIC_OCT_RECAL_AUTO} + set_component_parameter_value PHY_DDR4_USER_PING_PONG_EN {0} + set_component_parameter_value PHY_DDR4_USER_PLL_REF_CLK_IO_STD_ENUM {IO_STD_TRUE_DIFF_SIGNALING} + set_component_parameter_value PHY_DDR4_USER_REF_CLK_FREQ_MHZ {33.333} + set_component_parameter_value PHY_DDR4_USER_RZQ_IO_STD_ENUM {IO_STD_CMOS_12} + set_component_parameter_value PHY_DDR4_USER_STARTING_VREFIN {70.0} + set_component_parameter_value PHY_DDRT_2CH_EN {0} + set_component_parameter_value PHY_DDRT_CONFIG_ENUM {CONFIG_PHY_AND_SOFT_CTRL} + set_component_parameter_value PHY_DDRT_CORE_CLKS_SHARING_ENUM {CORE_CLKS_SHARING_DISABLED} + set_component_parameter_value PHY_DDRT_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT {0} + set_component_parameter_value PHY_DDRT_DEFAULT_IO {1} + set_component_parameter_value PHY_DDRT_DEFAULT_REF_CLK_FREQ {1} + set_component_parameter_value PHY_DDRT_EXPORT_CLK_STP_IF {0} + set_component_parameter_value PHY_DDRT_HPS_ENABLE_EARLY_RELEASE {0} + set_component_parameter_value PHY_DDRT_I2C_USE_SMC {0} + set_component_parameter_value PHY_DDRT_IC_EN {1} + set_component_parameter_value PHY_DDRT_IO_VOLTAGE {1.2} + set_component_parameter_value PHY_DDRT_MEM_CLK_FREQ_MHZ {1200.0} + set_component_parameter_value PHY_DDRT_MIMIC_HPS_EMIF {0} + set_component_parameter_value PHY_DDRT_RATE_ENUM {RATE_QUARTER} + set_component_parameter_value PHY_DDRT_REF_CLK_JITTER_PS {10.0} + set_component_parameter_value PHY_DDRT_USER_AC_DEEMPHASIS_ENUM {unset} + set_component_parameter_value PHY_DDRT_USER_AC_IN_MODE_ENUM {unset} + set_component_parameter_value PHY_DDRT_USER_AC_IO_STD_ENUM {unset} + set_component_parameter_value PHY_DDRT_USER_AC_MODE_ENUM {unset} + set_component_parameter_value PHY_DDRT_USER_AC_SLEW_RATE_ENUM {unset} + set_component_parameter_value PHY_DDRT_USER_AUTO_STARTING_VREFIN_EN {1} + set_component_parameter_value PHY_DDRT_USER_CK_DEEMPHASIS_ENUM {unset} + set_component_parameter_value PHY_DDRT_USER_CK_IO_STD_ENUM {unset} + set_component_parameter_value PHY_DDRT_USER_CK_MODE_ENUM {unset} + set_component_parameter_value PHY_DDRT_USER_CK_SLEW_RATE_ENUM {unset} + set_component_parameter_value PHY_DDRT_USER_DATA_IN_MODE_ENUM {unset} + set_component_parameter_value PHY_DDRT_USER_DATA_IO_STD_ENUM {unset} + set_component_parameter_value PHY_DDRT_USER_DATA_OUT_DEEMPHASIS_ENUM {unset} + set_component_parameter_value PHY_DDRT_USER_DATA_OUT_MODE_ENUM {unset} + set_component_parameter_value PHY_DDRT_USER_DATA_OUT_SLEW_RATE_ENUM {unset} + set_component_parameter_value PHY_DDRT_USER_DLL_CORE_UPDN_EN {0} + set_component_parameter_value PHY_DDRT_USER_PERIODIC_OCT_RECAL_ENUM {PERIODIC_OCT_RECAL_AUTO} + set_component_parameter_value PHY_DDRT_USER_PING_PONG_EN {0} + set_component_parameter_value PHY_DDRT_USER_PLL_REF_CLK_IO_STD_ENUM {unset} + set_component_parameter_value PHY_DDRT_USER_REF_CLK_FREQ_MHZ {-1.0} + set_component_parameter_value PHY_DDRT_USER_RZQ_IO_STD_ENUM {unset} + set_component_parameter_value PHY_DDRT_USER_STARTING_VREFIN {70.0} + set_component_parameter_value PHY_DDRT_USE_OLD_SMBUS_MULTICOL {0} + set_component_parameter_value PHY_LPDDR3_CONFIG_ENUM {CONFIG_PHY_AND_HARD_CTRL} + set_component_parameter_value PHY_LPDDR3_CORE_CLKS_SHARING_ENUM {CORE_CLKS_SHARING_DISABLED} + set_component_parameter_value PHY_LPDDR3_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT {0} + set_component_parameter_value PHY_LPDDR3_DEFAULT_IO {1} + set_component_parameter_value PHY_LPDDR3_DEFAULT_REF_CLK_FREQ {1} + set_component_parameter_value PHY_LPDDR3_HPS_ENABLE_EARLY_RELEASE {0} + set_component_parameter_value PHY_LPDDR3_IO_VOLTAGE {1.2} + set_component_parameter_value PHY_LPDDR3_MEM_CLK_FREQ_MHZ {800.0} + set_component_parameter_value PHY_LPDDR3_MIMIC_HPS_EMIF {0} + set_component_parameter_value PHY_LPDDR3_RATE_ENUM {RATE_QUARTER} + set_component_parameter_value PHY_LPDDR3_REF_CLK_JITTER_PS {10.0} + set_component_parameter_value PHY_LPDDR3_USER_AC_DEEMPHASIS_ENUM {unset} + set_component_parameter_value PHY_LPDDR3_USER_AC_IO_STD_ENUM {unset} + set_component_parameter_value PHY_LPDDR3_USER_AC_MODE_ENUM {unset} + set_component_parameter_value PHY_LPDDR3_USER_AC_SLEW_RATE_ENUM {unset} + set_component_parameter_value PHY_LPDDR3_USER_AUTO_STARTING_VREFIN_EN {1} + set_component_parameter_value PHY_LPDDR3_USER_CK_DEEMPHASIS_ENUM {unset} + set_component_parameter_value PHY_LPDDR3_USER_CK_IO_STD_ENUM {unset} + set_component_parameter_value PHY_LPDDR3_USER_CK_MODE_ENUM {unset} + set_component_parameter_value PHY_LPDDR3_USER_CK_SLEW_RATE_ENUM {unset} + set_component_parameter_value PHY_LPDDR3_USER_DATA_IN_MODE_ENUM {unset} + set_component_parameter_value PHY_LPDDR3_USER_DATA_IO_STD_ENUM {unset} + set_component_parameter_value PHY_LPDDR3_USER_DATA_OUT_DEEMPHASIS_ENUM {unset} + set_component_parameter_value PHY_LPDDR3_USER_DATA_OUT_MODE_ENUM {unset} + set_component_parameter_value PHY_LPDDR3_USER_DATA_OUT_SLEW_RATE_ENUM {unset} + set_component_parameter_value PHY_LPDDR3_USER_DLL_CORE_UPDN_EN {0} + set_component_parameter_value PHY_LPDDR3_USER_PERIODIC_OCT_RECAL_ENUM {PERIODIC_OCT_RECAL_AUTO} + set_component_parameter_value PHY_LPDDR3_USER_PING_PONG_EN {0} + set_component_parameter_value PHY_LPDDR3_USER_PLL_REF_CLK_IO_STD_ENUM {unset} + set_component_parameter_value PHY_LPDDR3_USER_REF_CLK_FREQ_MHZ {-1.0} + set_component_parameter_value PHY_LPDDR3_USER_RZQ_IO_STD_ENUM {unset} + set_component_parameter_value PHY_LPDDR3_USER_STARTING_VREFIN {70.0} + set_component_parameter_value PHY_QDR2_CONFIG_ENUM {CONFIG_PHY_AND_SOFT_CTRL} + set_component_parameter_value PHY_QDR2_CORE_CLKS_SHARING_ENUM {CORE_CLKS_SHARING_DISABLED} + set_component_parameter_value PHY_QDR2_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT {0} + set_component_parameter_value PHY_QDR2_DEFAULT_IO {1} + set_component_parameter_value PHY_QDR2_DEFAULT_REF_CLK_FREQ {1} + set_component_parameter_value PHY_QDR2_HPS_ENABLE_EARLY_RELEASE {0} + set_component_parameter_value PHY_QDR2_IO_VOLTAGE {1.5} + set_component_parameter_value PHY_QDR2_MEM_CLK_FREQ_MHZ {633.333} + set_component_parameter_value PHY_QDR2_MIMIC_HPS_EMIF {0} + set_component_parameter_value PHY_QDR2_RATE_ENUM {RATE_HALF} + set_component_parameter_value PHY_QDR2_REF_CLK_JITTER_PS {10.0} + set_component_parameter_value PHY_QDR2_USER_AC_DEEMPHASIS_ENUM {unset} + set_component_parameter_value PHY_QDR2_USER_AC_IO_STD_ENUM {unset} + set_component_parameter_value PHY_QDR2_USER_AC_MODE_ENUM {unset} + set_component_parameter_value PHY_QDR2_USER_AC_SLEW_RATE_ENUM {unset} + set_component_parameter_value PHY_QDR2_USER_AUTO_STARTING_VREFIN_EN {1} + set_component_parameter_value PHY_QDR2_USER_CK_DEEMPHASIS_ENUM {unset} + set_component_parameter_value PHY_QDR2_USER_CK_IO_STD_ENUM {unset} + set_component_parameter_value PHY_QDR2_USER_CK_MODE_ENUM {unset} + set_component_parameter_value PHY_QDR2_USER_CK_SLEW_RATE_ENUM {unset} + set_component_parameter_value PHY_QDR2_USER_DATA_IN_MODE_ENUM {unset} + set_component_parameter_value PHY_QDR2_USER_DATA_IO_STD_ENUM {unset} + set_component_parameter_value PHY_QDR2_USER_DATA_OUT_DEEMPHASIS_ENUM {unset} + set_component_parameter_value PHY_QDR2_USER_DATA_OUT_MODE_ENUM {unset} + set_component_parameter_value PHY_QDR2_USER_DATA_OUT_SLEW_RATE_ENUM {unset} + set_component_parameter_value PHY_QDR2_USER_DLL_CORE_UPDN_EN {0} + set_component_parameter_value PHY_QDR2_USER_PERIODIC_OCT_RECAL_ENUM {PERIODIC_OCT_RECAL_AUTO} + set_component_parameter_value PHY_QDR2_USER_PING_PONG_EN {0} + set_component_parameter_value PHY_QDR2_USER_PLL_REF_CLK_IO_STD_ENUM {unset} + set_component_parameter_value PHY_QDR2_USER_REF_CLK_FREQ_MHZ {-1.0} + set_component_parameter_value PHY_QDR2_USER_RZQ_IO_STD_ENUM {unset} + set_component_parameter_value PHY_QDR2_USER_STARTING_VREFIN {70.0} + set_component_parameter_value PHY_QDR4_CONFIG_ENUM {CONFIG_PHY_AND_SOFT_CTRL} + set_component_parameter_value PHY_QDR4_CORE_CLKS_SHARING_ENUM {CORE_CLKS_SHARING_DISABLED} + set_component_parameter_value PHY_QDR4_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT {0} + set_component_parameter_value PHY_QDR4_DEFAULT_IO {1} + set_component_parameter_value PHY_QDR4_DEFAULT_REF_CLK_FREQ {1} + set_component_parameter_value PHY_QDR4_HPS_ENABLE_EARLY_RELEASE {0} + set_component_parameter_value PHY_QDR4_IO_VOLTAGE {1.2} + set_component_parameter_value PHY_QDR4_MEM_CLK_FREQ_MHZ {1066.667} + set_component_parameter_value PHY_QDR4_MIMIC_HPS_EMIF {0} + set_component_parameter_value PHY_QDR4_RATE_ENUM {RATE_QUARTER} + set_component_parameter_value PHY_QDR4_REF_CLK_JITTER_PS {10.0} + set_component_parameter_value PHY_QDR4_USER_AC_DEEMPHASIS_ENUM {unset} + set_component_parameter_value PHY_QDR4_USER_AC_IO_STD_ENUM {unset} + set_component_parameter_value PHY_QDR4_USER_AC_MODE_ENUM {unset} + set_component_parameter_value PHY_QDR4_USER_AC_SLEW_RATE_ENUM {unset} + set_component_parameter_value PHY_QDR4_USER_AUTO_STARTING_VREFIN_EN {1} + set_component_parameter_value PHY_QDR4_USER_CK_DEEMPHASIS_ENUM {unset} + set_component_parameter_value PHY_QDR4_USER_CK_IO_STD_ENUM {unset} + set_component_parameter_value PHY_QDR4_USER_CK_MODE_ENUM {unset} + set_component_parameter_value PHY_QDR4_USER_CK_SLEW_RATE_ENUM {unset} + set_component_parameter_value PHY_QDR4_USER_DATA_IN_MODE_ENUM {unset} + set_component_parameter_value PHY_QDR4_USER_DATA_IO_STD_ENUM {unset} + set_component_parameter_value PHY_QDR4_USER_DATA_OUT_DEEMPHASIS_ENUM {unset} + set_component_parameter_value PHY_QDR4_USER_DATA_OUT_MODE_ENUM {unset} + set_component_parameter_value PHY_QDR4_USER_DATA_OUT_SLEW_RATE_ENUM {unset} + set_component_parameter_value PHY_QDR4_USER_DLL_CORE_UPDN_EN {1} + set_component_parameter_value PHY_QDR4_USER_PERIODIC_OCT_RECAL_ENUM {PERIODIC_OCT_RECAL_AUTO} + set_component_parameter_value PHY_QDR4_USER_PING_PONG_EN {0} + set_component_parameter_value PHY_QDR4_USER_PLL_REF_CLK_IO_STD_ENUM {unset} + set_component_parameter_value PHY_QDR4_USER_REF_CLK_FREQ_MHZ {-1.0} + set_component_parameter_value PHY_QDR4_USER_RZQ_IO_STD_ENUM {unset} + set_component_parameter_value PHY_QDR4_USER_STARTING_VREFIN {70.0} + set_component_parameter_value PHY_RLD2_CONFIG_ENUM {CONFIG_PHY_AND_SOFT_CTRL} + set_component_parameter_value PHY_RLD2_CORE_CLKS_SHARING_ENUM {CORE_CLKS_SHARING_DISABLED} + set_component_parameter_value PHY_RLD2_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT {0} + set_component_parameter_value PHY_RLD2_DEFAULT_IO {1} + set_component_parameter_value PHY_RLD2_DEFAULT_REF_CLK_FREQ {1} + set_component_parameter_value PHY_RLD2_HPS_ENABLE_EARLY_RELEASE {0} + set_component_parameter_value PHY_RLD2_IO_VOLTAGE {1.8} + set_component_parameter_value PHY_RLD2_MEM_CLK_FREQ_MHZ {533.333} + set_component_parameter_value PHY_RLD2_MIMIC_HPS_EMIF {0} + set_component_parameter_value PHY_RLD2_RATE_ENUM {RATE_HALF} + set_component_parameter_value PHY_RLD2_REF_CLK_JITTER_PS {10.0} + set_component_parameter_value PHY_RLD2_USER_AC_DEEMPHASIS_ENUM {unset} + set_component_parameter_value PHY_RLD2_USER_AC_IO_STD_ENUM {unset} + set_component_parameter_value PHY_RLD2_USER_AC_MODE_ENUM {unset} + set_component_parameter_value PHY_RLD2_USER_AC_SLEW_RATE_ENUM {unset} + set_component_parameter_value PHY_RLD2_USER_AUTO_STARTING_VREFIN_EN {1} + set_component_parameter_value PHY_RLD2_USER_CK_DEEMPHASIS_ENUM {unset} + set_component_parameter_value PHY_RLD2_USER_CK_IO_STD_ENUM {unset} + set_component_parameter_value PHY_RLD2_USER_CK_MODE_ENUM {unset} + set_component_parameter_value PHY_RLD2_USER_CK_SLEW_RATE_ENUM {unset} + set_component_parameter_value PHY_RLD2_USER_DATA_IN_MODE_ENUM {unset} + set_component_parameter_value PHY_RLD2_USER_DATA_IO_STD_ENUM {unset} + set_component_parameter_value PHY_RLD2_USER_DATA_OUT_DEEMPHASIS_ENUM {unset} + set_component_parameter_value PHY_RLD2_USER_DATA_OUT_MODE_ENUM {unset} + set_component_parameter_value PHY_RLD2_USER_DATA_OUT_SLEW_RATE_ENUM {unset} + set_component_parameter_value PHY_RLD2_USER_DLL_CORE_UPDN_EN {0} + set_component_parameter_value PHY_RLD2_USER_PERIODIC_OCT_RECAL_ENUM {PERIODIC_OCT_RECAL_AUTO} + set_component_parameter_value PHY_RLD2_USER_PING_PONG_EN {0} + set_component_parameter_value PHY_RLD2_USER_PLL_REF_CLK_IO_STD_ENUM {unset} + set_component_parameter_value PHY_RLD2_USER_REF_CLK_FREQ_MHZ {-1.0} + set_component_parameter_value PHY_RLD2_USER_RZQ_IO_STD_ENUM {unset} + set_component_parameter_value PHY_RLD2_USER_STARTING_VREFIN {70.0} + set_component_parameter_value PHY_RLD3_CONFIG_ENUM {CONFIG_PHY_ONLY} + set_component_parameter_value PHY_RLD3_CORE_CLKS_SHARING_ENUM {CORE_CLKS_SHARING_DISABLED} + set_component_parameter_value PHY_RLD3_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT {0} + set_component_parameter_value PHY_RLD3_DEFAULT_IO {1} + set_component_parameter_value PHY_RLD3_DEFAULT_REF_CLK_FREQ {1} + set_component_parameter_value PHY_RLD3_HPS_ENABLE_EARLY_RELEASE {0} + set_component_parameter_value PHY_RLD3_IO_VOLTAGE {1.2} + set_component_parameter_value PHY_RLD3_MEM_CLK_FREQ_MHZ {1066.667} + set_component_parameter_value PHY_RLD3_MIMIC_HPS_EMIF {0} + set_component_parameter_value PHY_RLD3_RATE_ENUM {RATE_QUARTER} + set_component_parameter_value PHY_RLD3_REF_CLK_JITTER_PS {10.0} + set_component_parameter_value PHY_RLD3_USER_AC_DEEMPHASIS_ENUM {unset} + set_component_parameter_value PHY_RLD3_USER_AC_IO_STD_ENUM {unset} + set_component_parameter_value PHY_RLD3_USER_AC_MODE_ENUM {unset} + set_component_parameter_value PHY_RLD3_USER_AC_SLEW_RATE_ENUM {unset} + set_component_parameter_value PHY_RLD3_USER_AUTO_STARTING_VREFIN_EN {1} + set_component_parameter_value PHY_RLD3_USER_CK_DEEMPHASIS_ENUM {unset} + set_component_parameter_value PHY_RLD3_USER_CK_IO_STD_ENUM {unset} + set_component_parameter_value PHY_RLD3_USER_CK_MODE_ENUM {unset} + set_component_parameter_value PHY_RLD3_USER_CK_SLEW_RATE_ENUM {unset} + set_component_parameter_value PHY_RLD3_USER_DATA_IN_MODE_ENUM {unset} + set_component_parameter_value PHY_RLD3_USER_DATA_IO_STD_ENUM {unset} + set_component_parameter_value PHY_RLD3_USER_DATA_OUT_DEEMPHASIS_ENUM {unset} + set_component_parameter_value PHY_RLD3_USER_DATA_OUT_MODE_ENUM {unset} + set_component_parameter_value PHY_RLD3_USER_DATA_OUT_SLEW_RATE_ENUM {unset} + set_component_parameter_value PHY_RLD3_USER_DLL_CORE_UPDN_EN {0} + set_component_parameter_value PHY_RLD3_USER_PERIODIC_OCT_RECAL_ENUM {PERIODIC_OCT_RECAL_AUTO} + set_component_parameter_value PHY_RLD3_USER_PING_PONG_EN {0} + set_component_parameter_value PHY_RLD3_USER_PLL_REF_CLK_IO_STD_ENUM {unset} + set_component_parameter_value PHY_RLD3_USER_REF_CLK_FREQ_MHZ {-1.0} + set_component_parameter_value PHY_RLD3_USER_RZQ_IO_STD_ENUM {unset} + set_component_parameter_value PHY_RLD3_USER_STARTING_VREFIN {70.0} + set_component_parameter_value PLL_ADD_EXTRA_CLKS {0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_0 {50.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_1 {50.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_2 {50.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_3 {50.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_4 {50.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_5 {50.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_6 {50.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_7 {50.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_8 {50.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_0 {50.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_1 {50.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_2 {50.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_3 {50.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_4 {50.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_5 {50.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_6 {50.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_7 {50.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_8 {50.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_0 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_1 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_2 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_3 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_4 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_5 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_6 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_7 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_8 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_0 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_1 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_2 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_3 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_4 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_5 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_6 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_7 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_8 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_0 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_1 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_2 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_3 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_4 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_5 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_6 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_7 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_8 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_0 {50.0} + set_component_parameter_value PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_1 {50.0} + set_component_parameter_value PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_2 {50.0} + set_component_parameter_value PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_3 {50.0} + set_component_parameter_value PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_4 {50.0} + set_component_parameter_value PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_5 {50.0} + set_component_parameter_value PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_6 {50.0} + set_component_parameter_value PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_7 {50.0} + set_component_parameter_value PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_8 {50.0} + set_component_parameter_value PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_0 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_1 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_2 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_3 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_4 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_5 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_6 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_7 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_8 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_DESIRED_PHASE_GUI_0 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_DESIRED_PHASE_GUI_1 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_DESIRED_PHASE_GUI_2 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_DESIRED_PHASE_GUI_3 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_DESIRED_PHASE_GUI_4 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_DESIRED_PHASE_GUI_5 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_DESIRED_PHASE_GUI_6 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_DESIRED_PHASE_GUI_7 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_DESIRED_PHASE_GUI_8 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_0 {ps} + set_component_parameter_value PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_1 {ps} + set_component_parameter_value PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_2 {ps} + set_component_parameter_value PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_3 {ps} + set_component_parameter_value PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_4 {ps} + set_component_parameter_value PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_5 {ps} + set_component_parameter_value PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_6 {ps} + set_component_parameter_value PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_7 {ps} + set_component_parameter_value PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_8 {ps} + set_component_parameter_value PLL_USER_NUM_OF_EXTRA_CLKS {0} + set_component_parameter_value PROTOCOL_ENUM {PROTOCOL_DDR4} + set_component_parameter_value SHORT_QSYS_INTERFACE_NAMES {1} + set_component_project_property HIDE_FROM_IP_CATALOG {false} + save_component + load_instantiation emif_fm_0 + remove_instantiation_interfaces_and_ports + add_instantiation_interface local_reset_req conduit INPUT + set_instantiation_interface_parameter_value local_reset_req associatedClock {} + set_instantiation_interface_parameter_value local_reset_req associatedReset {} + set_instantiation_interface_parameter_value local_reset_req prSafe {false} + add_instantiation_interface_port local_reset_req local_reset_req local_reset_req 1 STD_LOGIC Input + add_instantiation_interface local_reset_status conduit INPUT + set_instantiation_interface_parameter_value local_reset_status associatedClock {} + set_instantiation_interface_parameter_value local_reset_status associatedReset {} + set_instantiation_interface_parameter_value local_reset_status prSafe {false} + add_instantiation_interface_port local_reset_status local_reset_done local_reset_done 1 STD_LOGIC Output + add_instantiation_interface pll_ref_clk clock INPUT + set_instantiation_interface_parameter_value pll_ref_clk clockRate {0} + set_instantiation_interface_parameter_value pll_ref_clk externallyDriven {false} + set_instantiation_interface_parameter_value pll_ref_clk ptfSchematicName {} + add_instantiation_interface_port pll_ref_clk pll_ref_clk clk 1 STD_LOGIC Input + add_instantiation_interface pll_locked conduit INPUT + set_instantiation_interface_parameter_value pll_locked associatedClock {} + set_instantiation_interface_parameter_value pll_locked associatedReset {} + set_instantiation_interface_parameter_value pll_locked prSafe {false} + add_instantiation_interface_port pll_locked pll_locked pll_locked 1 STD_LOGIC Output + add_instantiation_interface oct conduit INPUT + set_instantiation_interface_parameter_value oct associatedClock {} + set_instantiation_interface_parameter_value oct associatedReset {} + set_instantiation_interface_parameter_value oct prSafe {false} + add_instantiation_interface_port oct oct_rzqin oct_rzqin 1 STD_LOGIC Input + add_instantiation_interface mem conduit INPUT + set_instantiation_interface_parameter_value mem associatedClock {} + set_instantiation_interface_parameter_value mem associatedReset {} + set_instantiation_interface_parameter_value mem prSafe {false} + add_instantiation_interface_port mem mem_ck mem_ck 1 STD_LOGIC_VECTOR Output + add_instantiation_interface_port mem mem_ck_n mem_ck_n 1 STD_LOGIC_VECTOR Output + add_instantiation_interface_port mem mem_a mem_a 17 STD_LOGIC_VECTOR Output + add_instantiation_interface_port mem mem_act_n mem_act_n 1 STD_LOGIC_VECTOR Output + add_instantiation_interface_port mem mem_ba mem_ba 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port mem mem_bg mem_bg 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port mem mem_cke mem_cke 1 STD_LOGIC_VECTOR Output + add_instantiation_interface_port mem mem_cs_n mem_cs_n 1 STD_LOGIC_VECTOR Output + add_instantiation_interface_port mem mem_odt mem_odt 1 STD_LOGIC_VECTOR Output + add_instantiation_interface_port mem mem_reset_n mem_reset_n 1 STD_LOGIC_VECTOR Output + add_instantiation_interface_port mem mem_par mem_par 1 STD_LOGIC_VECTOR Output + add_instantiation_interface_port mem mem_alert_n mem_alert_n 1 STD_LOGIC_VECTOR Input + add_instantiation_interface_port mem mem_dqs mem_dqs 9 STD_LOGIC_VECTOR Bidir + add_instantiation_interface_port mem mem_dqs_n mem_dqs_n 9 STD_LOGIC_VECTOR Bidir + add_instantiation_interface_port mem mem_dq mem_dq 72 STD_LOGIC_VECTOR Bidir + add_instantiation_interface_port mem mem_dbi_n mem_dbi_n 9 STD_LOGIC_VECTOR Bidir + add_instantiation_interface status conduit INPUT + set_instantiation_interface_parameter_value status associatedClock {} + set_instantiation_interface_parameter_value status associatedReset {} + set_instantiation_interface_parameter_value status prSafe {false} + add_instantiation_interface_port status local_cal_success local_cal_success 1 STD_LOGIC Output + add_instantiation_interface_port status local_cal_fail local_cal_fail 1 STD_LOGIC Output + add_instantiation_interface emif_calbus conduit INPUT + set_instantiation_interface_parameter_value emif_calbus associatedClock {emif_calbus_clk} + set_instantiation_interface_parameter_value emif_calbus associatedReset {} + set_instantiation_interface_parameter_value emif_calbus prSafe {false} + add_instantiation_interface_port emif_calbus calbus_read calbus_read 1 STD_LOGIC Input + add_instantiation_interface_port emif_calbus calbus_write calbus_write 1 STD_LOGIC Input + add_instantiation_interface_port emif_calbus calbus_address calbus_address 20 STD_LOGIC_VECTOR Input + add_instantiation_interface_port emif_calbus calbus_wdata calbus_wdata 32 STD_LOGIC_VECTOR Input + add_instantiation_interface_port emif_calbus calbus_rdata calbus_rdata 32 STD_LOGIC_VECTOR Output + add_instantiation_interface_port emif_calbus calbus_seq_param_tbl calbus_seq_param_tbl 4096 STD_LOGIC_VECTOR Output + add_instantiation_interface emif_calbus_clk clock INPUT + set_instantiation_interface_parameter_value emif_calbus_clk clockRate {0} + set_instantiation_interface_parameter_value emif_calbus_clk externallyDriven {false} + set_instantiation_interface_parameter_value emif_calbus_clk ptfSchematicName {} + add_instantiation_interface_port emif_calbus_clk calbus_clk clk 1 STD_LOGIC Input + add_instantiation_interface emif_usr_reset_n reset OUTPUT + set_instantiation_interface_parameter_value emif_usr_reset_n associatedClock {} + set_instantiation_interface_parameter_value emif_usr_reset_n associatedDirectReset {} + set_instantiation_interface_parameter_value emif_usr_reset_n associatedResetSinks {none} + set_instantiation_interface_parameter_value emif_usr_reset_n synchronousEdges {NONE} + add_instantiation_interface_port emif_usr_reset_n emif_usr_reset_n reset_n 1 STD_LOGIC Output + add_instantiation_interface emif_usr_clk clock OUTPUT + set_instantiation_interface_parameter_value emif_usr_clk associatedDirectClock {} + set_instantiation_interface_parameter_value emif_usr_clk clockRate {300000000} + set_instantiation_interface_parameter_value emif_usr_clk clockRateKnown {true} + set_instantiation_interface_parameter_value emif_usr_clk externallyDriven {false} + set_instantiation_interface_parameter_value emif_usr_clk ptfSchematicName {} + set_instantiation_interface_sysinfo_parameter_value emif_usr_clk clock_rate {300000000} + add_instantiation_interface_port emif_usr_clk emif_usr_clk clk 1 STD_LOGIC Output + add_instantiation_interface ctrl_ecc_user_interrupt_0 conduit INPUT + set_instantiation_interface_parameter_value ctrl_ecc_user_interrupt_0 associatedClock {} + set_instantiation_interface_parameter_value ctrl_ecc_user_interrupt_0 associatedReset {} + set_instantiation_interface_parameter_value ctrl_ecc_user_interrupt_0 prSafe {false} + add_instantiation_interface_port ctrl_ecc_user_interrupt_0 ctrl_ecc_user_interrupt_0 ctrl_ecc_user_interrupt 1 STD_LOGIC Output + add_instantiation_interface ctrl_amm_0 avalon INPUT + set_instantiation_interface_parameter_value ctrl_amm_0 addressAlignment {DYNAMIC} + set_instantiation_interface_parameter_value ctrl_amm_0 addressGroup {0} + set_instantiation_interface_parameter_value ctrl_amm_0 addressSpan {8589934592} + set_instantiation_interface_parameter_value ctrl_amm_0 addressUnits {WORDS} + set_instantiation_interface_parameter_value ctrl_amm_0 alwaysBurstMaxBurst {false} + set_instantiation_interface_parameter_value ctrl_amm_0 associatedClock {emif_usr_clk} + set_instantiation_interface_parameter_value ctrl_amm_0 associatedReset {emif_usr_reset_n} + set_instantiation_interface_parameter_value ctrl_amm_0 bitsPerSymbol {8} + set_instantiation_interface_parameter_value ctrl_amm_0 bridgedAddressOffset {0} + set_instantiation_interface_parameter_value ctrl_amm_0 bridgesToMaster {} + set_instantiation_interface_parameter_value ctrl_amm_0 burstOnBurstBoundariesOnly {false} + set_instantiation_interface_parameter_value ctrl_amm_0 burstcountUnits {WORDS} + set_instantiation_interface_parameter_value ctrl_amm_0 constantBurstBehavior {false} + set_instantiation_interface_parameter_value ctrl_amm_0 dfhFeatureGuid {0} + set_instantiation_interface_parameter_value ctrl_amm_0 dfhFeatureId {35} + set_instantiation_interface_parameter_value ctrl_amm_0 dfhFeatureMajorVersion {0} + set_instantiation_interface_parameter_value ctrl_amm_0 dfhFeatureMinorVersion {0} + set_instantiation_interface_parameter_value ctrl_amm_0 dfhFeatureType {3} + set_instantiation_interface_parameter_value ctrl_amm_0 dfhGroupId {0} + set_instantiation_interface_parameter_value ctrl_amm_0 dfhParameterData {} + set_instantiation_interface_parameter_value ctrl_amm_0 dfhParameterDataLength {} + set_instantiation_interface_parameter_value ctrl_amm_0 dfhParameterId {} + set_instantiation_interface_parameter_value ctrl_amm_0 dfhParameterName {} + set_instantiation_interface_parameter_value ctrl_amm_0 dfhParameterVersion {} + set_instantiation_interface_parameter_value ctrl_amm_0 explicitAddressSpan {0} + set_instantiation_interface_parameter_value ctrl_amm_0 holdTime {0} + set_instantiation_interface_parameter_value ctrl_amm_0 interleaveBursts {false} + set_instantiation_interface_parameter_value ctrl_amm_0 isBigEndian {false} + set_instantiation_interface_parameter_value ctrl_amm_0 isFlash {false} + set_instantiation_interface_parameter_value ctrl_amm_0 isMemoryDevice {true} + set_instantiation_interface_parameter_value ctrl_amm_0 isNonVolatileStorage {false} + set_instantiation_interface_parameter_value ctrl_amm_0 linewrapBursts {false} + set_instantiation_interface_parameter_value ctrl_amm_0 maximumPendingReadTransactions {64} + set_instantiation_interface_parameter_value ctrl_amm_0 maximumPendingWriteTransactions {0} + set_instantiation_interface_parameter_value ctrl_amm_0 minimumReadLatency {1} + set_instantiation_interface_parameter_value ctrl_amm_0 minimumResponseLatency {1} + set_instantiation_interface_parameter_value ctrl_amm_0 minimumUninterruptedRunLength {1} + set_instantiation_interface_parameter_value ctrl_amm_0 prSafe {false} + set_instantiation_interface_parameter_value ctrl_amm_0 printableDevice {false} + set_instantiation_interface_parameter_value ctrl_amm_0 readLatency {0} + set_instantiation_interface_parameter_value ctrl_amm_0 readWaitStates {1} + set_instantiation_interface_parameter_value ctrl_amm_0 readWaitTime {1} + set_instantiation_interface_parameter_value ctrl_amm_0 registerIncomingSignals {false} + set_instantiation_interface_parameter_value ctrl_amm_0 registerOutgoingSignals {false} + set_instantiation_interface_parameter_value ctrl_amm_0 setupTime {0} + set_instantiation_interface_parameter_value ctrl_amm_0 timingUnits {Cycles} + set_instantiation_interface_parameter_value ctrl_amm_0 transparentBridge {false} + set_instantiation_interface_parameter_value ctrl_amm_0 waitrequestAllowance {0} + set_instantiation_interface_parameter_value ctrl_amm_0 wellBehavedWaitrequest {false} + set_instantiation_interface_parameter_value ctrl_amm_0 writeLatency {0} + set_instantiation_interface_parameter_value ctrl_amm_0 writeWaitStates {0} + set_instantiation_interface_parameter_value ctrl_amm_0 writeWaitTime {0} + set_instantiation_interface_assignment_value ctrl_amm_0 embeddedsw.configuration.isFlash {0} + set_instantiation_interface_assignment_value ctrl_amm_0 embeddedsw.configuration.isMemoryDevice {1} + set_instantiation_interface_assignment_value ctrl_amm_0 embeddedsw.configuration.isNonVolatileStorage {0} + set_instantiation_interface_assignment_value ctrl_amm_0 embeddedsw.configuration.isPrintableDevice {0} + set_instantiation_interface_sysinfo_parameter_value ctrl_amm_0 address_map {} + set_instantiation_interface_sysinfo_parameter_value ctrl_amm_0 address_width {33} + set_instantiation_interface_sysinfo_parameter_value ctrl_amm_0 max_slave_data_width {512} + add_instantiation_interface_port ctrl_amm_0 amm_ready_0 waitrequest_n 1 STD_LOGIC Output + add_instantiation_interface_port ctrl_amm_0 amm_read_0 read 1 STD_LOGIC Input + add_instantiation_interface_port ctrl_amm_0 amm_write_0 write 1 STD_LOGIC Input + add_instantiation_interface_port ctrl_amm_0 amm_address_0 address 27 STD_LOGIC_VECTOR Input + add_instantiation_interface_port ctrl_amm_0 amm_readdata_0 readdata 512 STD_LOGIC_VECTOR Output + add_instantiation_interface_port ctrl_amm_0 amm_writedata_0 writedata 512 STD_LOGIC_VECTOR Input + add_instantiation_interface_port ctrl_amm_0 amm_burstcount_0 burstcount 7 STD_LOGIC_VECTOR Input + add_instantiation_interface_port ctrl_amm_0 amm_byteenable_0 byteenable 64 STD_LOGIC_VECTOR Input + add_instantiation_interface_port ctrl_amm_0 amm_readdatavalid_0 readdatavalid 1 STD_LOGIC Output + save_instantiation + add_component jtag_uart_0 ip/interconnect/interconnect_jtag_uart_0.ip altera_avalon_jtag_uart jtag_uart_0 19.2.4 + load_component jtag_uart_0 + set_component_parameter_value allowMultipleConnections {0} + set_component_parameter_value hubInstanceID {0} + set_component_parameter_value readBufferDepth {64} + set_component_parameter_value readIRQThreshold {8} + set_component_parameter_value simInputCharacterStream {} + set_component_parameter_value simInteractiveOptions {NO_INTERACTIVE_WINDOWS} + set_component_parameter_value useRegistersForReadBuffer {0} + set_component_parameter_value useRegistersForWriteBuffer {0} + set_component_parameter_value useRelativePathForSimFile {0} + set_component_parameter_value writeBufferDepth {64} + set_component_parameter_value writeIRQThreshold {8} + set_component_project_property HIDE_FROM_IP_CATALOG {false} + save_component + load_instantiation jtag_uart_0 + remove_instantiation_interfaces_and_ports + set_instantiation_assignment_value embeddedsw.CMacro.READ_DEPTH {64} + set_instantiation_assignment_value embeddedsw.CMacro.READ_THRESHOLD {8} + set_instantiation_assignment_value embeddedsw.CMacro.WRITE_DEPTH {64} + set_instantiation_assignment_value embeddedsw.CMacro.WRITE_THRESHOLD {8} + set_instantiation_assignment_value embeddedsw.dts.compatible {altr,juart-1.0} + set_instantiation_assignment_value embeddedsw.dts.group {serial} + set_instantiation_assignment_value embeddedsw.dts.name {juart} + set_instantiation_assignment_value embeddedsw.dts.vendor {altr} + add_instantiation_interface clk clock INPUT + set_instantiation_interface_parameter_value clk clockRate {0} + set_instantiation_interface_parameter_value clk externallyDriven {false} + set_instantiation_interface_parameter_value clk ptfSchematicName {} + add_instantiation_interface_port clk clk clk 1 STD_LOGIC Input + add_instantiation_interface reset reset INPUT + set_instantiation_interface_parameter_value reset associatedClock {clk} + set_instantiation_interface_parameter_value reset synchronousEdges {DEASSERT} + add_instantiation_interface_port reset rst_n reset_n 1 STD_LOGIC Input + add_instantiation_interface avalon_jtag_slave avalon INPUT + set_instantiation_interface_parameter_value avalon_jtag_slave addressAlignment {NATIVE} + set_instantiation_interface_parameter_value avalon_jtag_slave addressGroup {0} + set_instantiation_interface_parameter_value avalon_jtag_slave addressSpan {2} + set_instantiation_interface_parameter_value avalon_jtag_slave addressUnits {WORDS} + set_instantiation_interface_parameter_value avalon_jtag_slave alwaysBurstMaxBurst {false} + set_instantiation_interface_parameter_value avalon_jtag_slave associatedClock {clk} + set_instantiation_interface_parameter_value avalon_jtag_slave associatedReset {reset} + set_instantiation_interface_parameter_value avalon_jtag_slave bitsPerSymbol {8} + set_instantiation_interface_parameter_value avalon_jtag_slave bridgedAddressOffset {0} + set_instantiation_interface_parameter_value avalon_jtag_slave bridgesToMaster {} + set_instantiation_interface_parameter_value avalon_jtag_slave burstOnBurstBoundariesOnly {false} + set_instantiation_interface_parameter_value avalon_jtag_slave burstcountUnits {WORDS} + set_instantiation_interface_parameter_value avalon_jtag_slave constantBurstBehavior {false} + set_instantiation_interface_parameter_value avalon_jtag_slave dfhFeatureGuid {0} + set_instantiation_interface_parameter_value avalon_jtag_slave dfhFeatureId {35} + set_instantiation_interface_parameter_value avalon_jtag_slave dfhFeatureMajorVersion {0} + set_instantiation_interface_parameter_value avalon_jtag_slave dfhFeatureMinorVersion {0} + set_instantiation_interface_parameter_value avalon_jtag_slave dfhFeatureType {3} + set_instantiation_interface_parameter_value avalon_jtag_slave dfhGroupId {0} + set_instantiation_interface_parameter_value avalon_jtag_slave dfhParameterData {} + set_instantiation_interface_parameter_value avalon_jtag_slave dfhParameterDataLength {} + set_instantiation_interface_parameter_value avalon_jtag_slave dfhParameterId {} + set_instantiation_interface_parameter_value avalon_jtag_slave dfhParameterName {} + set_instantiation_interface_parameter_value avalon_jtag_slave dfhParameterVersion {} + set_instantiation_interface_parameter_value avalon_jtag_slave explicitAddressSpan {0} + set_instantiation_interface_parameter_value avalon_jtag_slave holdTime {0} + set_instantiation_interface_parameter_value avalon_jtag_slave interleaveBursts {false} + set_instantiation_interface_parameter_value avalon_jtag_slave isBigEndian {false} + set_instantiation_interface_parameter_value avalon_jtag_slave isFlash {false} + set_instantiation_interface_parameter_value avalon_jtag_slave isMemoryDevice {false} + set_instantiation_interface_parameter_value avalon_jtag_slave isNonVolatileStorage {false} + set_instantiation_interface_parameter_value avalon_jtag_slave linewrapBursts {false} + set_instantiation_interface_parameter_value avalon_jtag_slave maximumPendingReadTransactions {0} + set_instantiation_interface_parameter_value avalon_jtag_slave maximumPendingWriteTransactions {0} + set_instantiation_interface_parameter_value avalon_jtag_slave minimumReadLatency {1} + set_instantiation_interface_parameter_value avalon_jtag_slave minimumResponseLatency {1} + set_instantiation_interface_parameter_value avalon_jtag_slave minimumUninterruptedRunLength {1} + set_instantiation_interface_parameter_value avalon_jtag_slave prSafe {false} + set_instantiation_interface_parameter_value avalon_jtag_slave printableDevice {true} + set_instantiation_interface_parameter_value avalon_jtag_slave readLatency {0} + set_instantiation_interface_parameter_value avalon_jtag_slave readWaitStates {1} + set_instantiation_interface_parameter_value avalon_jtag_slave readWaitTime {1} + set_instantiation_interface_parameter_value avalon_jtag_slave registerIncomingSignals {false} + set_instantiation_interface_parameter_value avalon_jtag_slave registerOutgoingSignals {false} + set_instantiation_interface_parameter_value avalon_jtag_slave setupTime {0} + set_instantiation_interface_parameter_value avalon_jtag_slave timingUnits {Cycles} + set_instantiation_interface_parameter_value avalon_jtag_slave transparentBridge {false} + set_instantiation_interface_parameter_value avalon_jtag_slave waitrequestAllowance {0} + set_instantiation_interface_parameter_value avalon_jtag_slave wellBehavedWaitrequest {false} + set_instantiation_interface_parameter_value avalon_jtag_slave writeLatency {0} + set_instantiation_interface_parameter_value avalon_jtag_slave writeWaitStates {0} + set_instantiation_interface_parameter_value avalon_jtag_slave writeWaitTime {0} + set_instantiation_interface_assignment_value avalon_jtag_slave embeddedsw.configuration.isFlash {0} + set_instantiation_interface_assignment_value avalon_jtag_slave embeddedsw.configuration.isMemoryDevice {0} + set_instantiation_interface_assignment_value avalon_jtag_slave embeddedsw.configuration.isNonVolatileStorage {0} + set_instantiation_interface_assignment_value avalon_jtag_slave embeddedsw.configuration.isPrintableDevice {1} + set_instantiation_interface_sysinfo_parameter_value avalon_jtag_slave address_map {} + set_instantiation_interface_sysinfo_parameter_value avalon_jtag_slave address_width {3} + set_instantiation_interface_sysinfo_parameter_value avalon_jtag_slave max_slave_data_width {32} + add_instantiation_interface_port avalon_jtag_slave av_chipselect chipselect 1 STD_LOGIC Input + add_instantiation_interface_port avalon_jtag_slave av_address address 1 STD_LOGIC Input + add_instantiation_interface_port avalon_jtag_slave av_read_n read_n 1 STD_LOGIC Input + add_instantiation_interface_port avalon_jtag_slave av_readdata readdata 32 STD_LOGIC_VECTOR Output + add_instantiation_interface_port avalon_jtag_slave av_write_n write_n 1 STD_LOGIC Input + add_instantiation_interface_port avalon_jtag_slave av_writedata writedata 32 STD_LOGIC_VECTOR Input + add_instantiation_interface_port avalon_jtag_slave av_waitrequest waitrequest 1 STD_LOGIC Output + add_instantiation_interface irq interrupt INPUT + set_instantiation_interface_parameter_value irq associatedAddressablePoint {avalon_jtag_slave} + set_instantiation_interface_parameter_value irq associatedClock {clk} + set_instantiation_interface_parameter_value irq associatedReset {reset} + set_instantiation_interface_parameter_value irq bridgedReceiverOffset {0} + set_instantiation_interface_parameter_value irq bridgesToReceiver {} + set_instantiation_interface_parameter_value irq irqScheme {NONE} + add_instantiation_interface_port irq av_irq irq 1 STD_LOGIC Output + save_instantiation + add_component reset_bridge_0 ip/interconnect/interconnect_reset_bridge_0.ip altera_reset_bridge reset_bridge_0 19.2.0 + load_component reset_bridge_0 + set_component_parameter_value ACTIVE_LOW_RESET {0} + set_component_parameter_value NUM_RESET_OUTPUTS {1} + set_component_parameter_value SYNCHRONOUS_EDGES {deassert} + set_component_parameter_value SYNC_RESET {0} + set_component_parameter_value USE_RESET_REQUEST {0} + set_component_project_property HIDE_FROM_IP_CATALOG {false} + save_component + load_instantiation reset_bridge_0 + remove_instantiation_interfaces_and_ports + add_instantiation_interface clk clock INPUT + set_instantiation_interface_parameter_value clk clockRate {0} + set_instantiation_interface_parameter_value clk externallyDriven {false} + set_instantiation_interface_parameter_value clk ptfSchematicName {} + add_instantiation_interface_port clk clk clk 1 STD_LOGIC Input + add_instantiation_interface in_reset reset INPUT + set_instantiation_interface_parameter_value in_reset associatedClock {clk} + set_instantiation_interface_parameter_value in_reset synchronousEdges {DEASSERT} + add_instantiation_interface_port in_reset in_reset reset 1 STD_LOGIC Input + add_instantiation_interface out_reset reset OUTPUT + set_instantiation_interface_parameter_value out_reset associatedClock {clk} + set_instantiation_interface_parameter_value out_reset associatedDirectReset {in_reset} + set_instantiation_interface_parameter_value out_reset associatedResetSinks {in_reset} + set_instantiation_interface_parameter_value out_reset synchronousEdges {DEASSERT} + add_instantiation_interface_port out_reset out_reset reset 1 STD_LOGIC Output + save_instantiation + + # add wirelevel expressions + + # preserve ports for debug + + # add the connections + add_connection axi_bridge_0.m0/emif_fm_0.ctrl_amm_0 + set_connection_parameter_value axi_bridge_0.m0/emif_fm_0.ctrl_amm_0 addressMapSysInfo {} + set_connection_parameter_value axi_bridge_0.m0/emif_fm_0.ctrl_amm_0 addressWidthSysInfo {} + set_connection_parameter_value axi_bridge_0.m0/emif_fm_0.ctrl_amm_0 arbitrationPriority {1} + set_connection_parameter_value axi_bridge_0.m0/emif_fm_0.ctrl_amm_0 baseAddress {0x0000} + set_connection_parameter_value axi_bridge_0.m0/emif_fm_0.ctrl_amm_0 defaultConnection {0} + set_connection_parameter_value axi_bridge_0.m0/emif_fm_0.ctrl_amm_0 domainAlias {} + set_connection_parameter_value axi_bridge_0.m0/emif_fm_0.ctrl_amm_0 qsys_mm.burstAdapterImplementation {GENERIC_CONVERTER} + set_connection_parameter_value axi_bridge_0.m0/emif_fm_0.ctrl_amm_0 qsys_mm.clockCrossingAdapter {HANDSHAKE} + set_connection_parameter_value axi_bridge_0.m0/emif_fm_0.ctrl_amm_0 qsys_mm.enableAllPipelines {FALSE} + set_connection_parameter_value axi_bridge_0.m0/emif_fm_0.ctrl_amm_0 qsys_mm.enableEccProtection {FALSE} + set_connection_parameter_value axi_bridge_0.m0/emif_fm_0.ctrl_amm_0 qsys_mm.enableInstrumentation {FALSE} + set_connection_parameter_value axi_bridge_0.m0/emif_fm_0.ctrl_amm_0 qsys_mm.enableOutOfOrderSupport {FALSE} + set_connection_parameter_value axi_bridge_0.m0/emif_fm_0.ctrl_amm_0 qsys_mm.insertDefaultSlave {FALSE} + set_connection_parameter_value axi_bridge_0.m0/emif_fm_0.ctrl_amm_0 qsys_mm.interconnectResetSource {DEFAULT} + set_connection_parameter_value axi_bridge_0.m0/emif_fm_0.ctrl_amm_0 qsys_mm.interconnectType {STANDARD} + set_connection_parameter_value axi_bridge_0.m0/emif_fm_0.ctrl_amm_0 qsys_mm.maxAdditionalLatency {1} + set_connection_parameter_value axi_bridge_0.m0/emif_fm_0.ctrl_amm_0 qsys_mm.optimizeRdFifoSize {FALSE} + set_connection_parameter_value axi_bridge_0.m0/emif_fm_0.ctrl_amm_0 qsys_mm.piplineType {PIPELINE_STAGE} + set_connection_parameter_value axi_bridge_0.m0/emif_fm_0.ctrl_amm_0 qsys_mm.responseFifoType {REGISTER_BASED} + set_connection_parameter_value axi_bridge_0.m0/emif_fm_0.ctrl_amm_0 qsys_mm.syncResets {TRUE} + set_connection_parameter_value axi_bridge_0.m0/emif_fm_0.ctrl_amm_0 qsys_mm.widthAdapterImplementation {GENERIC_CONVERTER} + set_connection_parameter_value axi_bridge_0.m0/emif_fm_0.ctrl_amm_0 slaveDataWidthSysInfo {-1} + add_connection axi_bridge_1.m0/jtag_uart_0.avalon_jtag_slave + set_connection_parameter_value axi_bridge_1.m0/jtag_uart_0.avalon_jtag_slave addressMapSysInfo {} + set_connection_parameter_value axi_bridge_1.m0/jtag_uart_0.avalon_jtag_slave addressWidthSysInfo {} + set_connection_parameter_value axi_bridge_1.m0/jtag_uart_0.avalon_jtag_slave arbitrationPriority {1} + set_connection_parameter_value axi_bridge_1.m0/jtag_uart_0.avalon_jtag_slave baseAddress {0x0000} + set_connection_parameter_value axi_bridge_1.m0/jtag_uart_0.avalon_jtag_slave defaultConnection {0} + set_connection_parameter_value axi_bridge_1.m0/jtag_uart_0.avalon_jtag_slave domainAlias {} + set_connection_parameter_value axi_bridge_1.m0/jtag_uart_0.avalon_jtag_slave qsys_mm.burstAdapterImplementation {GENERIC_CONVERTER} + set_connection_parameter_value axi_bridge_1.m0/jtag_uart_0.avalon_jtag_slave qsys_mm.clockCrossingAdapter {HANDSHAKE} + set_connection_parameter_value axi_bridge_1.m0/jtag_uart_0.avalon_jtag_slave qsys_mm.enableAllPipelines {FALSE} + set_connection_parameter_value axi_bridge_1.m0/jtag_uart_0.avalon_jtag_slave qsys_mm.enableEccProtection {FALSE} + set_connection_parameter_value axi_bridge_1.m0/jtag_uart_0.avalon_jtag_slave qsys_mm.enableInstrumentation {FALSE} + set_connection_parameter_value axi_bridge_1.m0/jtag_uart_0.avalon_jtag_slave qsys_mm.enableOutOfOrderSupport {FALSE} + set_connection_parameter_value axi_bridge_1.m0/jtag_uart_0.avalon_jtag_slave qsys_mm.insertDefaultSlave {FALSE} + set_connection_parameter_value axi_bridge_1.m0/jtag_uart_0.avalon_jtag_slave qsys_mm.interconnectResetSource {DEFAULT} + set_connection_parameter_value axi_bridge_1.m0/jtag_uart_0.avalon_jtag_slave qsys_mm.interconnectType {STANDARD} + set_connection_parameter_value axi_bridge_1.m0/jtag_uart_0.avalon_jtag_slave qsys_mm.maxAdditionalLatency {1} + set_connection_parameter_value axi_bridge_1.m0/jtag_uart_0.avalon_jtag_slave qsys_mm.optimizeRdFifoSize {FALSE} + set_connection_parameter_value axi_bridge_1.m0/jtag_uart_0.avalon_jtag_slave qsys_mm.piplineType {PIPELINE_STAGE} + set_connection_parameter_value axi_bridge_1.m0/jtag_uart_0.avalon_jtag_slave qsys_mm.responseFifoType {REGISTER_BASED} + set_connection_parameter_value axi_bridge_1.m0/jtag_uart_0.avalon_jtag_slave qsys_mm.syncResets {TRUE} + set_connection_parameter_value axi_bridge_1.m0/jtag_uart_0.avalon_jtag_slave qsys_mm.widthAdapterImplementation {GENERIC_CONVERTER} + set_connection_parameter_value axi_bridge_1.m0/jtag_uart_0.avalon_jtag_slave slaveDataWidthSysInfo {-1} + add_connection emif_cal_0.emif_calbus_0/emif_fm_0.emif_calbus + set_connection_parameter_value emif_cal_0.emif_calbus_0/emif_fm_0.emif_calbus endPort {} + set_connection_parameter_value emif_cal_0.emif_calbus_0/emif_fm_0.emif_calbus endPortLSB {0} + set_connection_parameter_value emif_cal_0.emif_calbus_0/emif_fm_0.emif_calbus startPort {} + set_connection_parameter_value emif_cal_0.emif_calbus_0/emif_fm_0.emif_calbus startPortLSB {0} + set_connection_parameter_value emif_cal_0.emif_calbus_0/emif_fm_0.emif_calbus width {0} + add_connection emif_cal_0.emif_calbus_clk/emif_fm_0.emif_calbus_clk + set_connection_parameter_value emif_cal_0.emif_calbus_clk/emif_fm_0.emif_calbus_clk clockDomainSysInfo {-1} + set_connection_parameter_value emif_cal_0.emif_calbus_clk/emif_fm_0.emif_calbus_clk clockRateSysInfo {} + set_connection_parameter_value emif_cal_0.emif_calbus_clk/emif_fm_0.emif_calbus_clk clockResetSysInfo {} + set_connection_parameter_value emif_cal_0.emif_calbus_clk/emif_fm_0.emif_calbus_clk resetDomainSysInfo {-1} + add_connection emif_fm_0.emif_usr_clk/axi_bridge_0.clk + set_connection_parameter_value emif_fm_0.emif_usr_clk/axi_bridge_0.clk clockDomainSysInfo {-1} + set_connection_parameter_value emif_fm_0.emif_usr_clk/axi_bridge_0.clk clockRateSysInfo {300000000.0} + set_connection_parameter_value emif_fm_0.emif_usr_clk/axi_bridge_0.clk clockResetSysInfo {} + set_connection_parameter_value emif_fm_0.emif_usr_clk/axi_bridge_0.clk resetDomainSysInfo {-1} + add_connection emif_fm_0.emif_usr_clk/axi_bridge_1.clk + set_connection_parameter_value emif_fm_0.emif_usr_clk/axi_bridge_1.clk clockDomainSysInfo {-1} + set_connection_parameter_value emif_fm_0.emif_usr_clk/axi_bridge_1.clk clockRateSysInfo {300000000.0} + set_connection_parameter_value emif_fm_0.emif_usr_clk/axi_bridge_1.clk clockResetSysInfo {} + set_connection_parameter_value emif_fm_0.emif_usr_clk/axi_bridge_1.clk resetDomainSysInfo {-1} + add_connection emif_fm_0.emif_usr_clk/jtag_uart_0.clk + set_connection_parameter_value emif_fm_0.emif_usr_clk/jtag_uart_0.clk clockDomainSysInfo {-1} + set_connection_parameter_value emif_fm_0.emif_usr_clk/jtag_uart_0.clk clockRateSysInfo {300000000.0} + set_connection_parameter_value emif_fm_0.emif_usr_clk/jtag_uart_0.clk clockResetSysInfo {} + set_connection_parameter_value emif_fm_0.emif_usr_clk/jtag_uart_0.clk resetDomainSysInfo {-1} + add_connection emif_fm_0.emif_usr_clk/reset_bridge_0.clk + set_connection_parameter_value emif_fm_0.emif_usr_clk/reset_bridge_0.clk clockDomainSysInfo {-1} + set_connection_parameter_value emif_fm_0.emif_usr_clk/reset_bridge_0.clk clockRateSysInfo {300000000.0} + set_connection_parameter_value emif_fm_0.emif_usr_clk/reset_bridge_0.clk clockResetSysInfo {} + set_connection_parameter_value emif_fm_0.emif_usr_clk/reset_bridge_0.clk resetDomainSysInfo {-1} + add_connection reset_bridge_0.out_reset/axi_bridge_0.clk_reset + set_connection_parameter_value reset_bridge_0.out_reset/axi_bridge_0.clk_reset clockDomainSysInfo {-1} + set_connection_parameter_value reset_bridge_0.out_reset/axi_bridge_0.clk_reset clockResetSysInfo {} + set_connection_parameter_value reset_bridge_0.out_reset/axi_bridge_0.clk_reset resetDomainSysInfo {-1} + add_connection reset_bridge_0.out_reset/axi_bridge_1.clk_reset + set_connection_parameter_value reset_bridge_0.out_reset/axi_bridge_1.clk_reset clockDomainSysInfo {-1} + set_connection_parameter_value reset_bridge_0.out_reset/axi_bridge_1.clk_reset clockResetSysInfo {} + set_connection_parameter_value reset_bridge_0.out_reset/axi_bridge_1.clk_reset resetDomainSysInfo {-1} + add_connection reset_bridge_0.out_reset/jtag_uart_0.reset + set_connection_parameter_value reset_bridge_0.out_reset/jtag_uart_0.reset clockDomainSysInfo {-1} + set_connection_parameter_value reset_bridge_0.out_reset/jtag_uart_0.reset clockResetSysInfo {} + set_connection_parameter_value reset_bridge_0.out_reset/jtag_uart_0.reset resetDomainSysInfo {-1} + + # add the exports + set_interface_property axi_bridge_1_s0 EXPORT_OF axi_bridge_1.s0 + set_interface_property emif_fm_0_local_reset_req EXPORT_OF emif_fm_0.local_reset_req + set_interface_property emif_fm_0_local_reset_status EXPORT_OF emif_fm_0.local_reset_status + set_interface_property emif_fm_0_pll_ref_clk EXPORT_OF emif_fm_0.pll_ref_clk + set_interface_property emif_fm_0_pll_locked EXPORT_OF emif_fm_0.pll_locked + set_interface_property emif_fm_0_oct EXPORT_OF emif_fm_0.oct + set_interface_property emif_fm_0_mem EXPORT_OF emif_fm_0.mem + set_interface_property emif_fm_0_status EXPORT_OF emif_fm_0.status + set_interface_property emif_fm_0_emif_usr_reset_n EXPORT_OF emif_fm_0.emif_usr_reset_n + set_interface_property emif_fm_0_ctrl_ecc_user_interrupt_0 EXPORT_OF emif_fm_0.ctrl_ecc_user_interrupt_0 + set_interface_property jtag_uart_0_irq EXPORT_OF jtag_uart_0.irq + set_interface_property reset_bridge_0_in_reset EXPORT_OF reset_bridge_0.in_reset + + # set values for exposed HDL parameters + set_domain_assignment axi_bridge_0.m0 qsys_mm.burstAdapterImplementation GENERIC_CONVERTER + set_domain_assignment axi_bridge_0.m0 qsys_mm.clockCrossingAdapter HANDSHAKE + set_domain_assignment axi_bridge_0.m0 qsys_mm.enableAllPipelines FALSE + set_domain_assignment axi_bridge_0.m0 qsys_mm.enableEccProtection FALSE + set_domain_assignment axi_bridge_0.m0 qsys_mm.enableInstrumentation FALSE + set_domain_assignment axi_bridge_0.m0 qsys_mm.enableOutOfOrderSupport FALSE + set_domain_assignment axi_bridge_0.m0 qsys_mm.insertDefaultSlave FALSE + set_domain_assignment axi_bridge_0.m0 qsys_mm.interconnectResetSource DEFAULT + set_domain_assignment axi_bridge_0.m0 qsys_mm.interconnectType STANDARD + set_domain_assignment axi_bridge_0.m0 qsys_mm.maxAdditionalLatency 1 + set_domain_assignment axi_bridge_0.m0 qsys_mm.optimizeRdFifoSize FALSE + set_domain_assignment axi_bridge_0.m0 qsys_mm.piplineType PIPELINE_STAGE + set_domain_assignment axi_bridge_0.m0 qsys_mm.responseFifoType REGISTER_BASED + set_domain_assignment axi_bridge_0.m0 qsys_mm.syncResets TRUE + set_domain_assignment axi_bridge_0.m0 qsys_mm.widthAdapterImplementation GENERIC_CONVERTER + set_domain_assignment axi_bridge_1.m0 qsys_mm.burstAdapterImplementation GENERIC_CONVERTER + set_domain_assignment axi_bridge_1.m0 qsys_mm.clockCrossingAdapter HANDSHAKE + set_domain_assignment axi_bridge_1.m0 qsys_mm.enableAllPipelines FALSE + set_domain_assignment axi_bridge_1.m0 qsys_mm.enableEccProtection FALSE + set_domain_assignment axi_bridge_1.m0 qsys_mm.enableInstrumentation FALSE + set_domain_assignment axi_bridge_1.m0 qsys_mm.enableOutOfOrderSupport FALSE + set_domain_assignment axi_bridge_1.m0 qsys_mm.insertDefaultSlave FALSE + set_domain_assignment axi_bridge_1.m0 qsys_mm.interconnectResetSource DEFAULT + set_domain_assignment axi_bridge_1.m0 qsys_mm.interconnectType STANDARD + set_domain_assignment axi_bridge_1.m0 qsys_mm.maxAdditionalLatency 1 + set_domain_assignment axi_bridge_1.m0 qsys_mm.optimizeRdFifoSize FALSE + set_domain_assignment axi_bridge_1.m0 qsys_mm.piplineType PIPELINE_STAGE + set_domain_assignment axi_bridge_1.m0 qsys_mm.responseFifoType REGISTER_BASED + set_domain_assignment axi_bridge_1.m0 qsys_mm.syncResets TRUE + set_domain_assignment axi_bridge_1.m0 qsys_mm.widthAdapterImplementation GENERIC_CONVERTER + + # set the the module properties + set_module_property BONUS_DATA { + + + + + + + + + + + + + + + + + + + + + + + +} + set_module_property FILE {interconnect.qsys} + set_module_property GENERATION_ID {0x00000000} + set_module_property NAME {interconnect} + + # save the system + sync_sysinfo_parameters + save_system interconnect +} + +proc do_set_exported_interface_sysinfo_parameters {} { +} + +# create all the systems, from bottom up +do_create_interconnect + +# set system info parameters on exported interface, from bottom up +do_set_exported_interface_sysinfo_parameters diff --git a/corev_apu/altera/ip/io_pll.tcl b/corev_apu/altera/ip/io_pll.tcl new file mode 100644 index 0000000000..ea1e4b2986 --- /dev/null +++ b/corev_apu/altera/ip/io_pll.tcl @@ -0,0 +1,312 @@ +# Quartus Pro License required to use this file +package require -exact qsys 24.1 + +# create the system "io_pll" +proc do_create_io_pll {} { + # create the system + create_system io_pll + set_project_property BOARD {default} + set_project_property DEVICE {AGFB014R24B2E2V} + set_project_property DEVICE_FAMILY {Agilex 7} + set_project_property HIDE_FROM_IP_CATALOG {true} + set_use_testbench_naming_pattern 0 {} + + # add HDL parameters + + # add the components + add_instance iopll_0 altera_iopll 19.3.1 + set_instance_parameter_value iopll_0 {gui_active_clk} {0} + set_instance_parameter_value iopll_0 {gui_c_cnt_in_src0} {c_m_cnt_in_src_ph_mux_clk} + set_instance_parameter_value iopll_0 {gui_c_cnt_in_src1} {c_m_cnt_in_src_ph_mux_clk} + set_instance_parameter_value iopll_0 {gui_c_cnt_in_src2} {c_m_cnt_in_src_ph_mux_clk} + set_instance_parameter_value iopll_0 {gui_c_cnt_in_src3} {c_m_cnt_in_src_ph_mux_clk} + set_instance_parameter_value iopll_0 {gui_c_cnt_in_src4} {c_m_cnt_in_src_ph_mux_clk} + set_instance_parameter_value iopll_0 {gui_c_cnt_in_src5} {c_m_cnt_in_src_ph_mux_clk} + set_instance_parameter_value iopll_0 {gui_c_cnt_in_src6} {c_m_cnt_in_src_ph_mux_clk} + set_instance_parameter_value iopll_0 {gui_c_cnt_in_src7} {c_m_cnt_in_src_ph_mux_clk} + set_instance_parameter_value iopll_0 {gui_c_cnt_in_src8} {c_m_cnt_in_src_ph_mux_clk} + set_instance_parameter_value iopll_0 {gui_cal_code_hex_file} {iossm.hex} + set_instance_parameter_value iopll_0 {gui_cal_converge} {0} + set_instance_parameter_value iopll_0 {gui_cal_error} {cal_clean} + set_instance_parameter_value iopll_0 {gui_cascade_counter0} {0} + set_instance_parameter_value iopll_0 {gui_cascade_counter1} {0} + set_instance_parameter_value iopll_0 {gui_cascade_counter10} {0} + set_instance_parameter_value iopll_0 {gui_cascade_counter11} {0} + set_instance_parameter_value iopll_0 {gui_cascade_counter12} {0} + set_instance_parameter_value iopll_0 {gui_cascade_counter13} {0} + set_instance_parameter_value iopll_0 {gui_cascade_counter14} {0} + set_instance_parameter_value iopll_0 {gui_cascade_counter15} {0} + set_instance_parameter_value iopll_0 {gui_cascade_counter16} {0} + set_instance_parameter_value iopll_0 {gui_cascade_counter17} {0} + set_instance_parameter_value iopll_0 {gui_cascade_counter2} {0} + set_instance_parameter_value iopll_0 {gui_cascade_counter3} {0} + set_instance_parameter_value iopll_0 {gui_cascade_counter4} {0} + set_instance_parameter_value iopll_0 {gui_cascade_counter5} {0} + set_instance_parameter_value iopll_0 {gui_cascade_counter6} {0} + set_instance_parameter_value iopll_0 {gui_cascade_counter7} {0} + set_instance_parameter_value iopll_0 {gui_cascade_counter8} {0} + set_instance_parameter_value iopll_0 {gui_cascade_counter9} {0} + set_instance_parameter_value iopll_0 {gui_cascade_outclk_index} {0} + set_instance_parameter_value iopll_0 {gui_clk_bad} {0} + set_instance_parameter_value iopll_0 {gui_clock_name_global} {0} + set_instance_parameter_value iopll_0 {gui_clock_name_string0} {outclk0} + set_instance_parameter_value iopll_0 {gui_clock_name_string1} {outclk1} + set_instance_parameter_value iopll_0 {gui_clock_name_string10} {outclk10} + set_instance_parameter_value iopll_0 {gui_clock_name_string11} {outclk11} + set_instance_parameter_value iopll_0 {gui_clock_name_string12} {outclk12} + set_instance_parameter_value iopll_0 {gui_clock_name_string13} {outclk13} + set_instance_parameter_value iopll_0 {gui_clock_name_string14} {outclk14} + set_instance_parameter_value iopll_0 {gui_clock_name_string15} {outclk15} + set_instance_parameter_value iopll_0 {gui_clock_name_string16} {outclk16} + set_instance_parameter_value iopll_0 {gui_clock_name_string17} {outclk17} + set_instance_parameter_value iopll_0 {gui_clock_name_string2} {outclk2} + set_instance_parameter_value iopll_0 {gui_clock_name_string3} {outclk3} + set_instance_parameter_value iopll_0 {gui_clock_name_string4} {outclk4} + set_instance_parameter_value iopll_0 {gui_clock_name_string5} {outclk5} + set_instance_parameter_value iopll_0 {gui_clock_name_string6} {outclk6} + set_instance_parameter_value iopll_0 {gui_clock_name_string7} {outclk7} + set_instance_parameter_value iopll_0 {gui_clock_name_string8} {outclk8} + set_instance_parameter_value iopll_0 {gui_clock_name_string9} {outclk9} + set_instance_parameter_value iopll_0 {gui_clock_to_compensate} {0} + set_instance_parameter_value iopll_0 {gui_debug_mode} {0} + set_instance_parameter_value iopll_0 {gui_divide_factor_c0} {1} + set_instance_parameter_value iopll_0 {gui_divide_factor_c1} {25} + set_instance_parameter_value iopll_0 {gui_divide_factor_c10} {6} + set_instance_parameter_value iopll_0 {gui_divide_factor_c11} {6} + set_instance_parameter_value iopll_0 {gui_divide_factor_c12} {6} + set_instance_parameter_value iopll_0 {gui_divide_factor_c13} {6} + set_instance_parameter_value iopll_0 {gui_divide_factor_c14} {6} + set_instance_parameter_value iopll_0 {gui_divide_factor_c15} {6} + set_instance_parameter_value iopll_0 {gui_divide_factor_c16} {6} + set_instance_parameter_value iopll_0 {gui_divide_factor_c17} {6} + set_instance_parameter_value iopll_0 {gui_divide_factor_c2} {25} + set_instance_parameter_value iopll_0 {gui_divide_factor_c3} {6} + set_instance_parameter_value iopll_0 {gui_divide_factor_c4} {6} + set_instance_parameter_value iopll_0 {gui_divide_factor_c5} {6} + set_instance_parameter_value iopll_0 {gui_divide_factor_c6} {6} + set_instance_parameter_value iopll_0 {gui_divide_factor_c7} {6} + set_instance_parameter_value iopll_0 {gui_divide_factor_c8} {6} + set_instance_parameter_value iopll_0 {gui_divide_factor_c9} {6} + set_instance_parameter_value iopll_0 {gui_divide_factor_n} {6} + set_instance_parameter_value iopll_0 {gui_dps_cntr} {C0} + set_instance_parameter_value iopll_0 {gui_dps_dir} {Positive} + set_instance_parameter_value iopll_0 {gui_dps_num} {1} + set_instance_parameter_value iopll_0 {gui_dsm_out_sel} {1st_order} + set_instance_parameter_value iopll_0 {gui_duty_cycle0} {50.0} + set_instance_parameter_value iopll_0 {gui_duty_cycle1} {50.0} + set_instance_parameter_value iopll_0 {gui_duty_cycle10} {50.0} + set_instance_parameter_value iopll_0 {gui_duty_cycle11} {50.0} + set_instance_parameter_value iopll_0 {gui_duty_cycle12} {50.0} + set_instance_parameter_value iopll_0 {gui_duty_cycle13} {50.0} + set_instance_parameter_value iopll_0 {gui_duty_cycle14} {50.0} + set_instance_parameter_value iopll_0 {gui_duty_cycle15} {50.0} + set_instance_parameter_value iopll_0 {gui_duty_cycle16} {50.0} + set_instance_parameter_value iopll_0 {gui_duty_cycle17} {50.0} + set_instance_parameter_value iopll_0 {gui_duty_cycle2} {50.0} + set_instance_parameter_value iopll_0 {gui_duty_cycle3} {50.0} + set_instance_parameter_value iopll_0 {gui_duty_cycle4} {50.0} + set_instance_parameter_value iopll_0 {gui_duty_cycle5} {50.0} + set_instance_parameter_value iopll_0 {gui_duty_cycle6} {50.0} + set_instance_parameter_value iopll_0 {gui_duty_cycle7} {50.0} + set_instance_parameter_value iopll_0 {gui_duty_cycle8} {50.0} + set_instance_parameter_value iopll_0 {gui_duty_cycle9} {50.0} + set_instance_parameter_value iopll_0 {gui_en_adv_params} {0} + set_instance_parameter_value iopll_0 {gui_en_dps_ports} {0} + set_instance_parameter_value iopll_0 {gui_en_extclkout_ports} {0} + set_instance_parameter_value iopll_0 {gui_en_iossm_reconf} {0} + set_instance_parameter_value iopll_0 {gui_en_lvds_ports} {Disabled} + set_instance_parameter_value iopll_0 {gui_en_periphery_ports} {0} + set_instance_parameter_value iopll_0 {gui_en_phout_ports} {0} + set_instance_parameter_value iopll_0 {gui_en_reconf} {0} + set_instance_parameter_value iopll_0 {gui_enable_cascade_in} {0} + set_instance_parameter_value iopll_0 {gui_enable_cascade_out} {0} + set_instance_parameter_value iopll_0 {gui_enable_mif_dps} {0} + set_instance_parameter_value iopll_0 {gui_enable_output_counter_cascading} {0} + set_instance_parameter_value iopll_0 {gui_enable_permit_cal} {0} + set_instance_parameter_value iopll_0 {gui_enable_upstream_out_clk} {0} + set_instance_parameter_value iopll_0 {gui_existing_mif_file_path} {~/pll.mif} + set_instance_parameter_value iopll_0 {gui_extclkout_0_source} {C0} + set_instance_parameter_value iopll_0 {gui_extclkout_1_source} {C0} + set_instance_parameter_value iopll_0 {gui_extclkout_source} {C0} + set_instance_parameter_value iopll_0 {gui_feedback_clock} {Global Clock} + set_instance_parameter_value iopll_0 {gui_fix_vco_frequency} {0} + set_instance_parameter_value iopll_0 {gui_fixed_vco_frequency} {600.0} + set_instance_parameter_value iopll_0 {gui_fixed_vco_frequency_ps} {1667.0} + set_instance_parameter_value iopll_0 {gui_frac_multiply_factor} {1.0} + set_instance_parameter_value iopll_0 {gui_fractional_cout} {32} + set_instance_parameter_value iopll_0 {gui_include_iossm} {0} + set_instance_parameter_value iopll_0 {gui_location_type} {I/O Bank} + set_instance_parameter_value iopll_0 {gui_lock_setting} {Low Lock Time} + set_instance_parameter_value iopll_0 {gui_mif_config_name} {unnamed} + set_instance_parameter_value iopll_0 {gui_mif_gen_options} {Generate New MIF File} + set_instance_parameter_value iopll_0 {gui_multiply_factor} {25} + set_instance_parameter_value iopll_0 {gui_new_mif_file_path} {~/pll.mif} + set_instance_parameter_value iopll_0 {gui_number_of_clocks} {5} + set_instance_parameter_value iopll_0 {gui_operation_mode} {direct} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency0} {200.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency1} {125.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency10} {100.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency11} {100.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency12} {100.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency13} {100.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency14} {100.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency15} {100.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency16} {100.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency17} {100.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency2} {200.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency3} {125.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency4} {100.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency5} {100.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency6} {100.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency7} {100.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency8} {100.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency9} {100.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps0} {5000.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps1} {8000.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps10} {10000.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps11} {10000.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps12} {10000.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps13} {10000.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps14} {10000.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps15} {10000.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps16} {10000.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps17} {10000.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps2} {5000.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps3} {8000.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps4} {10000.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps5} {10000.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps6} {10000.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps7} {10000.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps8} {10000.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps9} {10000.0} + set_instance_parameter_value iopll_0 {gui_parameter_table_hex_file} {seq_params_sim.hex} + set_instance_parameter_value iopll_0 {gui_phase_shift0} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift1} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift10} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift11} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift12} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift13} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift14} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift15} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift16} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift17} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift2} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift3} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift4} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift5} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift6} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift7} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift8} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift9} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift_deg0} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift_deg1} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift_deg10} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift_deg11} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift_deg12} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift_deg13} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift_deg14} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift_deg15} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift_deg16} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift_deg17} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift_deg2} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift_deg3} {90.0} + set_instance_parameter_value iopll_0 {gui_phase_shift_deg4} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift_deg5} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift_deg6} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift_deg7} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift_deg8} {0.0} + set_instance_parameter_value iopll_0 {gui_phase_shift_deg9} {0.0} + set_instance_parameter_value iopll_0 {gui_phout_division} {1} + set_instance_parameter_value iopll_0 {gui_pll_auto_reset} {0} + set_instance_parameter_value iopll_0 {gui_pll_bandwidth_preset} {Medium} + set_instance_parameter_value iopll_0 {gui_pll_cal_done} {0} + set_instance_parameter_value iopll_0 {gui_pll_cascading_mode} {adjpllin} + set_instance_parameter_value iopll_0 {gui_pll_freqcal_en} {1} + set_instance_parameter_value iopll_0 {gui_pll_freqcal_req_flag} {1} + set_instance_parameter_value iopll_0 {gui_pll_m_cnt_in_src} {c_m_cnt_in_src_ph_mux_clk} + set_instance_parameter_value iopll_0 {gui_pll_mode} {Integer-N PLL} + set_instance_parameter_value iopll_0 {gui_pll_tclk_mux_en} {0} + set_instance_parameter_value iopll_0 {gui_pll_tclk_sel} {pll_tclk_m_src} + set_instance_parameter_value iopll_0 {gui_pll_type} {S10_Simple} + set_instance_parameter_value iopll_0 {gui_pll_vco_freq_band_0} {pll_freq_clk0_band18} + set_instance_parameter_value iopll_0 {gui_pll_vco_freq_band_1} {pll_freq_clk1_band18} + set_instance_parameter_value iopll_0 {gui_prot_mode} {UNUSED} + set_instance_parameter_value iopll_0 {gui_ps_units0} {ps} + set_instance_parameter_value iopll_0 {gui_ps_units1} {ps} + set_instance_parameter_value iopll_0 {gui_ps_units10} {ps} + set_instance_parameter_value iopll_0 {gui_ps_units11} {ps} + set_instance_parameter_value iopll_0 {gui_ps_units12} {ps} + set_instance_parameter_value iopll_0 {gui_ps_units13} {ps} + set_instance_parameter_value iopll_0 {gui_ps_units14} {ps} + set_instance_parameter_value iopll_0 {gui_ps_units15} {ps} + set_instance_parameter_value iopll_0 {gui_ps_units16} {ps} + set_instance_parameter_value iopll_0 {gui_ps_units17} {ps} + set_instance_parameter_value iopll_0 {gui_ps_units2} {ps} + set_instance_parameter_value iopll_0 {gui_ps_units3} {degrees} + set_instance_parameter_value iopll_0 {gui_ps_units4} {ps} + set_instance_parameter_value iopll_0 {gui_ps_units5} {ps} + set_instance_parameter_value iopll_0 {gui_ps_units6} {ps} + set_instance_parameter_value iopll_0 {gui_ps_units7} {ps} + set_instance_parameter_value iopll_0 {gui_ps_units8} {ps} + set_instance_parameter_value iopll_0 {gui_ps_units9} {ps} + set_instance_parameter_value iopll_0 {gui_refclk1_frequency} {100.0} + set_instance_parameter_value iopll_0 {gui_refclk_might_change} {0} + set_instance_parameter_value iopll_0 {gui_refclk_switch} {0} + set_instance_parameter_value iopll_0 {gui_reference_clock_frequency} {100.0} + set_instance_parameter_value iopll_0 {gui_reference_clock_frequency_ps} {10000.0} + set_instance_parameter_value iopll_0 {gui_simulation_type} {0} + set_instance_parameter_value iopll_0 {gui_skip_sdc_generation} {0} + set_instance_parameter_value iopll_0 {gui_switchover_delay} {0} + set_instance_parameter_value iopll_0 {gui_switchover_mode} {Automatic Switchover} + set_instance_parameter_value iopll_0 {gui_use_NDFB_modes} {0} + set_instance_parameter_value iopll_0 {gui_use_coreclk} {1} + set_instance_parameter_value iopll_0 {gui_use_locked} {1} + set_instance_parameter_value iopll_0 {gui_use_logical} {0} + set_instance_parameter_value iopll_0 {gui_user_base_address} {0} + set_instance_parameter_value iopll_0 {gui_usr_device_speed_grade} {1} + set_instance_parameter_value iopll_0 {gui_vco_frequency} {1250.0} + set_instance_parameter_value iopll_0 {hp_qsys_scripting_mode} {0} + set_instance_parameter_value iopll_0 {system_info_device_iobank_rev} {} + set_instance_property iopll_0 AUTO_EXPORT true + + # add wirelevel expressions + + # preserve ports for debug + + # add the exports + set_interface_property refclk EXPORT_OF iopll_0.refclk + set_interface_property locked EXPORT_OF iopll_0.locked + set_interface_property reset EXPORT_OF iopll_0.reset + set_interface_property outclk0 EXPORT_OF iopll_0.outclk0 + set_interface_property outclk1 EXPORT_OF iopll_0.outclk1 + set_interface_property outclk2 EXPORT_OF iopll_0.outclk2 + set_interface_property outclk3 EXPORT_OF iopll_0.outclk3 + set_interface_property outclk4 EXPORT_OF iopll_0.outclk4 + + # set values for exposed HDL parameters + + # set the the module properties + set_module_property BONUS_DATA { + + + + + +} + set_module_property FILE {io_pll.ip} + set_module_property GENERATION_ID {0x00000000} + set_module_property NAME {io_pll} + + # save the system + sync_sysinfo_parameters + save_system io_pll +} + +proc do_set_exported_interface_sysinfo_parameters {} { +} + +# create all the systems, from bottom up +do_create_io_pll + +# set system info parameters on exported interface, from bottom up +do_set_exported_interface_sysinfo_parameters diff --git a/corev_apu/altera/ip/iobuf.tcl b/corev_apu/altera/ip/iobuf.tcl new file mode 100644 index 0000000000..f6528a8af0 --- /dev/null +++ b/corev_apu/altera/ip/iobuf.tcl @@ -0,0 +1,75 @@ +# Quartus Pro License required to use this file +package require -exact qsys 24.1 + +# create the system "iobuf" +proc do_create_iobuf {} { + # create the system + create_system iobuf + set_project_property BOARD {default} + set_project_property DEVICE {AGFB014R24B2E2V} + set_project_property DEVICE_FAMILY {Agilex 7} + set_project_property HIDE_FROM_IP_CATALOG {true} + set_use_testbench_naming_pattern 0 {} + + # add HDL parameters + + # add the components + add_instance gpio_0 altera_gpio 22.1.0 + set_instance_parameter_value gpio_0 {EXT_DRIVER_PARAM} {0} + set_instance_parameter_value gpio_0 {GENERATE_SDC_FILE} {0} + set_instance_parameter_value gpio_0 {IP_MIGRATE_PORT_MAP_FILE} {altddio_bidir_port_map.csv} + set_instance_parameter_value gpio_0 {PIN_TYPE_GUI} {Bidir} + set_instance_parameter_value gpio_0 {SIZE} {1} + set_instance_parameter_value gpio_0 {gui_areset_mode} {None} + set_instance_parameter_value gpio_0 {gui_bus_hold} {0} + set_instance_parameter_value gpio_0 {gui_ddio_with_delay} {0} + set_instance_parameter_value gpio_0 {gui_diff_buff} {0} + set_instance_parameter_value gpio_0 {gui_enable_cke} {0} + set_instance_parameter_value gpio_0 {gui_enable_migratable_port_names} {0} + set_instance_parameter_value gpio_0 {gui_enable_termination_ports} {0} + set_instance_parameter_value gpio_0 {gui_hr_logic} {0} + set_instance_parameter_value gpio_0 {gui_io_reg_mode} {none} + set_instance_parameter_value gpio_0 {gui_open_drain} {0} + set_instance_parameter_value gpio_0 {gui_pseudo_diff} {0} + set_instance_parameter_value gpio_0 {gui_separate_io_clks} {0} + set_instance_parameter_value gpio_0 {gui_sreset_mode} {None} + set_instance_parameter_value gpio_0 {gui_use_oe} {0} + set_instance_property gpio_0 AUTO_EXPORT true + + # add wirelevel expressions + + # preserve ports for debug + + # add the exports + set_interface_property dout EXPORT_OF gpio_0.dout + set_interface_property din EXPORT_OF gpio_0.din + set_interface_property oe EXPORT_OF gpio_0.oe + set_interface_property pad_io EXPORT_OF gpio_0.pad_io + + # set values for exposed HDL parameters + + # set the the module properties + set_module_property BONUS_DATA { + + + + + +} + set_module_property FILE {iobuf.ip} + set_module_property GENERATION_ID {0x00000000} + set_module_property NAME {iobuf} + + # save the system + sync_sysinfo_parameters + save_system iobuf +} + +proc do_set_exported_interface_sysinfo_parameters {} { +} + +# create all the systems, from bottom up +do_create_iobuf + +# set system info parameters on exported interface, from bottom up +do_set_exported_interface_sysinfo_parameters diff --git a/corev_apu/altera/ip/oddr_intel.tcl b/corev_apu/altera/ip/oddr_intel.tcl new file mode 100644 index 0000000000..1b08417f1f --- /dev/null +++ b/corev_apu/altera/ip/oddr_intel.tcl @@ -0,0 +1,74 @@ +# Quartus Pro License required to use this file +package require -exact qsys 24.1 + +# create the system "oddr_intel" +proc do_create_oddr_intel {} { + # create the system + create_system oddr_intel + set_project_property BOARD {default} + set_project_property DEVICE {AGFB014R24B2E2V} + set_project_property DEVICE_FAMILY {Agilex 7} + set_project_property HIDE_FROM_IP_CATALOG {true} + set_use_testbench_naming_pattern 0 {} + + # add HDL parameters + + # add the components + add_instance gpio_0 altera_gpio 22.1.0 + set_instance_parameter_value gpio_0 {EXT_DRIVER_PARAM} {0} + set_instance_parameter_value gpio_0 {GENERATE_SDC_FILE} {0} + set_instance_parameter_value gpio_0 {IP_MIGRATE_PORT_MAP_FILE} {altddio_bidir_port_map.csv} + set_instance_parameter_value gpio_0 {PIN_TYPE_GUI} {Output} + set_instance_parameter_value gpio_0 {SIZE} {1} + set_instance_parameter_value gpio_0 {gui_areset_mode} {None} + set_instance_parameter_value gpio_0 {gui_bus_hold} {0} + set_instance_parameter_value gpio_0 {gui_ddio_with_delay} {0} + set_instance_parameter_value gpio_0 {gui_diff_buff} {0} + set_instance_parameter_value gpio_0 {gui_enable_cke} {0} + set_instance_parameter_value gpio_0 {gui_enable_migratable_port_names} {0} + set_instance_parameter_value gpio_0 {gui_enable_termination_ports} {0} + set_instance_parameter_value gpio_0 {gui_hr_logic} {0} + set_instance_parameter_value gpio_0 {gui_io_reg_mode} {DDIO} + set_instance_parameter_value gpio_0 {gui_open_drain} {0} + set_instance_parameter_value gpio_0 {gui_pseudo_diff} {0} + set_instance_parameter_value gpio_0 {gui_separate_io_clks} {0} + set_instance_parameter_value gpio_0 {gui_sreset_mode} {None} + set_instance_parameter_value gpio_0 {gui_use_oe} {0} + set_instance_property gpio_0 AUTO_EXPORT true + + # add wirelevel expressions + + # preserve ports for debug + + # add the exports + set_interface_property ck EXPORT_OF gpio_0.ck + set_interface_property din EXPORT_OF gpio_0.din + set_interface_property pad_out EXPORT_OF gpio_0.pad_out + + # set values for exposed HDL parameters + + # set the the module properties + set_module_property BONUS_DATA { + + + + + +} + set_module_property FILE {oddr_intel.ip} + set_module_property GENERATION_ID {0x00000000} + set_module_property NAME {oddr_intel} + + # save the system + sync_sysinfo_parameters + save_system oddr_intel +} + +proc do_set_exported_interface_sysinfo_parameters {} { +} + +# create all the systems, from bottom up +do_create_oddr_intel + +# set system info parameters on exported interface, from bottom up +do_set_exported_interface_sysinfo_parameters diff --git a/corev_apu/altera/ip/test_mm_ccb_0.tcl b/corev_apu/altera/ip/test_mm_ccb_0.tcl new file mode 100644 index 0000000000..f92c2b5fed --- /dev/null +++ b/corev_apu/altera/ip/test_mm_ccb_0.tcl @@ -0,0 +1,72 @@ +# Quartus Pro License required to use this file +package require -exact qsys 24.1 + +# create the system "test_mm_ccb_0" +proc do_create_test_mm_ccb_0 {} { + # create the system + create_system test_mm_ccb_0 + set_project_property BOARD {default} + set_project_property DEVICE {AGFB014R24B2E2V} + set_project_property DEVICE_FAMILY {Agilex 7} + set_project_property HIDE_FROM_IP_CATALOG {false} + set_use_testbench_naming_pattern 0 {} + + # add HDL parameters + + # add the components + add_instance mm_ccb_0 mm_ccb 19.2.1 + set_instance_parameter_value mm_ccb_0 {ADDRESS_UNITS} {SYMBOLS} + set_instance_parameter_value mm_ccb_0 {ADDRESS_WIDTH} {27} + set_instance_parameter_value mm_ccb_0 {COMMAND_FIFO_DEPTH} {256} + set_instance_parameter_value mm_ccb_0 {DATA_WIDTH} {512} + set_instance_parameter_value mm_ccb_0 {MASTER_SYNC_DEPTH} {2} + set_instance_parameter_value mm_ccb_0 {MAX_BURST_SIZE} {128} + set_instance_parameter_value mm_ccb_0 {RESPONSE_FIFO_DEPTH} {256} + set_instance_parameter_value mm_ccb_0 {SLAVE_SYNC_DEPTH} {2} + set_instance_parameter_value mm_ccb_0 {SYMBOL_WIDTH} {8} + set_instance_parameter_value mm_ccb_0 {SYNC_RESET} {1} + set_instance_parameter_value mm_ccb_0 {USE_AUTO_ADDRESS_WIDTH} {0} + set_instance_property mm_ccb_0 AUTO_EXPORT true + + # add wirelevel expressions + + # preserve ports for debug + + # add the exports + set_interface_property m0_clk EXPORT_OF mm_ccb_0.m0_clk + set_interface_property m0_reset EXPORT_OF mm_ccb_0.m0_reset + set_interface_property s0_clk EXPORT_OF mm_ccb_0.s0_clk + set_interface_property s0_reset EXPORT_OF mm_ccb_0.s0_reset + set_interface_property s0 EXPORT_OF mm_ccb_0.s0 + set_interface_property m0 EXPORT_OF mm_ccb_0.m0 + + # set values for exposed HDL parameters + + # set the the module properties + set_module_property BONUS_DATA { + + + + + +} + set_module_property FILE {ip/test_mm_ccb_0.ip} + set_module_property GENERATION_ID {0x00000000} + set_module_property NAME {test_mm_ccb_0} + + # save the system + sync_sysinfo_parameters + save_system test_mm_ccb_0 +} + +proc do_set_exported_interface_sysinfo_parameters {} { + load_system test_mm_ccb_0.ip + set_exported_interface_sysinfo_parameter_value m0 address_width {10} + save_system test_mm_ccb_0.ip +} + +# create all the systems, from bottom up +do_create_test_mm_ccb_0 + +# set system info parameters on exported interface, from bottom up +do_set_exported_interface_sysinfo_parameters diff --git a/corev_apu/altera/ip/vJTAG.tcl b/corev_apu/altera/ip/vJTAG.tcl new file mode 100644 index 0000000000..d229c9590c --- /dev/null +++ b/corev_apu/altera/ip/vJTAG.tcl @@ -0,0 +1,58 @@ +# Quartus Pro License required to use this file +package require -exact qsys 24.1 + +# create the system "vJTAG" +proc do_create_vJTAG {} { + # create the system + create_system vJTAG + set_project_property BOARD {default} + set_project_property DEVICE {AGFB014R24B2E2V} + set_project_property DEVICE_FAMILY {Agilex 7} + set_project_property HIDE_FROM_IP_CATALOG {true} + set_use_testbench_naming_pattern 0 {} + + # add HDL parameters + + # add the components + add_instance virtual_jtag_0 altera_virtual_jtag 19.2.1 + set_instance_parameter_value virtual_jtag_0 {CREATE_PRIMITIVE_JTAG_STATE_SIGNAL_PORTS} {1} + set_instance_parameter_value virtual_jtag_0 {gui_use_auto_index} {1} + set_instance_parameter_value virtual_jtag_0 {sld_instance_index} {0} + set_instance_parameter_value virtual_jtag_0 {sld_ir_width} {10} + set_instance_property virtual_jtag_0 AUTO_EXPORT true + + # add wirelevel expressions + + # preserve ports for debug + + # add the exports + set_interface_property jtag EXPORT_OF virtual_jtag_0.jtag + set_interface_property tck EXPORT_OF virtual_jtag_0.tck + + # set values for exposed HDL parameters + + # set the the module properties + set_module_property BONUS_DATA { + + + + + +} + set_module_property FILE {vJTAG.ip} + set_module_property GENERATION_ID {0x00000000} + set_module_property NAME {vJTAG} + + # save the system + sync_sysinfo_parameters + save_system vJTAG +} + +proc do_set_exported_interface_sysinfo_parameters {} { +} + +# create all the systems, from bottom up +do_create_vJTAG + +# set system info parameters on exported interface, from bottom up +do_set_exported_interface_sysinfo_parameters diff --git a/corev_apu/altera/ip_files.csv b/corev_apu/altera/ip_files.csv new file mode 100644 index 0000000000..9bdb7ff77e --- /dev/null +++ b/corev_apu/altera/ip_files.csv @@ -0,0 +1,9 @@ +./test_mm_ccb_0.ip +./io_pll.ip +./iobuf.ip +./oddr_intel.ip +./iddr_intel.ip +./ed_synth_emif_fm_0.ip +./emif_cal.ip +./vJTAG.ip +./cva6_intel_jtag_uart_0.ip diff --git a/corev_apu/altera/loc_constraints.csv b/corev_apu/altera/loc_constraints.csv new file mode 100644 index 0000000000..0ac21bf1c0 --- /dev/null +++ b/corev_apu/altera/loc_constraints.csv @@ -0,0 +1,139 @@ +PIN_A24 -to cpu_resetn +PIN_CU24 -to pll_ref_clk_p +PIN_C30 -to led[0] +PIN_A30 -to led[1] +PIN_D31 -to led[2] +PIN_B31 -to led[3] +PIN_L40 -to clk_ddr4_ch0_p +PIN_F33 -to ddr4_dq[0] +PIN_H33 -to ddr4_dq[1] +PIN_G34 -to ddr4_dq[2] +PIN_J34 -to ddr4_dq[3] +PIN_J38 -to ddr4_dq[4] +PIN_G38 -to ddr4_dq[5] +PIN_F37 -to ddr4_dq[6] +PIN_H37 -to ddr4_dq[7] +PIN_B33 -to ddr4_dq[8] +PIN_D33 -to ddr4_dq[9] +PIN_A34 -to ddr4_dq[10] +PIN_C34 -to ddr4_dq[11] +PIN_D37 -to ddr4_dq[12] +PIN_A38 -to ddr4_dq[13] +PIN_B37 -to ddr4_dq[14] +PIN_C38 -to ddr4_dq[15] +PIN_A40 -to ddr4_dq[16] +PIN_C40 -to ddr4_dq[17] +PIN_B41 -to ddr4_dq[18] +PIN_D41 -to ddr4_dq[19] +PIN_D45 -to ddr4_dq[20] +PIN_B45 -to ddr4_dq[21] +PIN_A44 -to ddr4_dq[22] +PIN_C44 -to ddr4_dq[23] +PIN_G40 -to ddr4_dq[24] +PIN_J40 -to ddr4_dq[25] +PIN_F41 -to ddr4_dq[26] +PIN_H41 -to ddr4_dq[27] +PIN_J44 -to ddr4_dq[28] +PIN_H45 -to ddr4_dq[29] +PIN_G44 -to ddr4_dq[30] +PIN_F45 -to ddr4_dq[31] +PIN_G48 -to ddr4_dq[32] +PIN_F47 -to ddr4_dq[33] +PIN_J48 -to ddr4_dq[34] +PIN_H47 -to ddr4_dq[35] +PIN_F51 -to ddr4_dq[36] +PIN_H51 -to ddr4_dq[37] +PIN_G52 -to ddr4_dq[38] +PIN_J52 -to ddr4_dq[39] +PIN_F55 -to ddr4_dq[40] +PIN_G54 -to ddr4_dq[41] +PIN_H55 -to ddr4_dq[42] +PIN_J54 -to ddr4_dq[43] +PIN_J58 -to ddr4_dq[44] +PIN_F59 -to ddr4_dq[45] +PIN_G58 -to ddr4_dq[46] +PIN_H59 -to ddr4_dq[47] +PIN_B55 -to ddr4_dq[48] +PIN_A54 -to ddr4_dq[49] +PIN_D55 -to ddr4_dq[50] +PIN_C54 -to ddr4_dq[51] +PIN_D59 -to ddr4_dq[52] +PIN_C58 -to ddr4_dq[53] +PIN_F61 -to ddr4_dq[54] +PIN_H61 -to ddr4_dq[55] +PIN_V55 -to ddr4_dq[56] +PIN_T55 -to ddr4_dq[57] +PIN_W54 -to ddr4_dq[58] +PIN_U54 -to ddr4_dq[59] +PIN_W58 -to ddr4_dq[60] +PIN_T59 -to ddr4_dq[61] +PIN_U58 -to ddr4_dq[62] +PIN_V59 -to ddr4_dq[63] +PIN_A48 -to ddr4_dq[64] +PIN_B47 -to ddr4_dq[65] +PIN_C48 -to ddr4_dq[66] +PIN_D47 -to ddr4_dq[67] +PIN_C52 -to ddr4_dq[68] +PIN_D51 -to ddr4_dq[69] +PIN_B51 -to ddr4_dq[70] +PIN_A52 -to ddr4_dq[71] +PIN_G36 -to ddr4_dbi_n[0] +PIN_A36 -to ddr4_dbi_n[1] +PIN_B43 -to ddr4_dbi_n[2] +PIN_F43 -to ddr4_dbi_n[3] +PIN_G50 -to ddr4_dbi_n[4] +PIN_F57 -to ddr4_dbi_n[5] +PIN_B57 -to ddr4_dbi_n[6] +PIN_T57 -to ddr4_dbi_n[7] +PIN_A50 -to ddr4_dbi_n[8] +PIN_H35 -to ddr4_dqs_n[0] +PIN_F35 -to ddr4_dqs_p[0] +PIN_D35 -to ddr4_dqs_n[1] +PIN_B35 -to ddr4_dqs_p[1] +PIN_C42 -to ddr4_dqs_n[2] +PIN_A42 -to ddr4_dqs_p[2] +PIN_J42 -to ddr4_dqs_n[3] +PIN_G42 -to ddr4_dqs_p[3] +PIN_H49 -to ddr4_dqs_n[4] +PIN_F49 -to ddr4_dqs_p[4] +PIN_J56 -to ddr4_dqs_n[5] +PIN_G56 -to ddr4_dqs_p[5] +PIN_C56 -to ddr4_dqs_n[6] +PIN_A56 -to ddr4_dqs_p[6] +PIN_W56 -to ddr4_dqs_n[7] +PIN_U56 -to ddr4_dqs_p[7] +PIN_D49 -to ddr4_dqs_n[8] +PIN_B49 -to ddr4_dqs_p[8] +PIN_P37 -to ddr4_ck_n[0] +PIN_M37 -to ddr4_ck_p[0] +PIN_P43 -to ddr4_a[16] +PIN_M43 -to ddr4_a[15] +PIN_N42 -to ddr4_a[14] +PIN_L42 -to ddr4_a[13] +PIN_P41 -to ddr4_a[12] +PIN_W38 -to ddr4_a[11] +PIN_U38 -to ddr4_a[10] +PIN_V37 -to ddr4_a[9] +PIN_T37 -to ddr4_a[8] +PIN_W36 -to ddr4_a[7] +PIN_U36 -to ddr4_a[6] +PIN_V35 -to ddr4_a[5] +PIN_T35 -to ddr4_a[4] +PIN_W34 -to ddr4_a[3] +PIN_U34 -to ddr4_a[2] +PIN_V33 -to ddr4_a[1] +PIN_T33 -to ddr4_a[0] +PIN_L34 -to ddr4_cs_n[0] +PIN_P45 -to ddr4_bg[0] +PIN_M33 -to ddr4_bg[1] +PIN_N44 -to ddr4_ba[0] +PIN_M45 -to ddr4_ba[1] +PIN_L36 -to ddr4_cke[0] +PIN_M35 -to ddr4_odt[0] +PIN_U44 -to ddr4_alert_n +PIN_M41 -to oct_rzqin +PIN_N38 -to ddr4_par +PIN_N34 -to ddr4_act_n +PIN_P33 -to ddr4_reset_n +PIN_AA6 -to tx +PIN_F1 -to rx diff --git a/corev_apu/altera/search_paths.csv b/corev_apu/altera/search_paths.csv new file mode 100644 index 0000000000..1d88707ec8 --- /dev/null +++ b/corev_apu/altera/search_paths.csv @@ -0,0 +1,9 @@ +"../fpga/src/apb/include" +"../fpga/src" +"../fpga/" +"../../vendor/pulp-platform/common_cells/include" +"../../vendor/pulp-platform/axi/include" +"../../core/cache_subsystem/hpdcache/rtl/include" +"../../core/include" +"../register_interface/include" +"../" \ No newline at end of file diff --git a/corev_apu/altera/settings.csv b/corev_apu/altera/settings.csv new file mode 100644 index 0000000000..b069925db4 --- /dev/null +++ b/corev_apu/altera/settings.csv @@ -0,0 +1,45 @@ +TOP_LEVEL_ENTITY cva6_altera +ORIGINAL_QUARTUS_VERSION 24.1.0 +PROJECT_CREATION_TIME_DATE "14:07:44 JUNE 03, 2024" +LAST_QUARTUS_VERSION "24.1.0 Pro Edition" +PROJECT_OUTPUT_DIRECTORY output_files +MIN_CORE_JUNCTION_TEMP 0 +MAX_CORE_JUNCTION_TEMP 100 +DEVICE AGFB014R24B2E2V +FAMILY "Agilex 7" +ERROR_CHECK_FREQUENCY_DIVISOR 256 +EDA_SIMULATION_TOOL "QuestaSim (Verilog)" +EDA_TIME_SCALE "1 ps" -section_id eda_simulation +EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation +STRATIXV_CONFIGURATION_SCHEME "ACTIVE SERIAL X4" +USE_CONFIGURATION_DEVICE ON +GENERATE_PR_RBF_FILE ON +ENABLE_ED_CRC_CHECK ON +MINIMUM_SEU_INTERVAL 0 +PWRMGT_SLAVE_DEVICE_TYPE ED8401 +PWRMGT_SLAVE_DEVICE0_ADDRESS 47 +PWRMGT_SLAVE_DEVICE1_ADDRESS 00 +PWRMGT_SLAVE_DEVICE2_ADDRESS 00 +ACTIVE_SERIAL_CLOCK AS_FREQ_100MHZ +USE_PWRMGT_SCL SDM_IO14 +USE_PWRMGT_SDA SDM_IO11 +USE_CONF_DONE SDM_IO16 +AUTO_RESTART_CONFIGURATION OFF +USE_CVP_CONFDONE SDM_IO10 +DEVICE_INITIALIZATION_CLOCK OSC_CLK_1_125MHZ +PWRMGT_PAGE_COMMAND_ENABLE OFF +PWRMGT_VOLTAGE_OUTPUT_FORMAT "LINEAR FORMAT" +PWRMGT_LINEAR_FORMAT_N "-13" +POWER_APPLY_THERMAL_MARGIN ADDITIONAL +USE_INIT_DONE SDM_IO0 +BOARD default +OPTIMIZATION_MODE "OPTIMIZE NETLIST FOR ROUTABILITY" +ALM_REGISTER_PACKING_EFFORT "LOW" +ADVANCED_PHYSICAL_SYNTHESIS "ON" +PLACEMENT_EFFORT_MULTIPLIER 50 +ROUTER_TIMING_OPTIMIZATION_LEVEL "MAXIMUM" +FINAL_PLACEMENT_OPTIMIZATION "AUTOMATICALLY" +FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION ALWAYS +GLOBAL_PLACEMENT_EFFORT "MAXIMUM EFFORT" +QII_AUTO_PACKED_REGISTERS SPARSE +OPTIMIZATION_TECHNIQUE SPEED diff --git a/corev_apu/fpga/src/agilex7.svh b/corev_apu/fpga/src/agilex7.svh new file mode 100644 index 0000000000..467ddaf3fe --- /dev/null +++ b/corev_apu/fpga/src/agilex7.svh @@ -0,0 +1,21 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Description: Set global FPGA degines +// Author: Florian Zaruba + +`define AGILEX7 +// include KINTEX7 specific code (relevant for KC705, GENESYSII,...) +`define KINTEX7 + +`define ARIANE_DATA_WIDTH 64 + +// Instantiate protocl checker +// `define PROTOCOL_CHECKER diff --git a/corev_apu/fpga/src/bootrom/Makefile b/corev_apu/fpga/src/bootrom/Makefile index 35c2b872ea..81679948f2 100644 --- a/corev_apu/fpga/src/bootrom/Makefile +++ b/corev_apu/fpga/src/bootrom/Makefile @@ -20,7 +20,7 @@ endif CC = $(RISCV)/bin/${CROSSCOMPILE}gcc OBJCOPY = $(RISCV)/bin/$(CROSSCOMPILE)objcopy SED = sed -PLATFORM_DEFINES = -DCLOCK_FREQUENCY=$(CLOCK_FREQUENCY) -DUART_BITRATE=$(UART_BITRATE) +PLATFORM_DEFINES = -DCLOCK_FREQUENCY=$(CLOCK_FREQUENCY) -DUART_BITRATE=$(UART_BITRATE) -D$(PLATFORM) ifeq ($(XLEN), 64) CFLAGS = $(PLATFORM_DEFINES) -Os -ggdb -march=rv64im_zicsr -mabi=lp64 -Wall -mcmodel=medany -mexplicit-relocs -ffreestanding @@ -56,6 +56,7 @@ endif $(MAIN): $(DTB) $(OBJS_C) $(OBJS_S) linker.lds $(CC) $(CFLAGS) $(LDFLAGS) $(INCLUDES) -Tlinker.lds $(OBJS_S) $(OBJS_C) -o $(MAIN) @echo "LD >= $(MAIN)" + @echo "BOOTROM PLATFORM IS : $(PLATFORM)" %.img: %.bin dd if=$< of=$@ bs=128 diff --git a/corev_apu/fpga/src/bootrom/src/main.c b/corev_apu/fpga/src/bootrom/src/main.c index f62485ba24..fe2f744ec8 100644 --- a/corev_apu/fpga/src/bootrom/src/main.c +++ b/corev_apu/fpga/src/bootrom/src/main.c @@ -48,7 +48,9 @@ int main() uint8_t uart_res = 0; uintptr_t start; - init_uart(CLOCK_FREQUENCY, UART_BITRATE); + #ifndef PLAT_AGILEX + init_uart(CLOCK_FREQUENCY, UART_BITRATE); //not needed in intel setup as UART IP is already configured via HW + #endif print_uart("Hello World!\r\n"); // See if we should enter update mode @@ -70,9 +72,12 @@ int main() res = update((uint8_t *)0x80000000UL); } else { print_uart(" booting!\r\n"); - res = gpt_find_boot_partition((uint8_t *)0x80000000UL, 2 * 16384); + #ifndef PLAT_AGILEX + res = gpt_find_boot_partition((uint8_t *)0x80000000UL, 2 * 16384); // linux boot not yet supported for altera + #endif } + #ifndef PLAT_AGILEX // linux boot not yet supported for altera if (res == 0) { // jump to the address @@ -81,6 +86,7 @@ int main() "la a1, _dtb;" "jr s0"); } + #endif while (1) { diff --git a/corev_apu/fpga/src/bootrom/src/uart.c b/corev_apu/fpga/src/bootrom/src/uart.c index a400b87ac9..79a4ee8b78 100644 --- a/corev_apu/fpga/src/bootrom/src/uart.c +++ b/corev_apu/fpga/src/bootrom/src/uart.c @@ -20,15 +20,27 @@ int is_transmit_empty() return read_reg_u8(UART_LINE_STATUS) & 0x20; } +char is_transmit_empty_altera() +{ + return read_reg_u8(UART_THR+6); +} + int is_receive_empty() { - return !(read_reg_u8(UART_LINE_STATUS) & 0x1); + #ifndef PLAT_AGILEX + return !(read_reg_u8(UART_LINE_STATUS) & 0x1); + #else + return !(read_reg_u8(UART_THR+1) & 0x8); + #endif } void write_serial(char a) { - while (is_transmit_empty() == 0) {}; - + #ifndef PLAT_AGILEX + while (is_transmit_empty() == 0) {}; + #else + while (is_transmit_empty_altera() < 8) {}; + #endif write_reg_u8(UART_THR, a); } diff --git a/docs/design/design-manual/source/CVX_Interface_Coprocessor.adoc b/docs/design/design-manual/source/CVX_Interface_Coprocessor.adoc index 4290a1372e..cfdfdf8607 100644 --- a/docs/design/design-manual/source/CVX_Interface_Coprocessor.adoc +++ b/docs/design/design-manual/source/CVX_Interface_Coprocessor.adoc @@ -61,57 +61,71 @@ Supported Parameters The following table presents CVXIF parameters supported by CVA6. -[cols=",,",options="header",] +[cols=",a,a",options="header",] |============================================= |Signal |Value |Description -|*X_NUM_RS* |int: 2 or 3 (configurable) a| +|*X_NUM_RS* | +int: 2 or 3 (configurable) + + +* CV32A60X: 2 +* CV32A65X: 2 +| [verse] -- Number of register file read ports that can be used by the eXtension interface -- - | -|*X_ID_WIDTH* |int: 3 a| +|*X_ID_WIDTH* | +int: 1 to 32 + + +* CV32A60X: 2 +* CV32A65X: 3 +| [verse] -- Identification width for the eXtension interface -- - | -|*X_MEM_WIDTH* |n/a (feature not supported) a| +|*X_MEM_WIDTH* |n/a (feature not supported) | [verse] -- Memory access width for loads/stores via the eXtension interface -- - | -|*X_RFR_WIDTH* |int: `XLEN` (32 or 64) a| +|*X_RFR_WIDTH* | +int: `XLEN` (32 or 64) + + +* CV32A60X: 32 +* CV32A65X: 32 +| [verse] -- Register file read access width for the eXtension interface -- - | -|*X_RFW_WIDTH* |int: `XLEN` (32 or 64) a| +|*X_RFW_WIDTH* | +int: `XLEN` (32 or 64) + + +* CV32A60X: 32 +* CV32A65X: 32 +| [verse] -- Register file write access width for the eXtension interface -- - | -|*X_MISA* |logic[31:0]: 0x0000_0000 a| +|*X_MISA* |logic[31:0]: 0x0000_0000 | [verse] -- MISA extensions implemented on the eXtension interface -- - | |============================================= [[cv-x-if-enabling]] diff --git a/docs/requirements.txt b/docs/requirements.txt index a77aa8cf7d..d9cbc647a1 100644 --- a/docs/requirements.txt +++ b/docs/requirements.txt @@ -3,3 +3,9 @@ sphinx-rtd-theme recommonmark sphinxcontrib-svg2pdfconverter sphinx_github_changelog + +# for gen_from_riscv_config +mako +mdutils +pyyaml +rstcloth diff --git a/docs/riscv-isa/riscv-isa-manual b/docs/riscv-isa/riscv-isa-manual index 2c07aa2bcc..4f277ff8ea 160000 --- a/docs/riscv-isa/riscv-isa-manual +++ b/docs/riscv-isa/riscv-isa-manual @@ -1 +1 @@ -Subproject commit 2c07aa2bcc02fd5fb2e53e42a32dc62a3eb0aa62 +Subproject commit 4f277ff8ea8c0fc9394dfccd1da0ace34b1aef68 diff --git a/docs/riscv-isa/src/colophon.adoc b/docs/riscv-isa/src/colophon.adoc index d05ee78be3..d5d1e07c45 100644 --- a/docs/riscv-isa/src/colophon.adoc +++ b/docs/riscv-isa/src/colophon.adoc @@ -7,7 +7,7 @@ This document describes the RISC-V unprivileged architecture tailored for OpenHW Group {ohg-config}. -[.big]*_Preface to Document Version 20241017_* +[.big]*_Preface to Document Version 20241101_* This document describes the RISC-V unprivileged architecture. diff --git a/docs/riscv-isa/src/counters.adoc b/docs/riscv-isa/src/counters.adoc index ec0676006e..7a3baa1ec5 100644 --- a/docs/riscv-isa/src/counters.adoc +++ b/docs/riscv-isa/src/counters.adoc @@ -9,6 +9,7 @@ divided between the "Zicntr" and "Zihpm" extensions. === "Zicntr" Extension for Base Counters and Timers +ifeval::[{RVZicntr} == true] The Zicntr standard extension comprises the first three of these counters (CYCLE, TIME, and INSTRET), which have dedicated functions (cycle count, real-time clock, and instructions retired, respectively). @@ -171,6 +172,11 @@ reading its upper and lower halves. rdcycle x2 rdcycleh x4 bne x3, x4, again +endif::[] + +ifeval::[{RVZicntr} == false] +{ohg-config}: This extension is not supported. +endif::[] === "Zihpm" Extension for Hardware Performance Counters diff --git a/docs/riscv-isa/src/machine.adoc b/docs/riscv-isa/src/machine.adoc index ceb8e904a0..1f647106c7 100644 --- a/docs/riscv-isa/src/machine.adoc +++ b/docs/riscv-isa/src/machine.adoc @@ -226,10 +226,17 @@ supervisor modes respectively. The "X" bit will be set if there are any non-standard extensions. -When "B" bit is 1, the implementation supports the instructions provided by the -Zba, Zbb, and Zbs extensions. When "B" bit is 0, it indicates that the +When the "B" bit is 1, the implementation supports the instructions provided by the +Zba, Zbb, and Zbs extensions. When the "B" bit is 0, it indicates that the implementation may not support one or more of the Zba, Zbb, or Zbs extensions. +When the "M" bit is 1, the implementation supports all multiply and +division instructions defined by the M extension. When the "M" bit +is 0, it indicates that the implementation may not support those +instructions. However if the Zmmul extension is supported then +the multiply instructions it specifies are supported irrespective +of the value of the "M" bit. + ifeval::[{note} == true] [NOTE] ==== @@ -1554,7 +1561,7 @@ additional microarchitectural bits might be maintained in the extension to further reduce context save and restore overhead. The SD bit is read-only and is set when either the FS, VS, or XS bits -encode a Dirty state (i.e., SD=((FS==11) OR (XS==11) OR (VS==11))). This +encode a Dirty state (i.e., `SD=(FS==0b11 OR XS==0b11 OR VS==0b11)`). This allows privileged code to quickly determine when no additional context save is required beyond the integer register set and `pc`. @@ -3865,7 +3872,9 @@ and I/O regions may be accessed with either _relaxed_ or _strong_ ordering. Accesses to an I/O region with relaxed ordering are generally observed by other harts and bus mastering devices in a manner similar to the ordering of accesses to an RVWMO memory region, as discussed in -Section A.4.2 in Volume I of this specification. By contrast, accesses +the I/O Ordering section in the RVWMO Explanatory Material appendix +of Volume I of this specification. +By contrast, accesses to an I/O region with strong ordering are generally observed by other harts and bus mastering devices in program order. diff --git a/docs/riscv-isa/src/mm-formal.adoc b/docs/riscv-isa/src/mm-formal.adoc new file mode 100644 index 0000000000..200edb8feb --- /dev/null +++ b/docs/riscv-isa/src/mm-formal.adoc @@ -0,0 +1,7 @@ +[appendix] +== Formal Memory Model Specifications, Version 0.1 +[[mm-formal]] + +ifeval::["{ohg-config}" == "CV32A65X"] +{ohg-config}: No RVWMO memory model. +endif::[] diff --git a/docs/riscv-isa/src/priv-preface.adoc b/docs/riscv-isa/src/priv-preface.adoc index c971911fb3..38dc7ce812 100644 --- a/docs/riscv-isa/src/priv-preface.adoc +++ b/docs/riscv-isa/src/priv-preface.adoc @@ -6,6 +6,98 @@ This document describes the RISC-V privileged architecture tailored for OpenHW Group {ohg-config}. +[.big]*_Preface to Version 20241101_* + +This document describes the RISC-V privileged architecture. This +release, version 20241101, contains the following versions of the RISC-V ISA +modules: + +[%autowidth,float="center",align="center",cols="^,<,^",options="header",] +|=== +|Module |Version |Status +|_Machine ISA_ + +*Smstateen Extension* + +*Smcsrind/Sscsrind Extension* + +*Smepmp Extension* + +*Smcntrpmf Extension* + +*Smrnmi Extension* + +*Smcdeleg Extension* + +*Smdbltrp Extension* + +_Supervisor ISA_ + +*Svade Extension* + +*Svnapot Extension* + +*Svpbmt Extension* + +*Svinval Extension* + +*Svadu Extension* + +*Sstc Extension* + +*Sscofpmf Extension* + +*Ssdbltrp Extension* + +*Ssqosid Extension* + +*Hypervisor ISA* + +*Shlcofideleg Extension* + +*Svvptc Extension* + +|_1.14_ + +*1.0* + +*1.0* + +*1.0* + +*1.0* + +*1.0* + +*1.0* + +*1.0* + +_1.14_ + +*1.0* + +*1.0* + +*1.0* + +*1.0* + +*1.0* + +*1.0* + +*1.0* + +*1.0* + +*1.0* + +*1.0* + +*1.0* + +*1.0* + +|_Draft_ + +*Ratified* + +*Ratified* + +*Ratified* + +*Ratified* + +*Ratified* + +*Ratified* + +*Ratified* + +_Draft_ + +*Ratified* + +*Ratified* + +*Ratified* + +*Ratified* + +*Ratified* + +*Ratified* + +*Ratified* + +*Ratified* + +*Ratified* + +*Ratified* + +*Ratified* + +*Ratified* +|=== + +The following changes have been made since version 1.13 of the Machine and +Supervisor ISAs, which, while not strictly backwards compatible, are not +anticipated to cause software portability problems in practice: + +* (None yet) + +Additionally, the following compatible changes have been +made to the Machine and Supervisor ISAs since version 1.13: + +* Defined the `mstateen0` P1P14 field. + +Finally, the following clarifications and document improvements have been made +since the last document release: + +* (None yet) + [.big]*_Preface to Version 20241017_* This document describes the RISC-V privileged architecture. This diff --git a/docs/riscv-isa/src/riscv-privileged.adoc b/docs/riscv-isa/src/riscv-privileged.adoc index bc8d53217e..07b28a33be 100644 --- a/docs/riscv-isa/src/riscv-privileged.adoc +++ b/docs/riscv-isa/src/riscv-privileged.adoc @@ -4,8 +4,8 @@ include::config.adoc[] = The RISC-V Instruction Set Manual for {ohg-config}: Volume II: Privileged Architecture include::../docs-resources/global-config.adoc[] :description: Volume II - Privileged Architecture -:revnumber: 20241017 -:revremark: This document is in Ratified state. +:revnumber: 20241101 +//:revremark: This document is in Ratified state. //development: assume everything can change //stable: assume everything could change //frozen: of you implement this version you assume the risk that something might change because of the public review cycle but we expect little to no change. @@ -22,7 +22,7 @@ include::../docs-resources/global-config.adoc[] // Settings: :experimental: :reproducible: -:imagesoutdir: images +:imagesoutdir: {docdir}/../build/images-out :bibtex-file: src/resources/riscv-spec.bib :bibtex-order: alphabetical :bibtex-style: apa @@ -100,6 +100,7 @@ include::smcntrpmf.adoc[] include::rnmi.adoc[] include::smcdeleg.adoc[] include::smdbltrp.adoc[] +include::smctr.adoc[] include::supervisor.adoc[] include::sstc.adoc[] include::sscofpmf.adoc[] diff --git a/docs/riscv-isa/src/riscv-unprivileged.adoc b/docs/riscv-isa/src/riscv-unprivileged.adoc index c9c5bb8861..01e7c37708 100644 --- a/docs/riscv-isa/src/riscv-unprivileged.adoc +++ b/docs/riscv-isa/src/riscv-unprivileged.adoc @@ -4,7 +4,7 @@ include::config.adoc[] = The RISC-V Instruction Set Manual for {ohg-config}: Volume I - Unprivileged Architecture include::../docs-resources/global-config.adoc[] :description: Unprivileged Architecture -:revnumber: 20241017 +:revnumber: 20241101 //:revremark: Pre-release version :colophon: :preface-title: Preamble @@ -19,7 +19,7 @@ include::../docs-resources/global-config.adoc[] // Settings: :experimental: :reproducible: -:imagesoutdir: images +:imagesoutdir: {docdir}/../build/images-out :bibtex-file: src/resources/riscv-spec.bib :bibtex-order: alphabetical :bibtex-style: apa diff --git a/docs/riscv-isa/src/rv64.adoc b/docs/riscv-isa/src/rv64.adoc index 38c52e66c7..06d844396c 100644 --- a/docs/riscv-isa/src/rv64.adoc +++ b/docs/riscv-isa/src/rv64.adoc @@ -205,6 +205,10 @@ no standard HINTs will ever be defined in this subspace. (_rs2_=_x4_) NTL.S1 + (_rs2_=_x5_) NTL.ALL +|SLLI |_rd_=`x0`, _rs1_=`x0`, _shamt_=31 |1|Semihosting entry marker + +|SRAI |_rd_=`x0`, _rs1_=`x0`, _shamt_=7 |1|Semihosting exit marker + |SUB |_rd_=_x0_ |latexmath:[$2^{10}$] .16+.^| _Designated for future standard use_ |AND |_rd_=_x0_ |latexmath:[$2^{10}$] @@ -243,11 +247,11 @@ no standard HINTs will ever be defined in this subspace. |SLTIU |_rd_=_x0_ |latexmath:[$2^{17}$] -|SLLI |_rd_=_x0_ |latexmath:[$2^{11}$] +|SLLI |_rd_=`x0`, and either _rs1_≠``x0`` or _shamt_≠31 |latexmath:[$2^{11}-1$] -|SRLI |_rd_=_x0_ |latexmath:[$2^{11}$] +|SRLI |_rd_=`x0` |latexmath:[$2^{11}$] -|SRAI |_rd_=_x0_ |latexmath:[$2^{11}$] +|SRAI |_rd_=`x0`, and either _rs1_≠``x0`` or _shamt_≠7 |latexmath:[$2^{11}-1$] |SLLIW |_rd_=_x0_ |latexmath:[$2^{10}$] diff --git a/docs/riscv-isa/src/scalar-crypto.adoc b/docs/riscv-isa/src/scalar-crypto.adoc index a62f39cac9..32f1bd4633 100644 --- a/docs/riscv-isa/src/scalar-crypto.adoc +++ b/docs/riscv-isa/src/scalar-crypto.adoc @@ -1,4 +1,4 @@ -[[scalar-crypto]] +[[crypto_scalar_instructions]] == Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 ifeval::[{RVZk} == false] diff --git a/docs/riscv-isa/src/smctr.adoc b/docs/riscv-isa/src/smctr.adoc new file mode 100644 index 0000000000..36407608d3 --- /dev/null +++ b/docs/riscv-isa/src/smctr.adoc @@ -0,0 +1,7 @@ +[[smctr]] + +== "Smctr" Control Transfer Records Extension, Version 1.0 + +ifeval::[{RVZsmctr} == false] +{ohg-config}: This extension is not supported. +endif::[] diff --git a/docs/riscv-isa/src/supervisor.adoc b/docs/riscv-isa/src/supervisor.adoc index 697cbf541f..cbb545405c 100644 --- a/docs/riscv-isa/src/supervisor.adoc +++ b/docs/riscv-isa/src/supervisor.adoc @@ -45,7 +45,7 @@ supervisor-level CSR descriptions. endif::[] [[sstatus]] -==== Supervisor Status (`sstatus`) Register +==== Supervisor Status (`sstatus`) Register ifdef::archi-default[] The `sstatus` register is an SXLEN-bit read/write register formatted as @@ -360,7 +360,7 @@ ifndef::archi-default,RVZssdbltrp-true[] SDT field is read-only 0. endif::[] -==== Supervisor Trap Vector Base Address (`stvec`) Register +==== Supervisor Trap Vector Base Address (`stvec`) Register The `stvec` register is an SXLEN-bit read/write register that holds trap vector configuration, consisting of a vector base address (BASE) and a @@ -382,7 +382,7 @@ field. |Value |Name |Description |0 + 1 + -≥2 +≥2 |Direct + Vectored |All exceptions set `pc` to BASE. + @@ -401,7 +401,7 @@ supervisor-mode timer interrupt (see <>) causes the `pc` to be set to BASE+`0x14`. Setting MODE=Vectored may impose a stricter alignment constraint on BASE. -==== Supervisor Interrupt (`sip` and `sie`) Registers +==== Supervisor Interrupt (`sip` and `sie`) Registers The `sip` register is an SXLEN-bit read/write register containing information on pending interrupts, while `sie` is the corresponding @@ -528,7 +528,7 @@ the counter values. The implementation must provide a facility for scheduling timer interrupts in terms of the real-time counter, `time`. -==== Counter-Enable (`scounteren`) Register +==== Counter-Enable (`scounteren`) Register .Counter-enable (`scounteren`) register include::images/bytefield/scounteren.edn[] @@ -560,13 +560,15 @@ access a counter if the corresponding bits in `scounteren` and ==== endif::[] -==== Supervisor Scratch (`sscratch`) Register +==== Supervisor Scratch (`sscratch`) Register The `sscratch` CSR is an SXLEN-bit read/write register, dedicated for use by the supervisor. Typically, `sscratch` is used to hold a pointer to the hart-local supervisor context while the hart is executing -user code. At the beginning of a trap handler, `sscratch` is swapped -with a user register to provide an initial working register. +user code. +At the beginning of a trap handler, software normally uses a CSRRW +instruction to swap `sscratch` with an integer register to obtain an +initial working register. .Supervisor Scratch Register include::images/bytefield/sscratch.edn[] @@ -600,7 +602,7 @@ though it may be explicitly written by software. include::images/bytefield/epcreg.edn[] [[scause]] -==== Supervisor Cause (`scause`) Register +==== Supervisor Cause (`scause`) Register The `scause` CSR is an SXLEN-bit read-write register formatted as shown in <>. When a trap is taken into @@ -654,7 +656,7 @@ Supervisor external interrupt + _Reserved_ + Counter-overflow interrupt + _Reserved_ + -_Designated for platform use_ +_Designated for platform use_ |0 + 0 + @@ -721,7 +723,7 @@ _Reserved_ + _Designated for custom use_ + _Reserved_ + _Designated for custom use_ + -_Reserved_ +_Reserved_ |=== ==== Supervisor Trap Value (`stval`) Register @@ -795,7 +797,7 @@ ifndef::archi-default,MTvalEn-true[] endif::[] [[sec:senvcfg]] -==== Supervisor Environment Configuration (`senvcfg`) Register +==== Supervisor Environment Configuration (`senvcfg`) Register The `senvcfg` CSR is an SXLEN-bit read/write register, formatted as shown in <>, that controls certain @@ -1736,14 +1738,24 @@ A virtual address _va_ is translated into a physical address _pa_ as follows: . Let _a_ be ``satp``.__ppn__×PAGESIZE, and let __i__=LEVELS-1. (For Sv32, PAGESIZE=2^12^ and LEVELS=2.) The `satp` register must be _active_, i.e., the effective privilege mode must be S-mode or U-mode. + . Let _pte_ be the value of the PTE at address __a__+__va__.__vpn__[__i__]×PTESIZE. (For Sv32, PTESIZE=4.) If accessing _pte_ violates a PMA or PMP check, raise an access-fault exception corresponding to the original access type. + . If _pte_._v_=0, or if _pte_._r_=0 and _pte_._w_=1, or if any bits or encodings that are reserved for future standard use are set within _pte_, stop and raise a page-fault exception corresponding to the original access type. + . Otherwise, the PTE is valid. If __pte__.__r__=1 or __pte__.__x__=1, go to step 5. Otherwise, this PTE is a pointer to the next level of the page table. Let __i=i__-1. If __i__<0, stop and raise a page-fault exception corresponding to the original access type. Otherwise, let __a__=__pte__.__ppn__×PAGESIZE and go to step 2. -. A leaf PTE has been found. Determine if the requested memory access is -allowed by the _pte_._r_, _pte_._w_, _pte_._x_, and _pte_._u_ bits, given the current privilege mode and the value of the SUM and MXR fields of the `mstatus` register. If not, stop and raise a page-fault exception corresponding to the original access type. -. If _i>0_ and _pte_._ppn_[__i__-1:0] ≠ 0, this is a misaligned superpage; stop and raise a page-fault exception corresponding to the original access type. + +. A leaf PTE has been reached. If _i>0_ and _pte_._ppn_[__i__-1:0] ≠ 0, this is a misaligned superpage; stop and raise a page-fault exception corresponding to the original access type. + +. Determine if the requested memory access is allowed by the _pte_._u_ bit, given the current privilege mode and the value of the SUM and MXR fields of the *mstatus* register. If not, stop and raise a page-fault exception corresponding to the original access type. + +. Determine if the requested memory access is allowed by the _pte_._r_, _pte_._w_, and _pte_._x_ bits, given the Shadow Stack Memory Protection rules. If not, stop and raise an access-fault exception. + +. Determine if the requested memory access is allowed by the _pte_._r_, _pte_._w_, and _pte_._x_ bits. If not, stop and raise a page-fault exception corresponding to the original access type. + . If _pte_._a_=0, or if the original memory access is a store and _pte_._d_=0: + * If the Svade extension is implemented, stop and raise a page-fault exception corresponding to the original access type. * If a store to _pte_ would violate a PMA or PMP check, raise an access-fault exception corresponding to the original access @@ -1753,6 +1765,7 @@ type. ** If the values match, set _pte_._a_ to 1 and, if the original memory access is a store, also set _pte_._d_ to 1. ** If the comparison fails, return to step 2. + . The translation is successful. The translated physical address is given as follows: * _pa.pgoff_ = _va.pgoff_. @@ -2224,7 +2237,7 @@ __vpn__[__i__][__pte__.__napot_bits__-1:0]. If the encoding in _pte_ is reserved <>, then a page-fault exception must be raised. * Implicit reads of NAPOT page table entries may create address-translation cache entries mapping -_a_ + _j_×PTESIZE to a copy of _pte_ in which _pte_._ppn_[_i_][_pte_.__napot_bits__-1:0] +_a_ + _j_×PTESIZE to a copy of _pte_ in which _pte_._ppn_[_i_][_pte_.__napot_bits__-1:0] is replaced by _vpn[i][pte.napot_bits_-1:0], for any or all _j_ such that __j__ >> __napot_bits__ = __vpn__[__i__] >> __napot_bits__, all for the address space identified in _satp_ as loaded by step 1. endif::[] @@ -2322,7 +2335,7 @@ __ 1 + 2 + ... -|=== +|=== In such a case, an implementation may or may not support all options. The discoverability mechanism for this extension would be extended to @@ -2625,8 +2638,7 @@ coherent with store instructions that modify PTEs. ==== endif::[] -//// -[[sec:ssqosid]] +[[ssqosid]] == "Ssqosid" Extension for Quality-of-Service (QoS) Identifiers, Version 1.0 Quality of Service (QoS) is defined as the minimal end-to-end performance @@ -2708,11 +2720,11 @@ modes of software execution on that hart by default, but this behavior may be overridden by future extensions. If extension Smstateen is implemented together with Ssqosid, then Ssqosid also -requires the bit 55 in `mstateen0` introduced by Priv 1.14 to be implemented. If -bit 55 of `mstateen0` is 0, attempts to access `srmcfg` in privilege modes less -privileged than M-mode raise an illegal-instruction exception. If bit 55 of -`mstateen0` is 1 or if extension Smstateen is not implemented, attempts to -access `srmcfg` when `V=1` raise a virtual-instruction exception. +requires the P1P14 bit in `mstateen0` to be implemented. +If P1P14 of `mstateen0` is 0, attempts to access `srmcfg` in privilege modes +less privileged than M-mode raise an illegal-instruction exception. +If P1P14 bit of `mstateen0` is 1 or if extension Smstateen is not implemented, +attempts to access `srmcfg` when `V=1` raise a virtual-instruction exception. [NOTE] ==== @@ -2748,6 +2760,4 @@ the new context, it switches to the new VM's `srmcfg`. The supervisor can also use a separate configuration for execution not to be attributed to either contexts. ==== -//// - endif::[] diff --git a/docs/scripts/spec_builder.py b/docs/scripts/spec_builder.py index b76e0fd753..31c47ea86c 100755 --- a/docs/scripts/spec_builder.py +++ b/docs/scripts/spec_builder.py @@ -58,6 +58,7 @@ 'RVZicbo': False, 'RVZicfilp': False, 'RVZpm': False, + 'RVZsmctr': False, 'RVZsmepmp': False, 'RVZsmmpm': False, 'RVZsmrnmi': False, diff --git a/spyglass/reference_summary.rpt b/spyglass/reference_summary.rpt index 8cd2eeaab5..21af934a3b 100644 --- a/spyglass/reference_summary.rpt +++ b/spyglass/reference_summary.rpt @@ -3,9 +3,9 @@ # # This file has been generated by SpyGlass: # Report Name : summary -# Report Created by: asintzoff -# Report Created on: Mon Sep 9 16:12:42 2024 -# Working Directory: /home/asintzoff/git-repo/tss/cva6/spyglass +# Report Created by: gchauvon +# Report Created on: Wed Jan 15 17:25:40 2025 +# Working Directory: /home/gchauvon/rhel8/github_issue/issue_2280/cva6/spyglass # SpyGlass Version : SpyGlass_vS-2021.09-SP2-3 # Policy Name : SpyGlass(SpyGlass_vS-2021.09-SP2-03) # erc(SpyGlass_vS-2021.09-SP2-03) @@ -17,9 +17,9 @@ # starc(SpyGlass_vS-2021.09-SP2-03) # starc2005(SpyGlass_vS-2021.09-SP2-03) # -# Total Number of Generated Messages : 1023 -# Number of Waived Messages : 327 -# Number of Reported Messages : 696 +# Total Number of Generated Messages : 977 +# Number of Waived Messages : 885 +# Number of Reported Messages : 92 # Number of Overlimit Messages : 0 # # @@ -54,17 +54,9 @@ INFO HdlLibDuCheck_03 1 Reports that 'hdllibdu' is not required +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Severity Rule Name Count Short Help =============================================================================== -WARNING SYNTH_12605 5 Used Priority/Unique Type case/if - statement but all the conditions are - not covered -WARNING SYNTH_12608 1 The logic of the always block - mismatches with the type of Always - Block -WARNING SYNTH_12611 2 Property blocks will be ignored for - synthesis -WARNING SYNTH_5064 38 Non-synthesizable statements are +WARNING SYNTH_5064 12 Non-synthesizable statements are ignored for synthesis. -WARNING SYNTH_5143 11 Initial block is ignored for synthesis +WARNING SYNTH_5143 1 Initial block is ignored for synthesis WARNING SYNTH_89 4 Initial Assignment at Declaration is ignored by synthesis. WARNING WRN_27 1 Bit-select should not be out-of-range. @@ -80,46 +72,21 @@ INFO ElabSummary 1 Generates Elaborated design units +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Severity Rule Name Count Short Help =============================================================================== -ERROR InferLatch 2 Latch inferred -ERROR UndrivenInTerm-ML 1 Undriven but loaded input terminal of - an instance detected -ERROR W123 11 A signal or variable has been read but +ERROR W123 12 A signal or variable has been read but is not set ERROR W416 1 Width of return type and return value of a function should be same (Verilog) Range of return type and return value of a function should be same (VHDL) -WARNING FlopEConst 19 Flip-flop enable pin is permanently - disabled or enabled -WARNING ParamWidthMismatch-ML 1 Parameter width does not match with the - value assigned -WARNING STARC05-1.3.1.3 1 Asynchronous reset/preset signals must - not be used as non-reset/preset or - synchronous reset/preset signals -WARNING STARC05-2.1.3.1 2 Bit-width of function arguments must - match bit-width of the corresponding - function inputs. -WARNING STARC05-2.1.4.5 1 Bit-wise operators must be used instead - of logic operators in multi-bit - operations. -WARNING STARC05-2.1.5.3 2 Conditional expressions should evaluate - to a scalar. -WARNING STARC05-2.2.3.3 14 Do not assign over the same signal in +WARNING STARC05-2.2.3.3 2 Do not assign over the same signal in an always construct for sequential circuits -WARNING W224 2 Multi-bit expression found when one-bit - expression expected WARNING W263 4 A case expression width does not match case select expression width -WARNING W287b 36 Output port of an instance is not +WARNING W287b 17 Output port of an instance is not connected -WARNING W415a 45 Signal may be multiply assigned (beside +WARNING W415a 33 Signal may be multiply assigned (beside initialization) in the same scope. -WARNING W480 3 Loop index is not of type integer -WARNING W486 2 Shift overflow - some bits may be lost -WARNING W528 482 A signal or variable is set but never - read -INFO W528 1 A signal or variable is set but never - read +WARNING W486 1 Shift overflow - some bits may be lost +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ diff --git a/spyglass/sg_setup/cva6/cva6_waiver.awl b/spyglass/sg_setup/cva6/cva6_waiver.awl index 44ca186667..7327998b36 100644 --- a/spyglass/sg_setup/cva6/cva6_waiver.awl +++ b/spyglass/sg_setup/cva6/cva6_waiver.awl @@ -6,9 +6,13 @@ ## Modified by : Asmaa Kassimi (asmaa.kassimi@external.thalesgroup.com) - Thales ####################################################################################################### -waive -file_line {$CVA6_REPO_DIR/common/local/util/sram_cache.sv} {55} -severity { {ERROR} } -rule { {ErrorAnalyzeBBox} } -waive -file_line {$CVA6_REPO_DIR/common/local/util/sram_cache.sv} {85} -severity { {ERROR} } -rule { {ErrorAnalyzeBBox} } -waive -file { {$CVA6_REPO_DIR/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_sram.sv} } -severity { {ERROR} } -rule { {ErrorAnalyzeBBox} } -waive -file { {$CVA6_REPO_DIR/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_sram.sv} } -severity { {ERROR} } -rule { {SYNTH_5251} } +waive -file_line {$CVA6_REPO_DIR/common/local/util/sram_cache.sv} {55} -severity { {ERROR} } -rule { {ErrorAnalyzeBBox} } +waive -file_line {$CVA6_REPO_DIR/common/local/util/sram_cache.sv} {85} -severity { {ERROR} } -rule { {ErrorAnalyzeBBox} } +waive -file { {$CVA6_REPO_DIR/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_sram.sv} } -severity { {ERROR} } -rule { {ErrorAnalyzeBBox} } +waive -file { {$CVA6_REPO_DIR/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_sram.sv} } -severity { {ERROR} } -rule { {SYNTH_5251} } waive -file { {$CVA6_REPO_DIR/common/local/util/tc_sram_wrapper_cache_techno.sv} } -du { {tc_sram_wrapper_cache_techno} } -severity { {ERROR} } -rule { {ErrorAnalyzeBBox} } -waive -rule { {W240} } -comment {Created by akassimi on 26-Jul-2024 18:36:59} + +waive -file {$CVA6_REPO_DIR/core/cache_subsystem/*} -regexp + +waive -rule { {W240} } -comment {Created by akassimi on 26-Jul-2024 18:36:59} +waive -rule { {W528} } -comment {Remove Set but not read warning as it happens very often for disable features such as PMP, Accelerator, ...} diff --git a/vendor/patches/pulp-platform/common_cells/00001-spyglass-no-multiple-assignement-same-block-padded_input.patch b/vendor/patches/pulp-platform/common_cells/00001-spyglass-no-multiple-assignement-same-block-padded_input.patch new file mode 100644 index 0000000000..01410cbbd3 --- /dev/null +++ b/vendor/patches/pulp-platform/common_cells/00001-spyglass-no-multiple-assignement-same-block-padded_input.patch @@ -0,0 +1,16 @@ +diff --git a/vendor/pulp-platform/common_cells/src/popcount.sv b/vendor/pulp-platform/common_cells/src/popcount.sv +index 72b9b71f0..6fde114f3 100644 +--- a/vendor/pulp-platform/common_cells/src/popcount.sv ++++ b/vendor/pulp-platform/common_cells/src/popcount.sv +@@ -30,10 +30,7 @@ module popcount #( + logic [PopcountWidth-2:0] left_child_result, right_child_result; + + //Zero pad the input to next power of two +- always_comb begin +- padded_input = '0; +- padded_input[INPUT_WIDTH-1:0] = data_i; +- end ++ assign padded_input = {{{PaddedWidth-INPUT_WIDTH}{1'b0}}, data_i}; + + //Recursive instantiation to build binary adder tree + if (INPUT_WIDTH == 1) begin : single_node diff --git a/vendor/pulp-platform/common_cells/src/popcount.sv b/vendor/pulp-platform/common_cells/src/popcount.sv index 72b9b71f0f..6fde114f3e 100644 --- a/vendor/pulp-platform/common_cells/src/popcount.sv +++ b/vendor/pulp-platform/common_cells/src/popcount.sv @@ -30,10 +30,7 @@ module popcount #( logic [PopcountWidth-2:0] left_child_result, right_child_result; //Zero pad the input to next power of two - always_comb begin - padded_input = '0; - padded_input[INPUT_WIDTH-1:0] = data_i; - end + assign padded_input = {{{PaddedWidth-INPUT_WIDTH}{1'b0}}, data_i}; //Recursive instantiation to build binary adder tree if (INPUT_WIDTH == 1) begin : single_node diff --git a/verif/core-v-verif b/verif/core-v-verif index 6c1e999a97..60e57248c4 160000 --- a/verif/core-v-verif +++ b/verif/core-v-verif @@ -1 +1 @@ -Subproject commit 6c1e999a97f61b4b805603ba142a1347f785fff2 +Subproject commit 60e57248c48b0f8f90cf52af20aecc5c16e9d6d8 diff --git a/verif/docs/VerifPlans/csr_access/VP_IP000.yml b/verif/docs/VerifPlans/csr_access/VP_IP000.yml index a62965d9d2..6ea386da30 100644 --- a/verif/docs/VerifPlans/csr_access/VP_IP000.yml +++ b/verif/docs/VerifPlans/csr_access/VP_IP000.yml @@ -109,7 +109,7 @@ subfeatures: !!omap cores: 8 coverage_loc: '' comments: '' -vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' -io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' -config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' -ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' +vptool_gitrev: '$Id: a8b561f68549658061625891c533e7d45996bc9e $' +io_fmt_gitrev: '$Id: 61ab4e53ca49e21d56c416f0af0fa04d148e8001 $' +config_gitrev: '$Id: 5192fced2cfa10be5e18e827922e31e7489ed987 $' +ymlcfg_gitrev: '$Id: ce5e73bd5e8e0099334cb657afb7a624a99afbda $' diff --git a/verif/docs/VerifPlans/csr_access/VP_IP001.yml b/verif/docs/VerifPlans/csr_access/VP_IP001.yml index 8b16419697..39fff3010d 100644 --- a/verif/docs/VerifPlans/csr_access/VP_IP001.yml +++ b/verif/docs/VerifPlans/csr_access/VP_IP001.yml @@ -83,7 +83,7 @@ subfeatures: !!omap cores: 8 coverage_loc: '' comments: '' -vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' -io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' -config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' -ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' +vptool_gitrev: '$Id: a8b561f68549658061625891c533e7d45996bc9e $' +io_fmt_gitrev: '$Id: 61ab4e53ca49e21d56c416f0af0fa04d148e8001 $' +config_gitrev: '$Id: 5192fced2cfa10be5e18e827922e31e7489ed987 $' +ymlcfg_gitrev: '$Id: ce5e73bd5e8e0099334cb657afb7a624a99afbda $' diff --git a/verif/docs/VerifPlans/csr_access/VP_IP002.yml b/verif/docs/VerifPlans/csr_access/VP_IP002.yml index 51ed9fa8d0..2d6de3ffa8 100644 --- a/verif/docs/VerifPlans/csr_access/VP_IP002.yml +++ b/verif/docs/VerifPlans/csr_access/VP_IP002.yml @@ -108,7 +108,7 @@ subfeatures: !!omap cores: 8 coverage_loc: '' comments: '' -vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' -io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' -config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' -ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' +vptool_gitrev: '$Id: a8b561f68549658061625891c533e7d45996bc9e $' +io_fmt_gitrev: '$Id: 61ab4e53ca49e21d56c416f0af0fa04d148e8001 $' +config_gitrev: '$Id: 5192fced2cfa10be5e18e827922e31e7489ed987 $' +ymlcfg_gitrev: '$Id: ce5e73bd5e8e0099334cb657afb7a624a99afbda $' diff --git a/verif/docs/VerifPlans/csr_access/VP_IP003.yml b/verif/docs/VerifPlans/csr_access/VP_IP003.yml index 3099b330be..8b2c033333 100644 --- a/verif/docs/VerifPlans/csr_access/VP_IP003.yml +++ b/verif/docs/VerifPlans/csr_access/VP_IP003.yml @@ -119,7 +119,7 @@ subfeatures: !!omap cores: 8 coverage_loc: '' comments: '' -vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' -io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' -config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' -ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' +vptool_gitrev: '$Id: a8b561f68549658061625891c533e7d45996bc9e $' +io_fmt_gitrev: '$Id: 61ab4e53ca49e21d56c416f0af0fa04d148e8001 $' +config_gitrev: '$Id: 5192fced2cfa10be5e18e827922e31e7489ed987 $' +ymlcfg_gitrev: '$Id: ce5e73bd5e8e0099334cb657afb7a624a99afbda $' diff --git a/verif/docs/VerifPlans/csr_access/VP_IP004.yml b/verif/docs/VerifPlans/csr_access/VP_IP004.yml index 2250afd03e..e21f85d7fc 100644 --- a/verif/docs/VerifPlans/csr_access/VP_IP004.yml +++ b/verif/docs/VerifPlans/csr_access/VP_IP004.yml @@ -121,7 +121,7 @@ subfeatures: !!omap cores: 8 coverage_loc: '' comments: '' -vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' -io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' -config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' -ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' +vptool_gitrev: '$Id: a8b561f68549658061625891c533e7d45996bc9e $' +io_fmt_gitrev: '$Id: 61ab4e53ca49e21d56c416f0af0fa04d148e8001 $' +config_gitrev: '$Id: 5192fced2cfa10be5e18e827922e31e7489ed987 $' +ymlcfg_gitrev: '$Id: ce5e73bd5e8e0099334cb657afb7a624a99afbda $' diff --git a/verif/docs/VerifPlans/source/dvplan_csr-access.md b/verif/docs/VerifPlans/source/dvplan_csr-access.md index 3db4f93f73..278a48e805 100644 --- a/verif/docs/VerifPlans/source/dvplan_csr-access.md +++ b/verif/docs/VerifPlans/source/dvplan_csr-access.md @@ -1,67 +1,451 @@ # Module: CSR ACCESS VERIFICATION -## Feature: machineScratch(MSCRATCH) +## Feature: CVA6_Machine_mode_RW_CSRs(mstatus, misa, mideleg, medeleg, mie, mtvec, mcounteren, mepc, mcause, mtval, mip,pmpaddr[0..7], pmpcfg[0..1]) -### Sub-feature: 000_MSCRATCH +### Sub-feature: 000_Power-on-reset (POR) values of CSR #### Item: 000 -* **Requirement location:** riscv-privileged-20211203 +* **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CSR_CV32A60X.html * **Feature Description** - To verify the Power-on Reset value for MSCRATCH CSR. + Upon reset, RISC-V CVA6 Machine mode RW CSRs must initialize to their respective POR value. +* **Verification Goals** + + Verify that the Machine Mode RW CSR POR value must match with the value specified in the RISC-V CVA6 user manual. +* **Pass/Fail Criteria:** Self-Check +* **Test Type:** Directed SelfChk +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0 +* **Unique verification tag:** VP_CSR_VERIFICATION_F000_S000_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 001_Testing CSR with inverted reset value + + + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + Check the behaviour of the RISC-V Machine mode CVA6 CSRs,when reset inverted values are written to respective CSRs. +* **Verification Goals** + + 1. Verify CSR reading post write operation. + 2. Verify if the core correctly handles inverted reset values or not. +* **Pass/Fail Criteria:** Self-Check +* **Test Type:** Directed SelfChk +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0 +* **Unique verification tag:** VP_csr-access_F000_S003_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 002_CSR write and read operations + +#### Item: 000 + +* **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CSR_CV32A60X.html +* **Feature Description** + + check the correctness of RISCV CVA6 Machine Mode RW CSRs by writing random values like 0xa5a5a5a5, 0x5a5a5a5a, 0xffa1ae40.. and read using the CSR instructions defined in the instruction set architecture (ISA). +* **Verification Goals** + + 1.Verify that CSR can be written using the appropriate CSR write instructions. + + 2.Ensure correct read operations using CSR read instructions. - Address Offset : 0x340 - Width (bits) : 32 - Access Type : RW - Reset Value : 0x00000000 - priviliged mode : Machine + 3.Ensure that read values of the CSR should be as per CVA6 user manual +* **Pass/Fail Criteria:** Self-Check +* **Test Type:** Directed SelfChk +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0 +* **Unique verification tag:** VP_CSR_VERIFICATION_F000_S001_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 003_CSR access in different privilege modes + +#### Item: 000 + +* **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CSR_CV32A60X.html +* **Feature Description** + + Accessing RISC-V CVA6 Machine Mode CSRs in different privilege modes (User, Supervisor and Machine modes). * **Verification Goals** - Read MSCRATCH CSR to check default POR value that should be equal to 0x00000000. + 1.Ensure that Machine mode CSRs can only be accessed in the Machine mode according to the RISCV specification. + + 2.Verify that trying to access Machine Mode CSRs in lower privilege mode raises an illegal instruction exception. +* **Pass/Fail Criteria:** Self-Check +* **Test Type:** Directed SelfChk +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0 +* **Unique verification tag:** VP_CSR_VERIFICATION_F000_S002_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +## Feature: CVA6_Machine_mode_RO_CSRs(mvendorid, marchid, mimpid, mhartid) + +### Sub-feature: 000_Power-on-reset (POR) values of CSR + +#### Item: 000 + +* **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CSR_CV32A60X.html +* **Feature Description** + + Upon reset,RISC-V CVA6 Machine RO(read only) CSR must initialize to their respective POR value. +* **Verification Goals** + + Verify that the Machine RO(Read only) CSR POR value must match with the value specified in the RISC-V CVA6 User Manual. +* **Pass/Fail Criteria:** Self-Check +* **Test Type:** Directed SelfChk +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0 +* **Unique verification tag:** VP_CSR_VERIFICATION_F001_S000_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 001_CSR write and read operations + +#### Item: 000 + +* **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CSR_CV32A60X.html +* **Feature Description** + + Check the correctness of RISCV CVA6 read only CSR by writing random values like 0xa5a5a5a5, 0x5a5a5a5a, 0xffa1ae40.. and confirm whether write into RO CSRs is possible or not. +* **Verification Goals** + + 1.Attempt to write a RO CSR. + 2.Check to see that an illegal instruction exception occurred. + 3.Immediately after returning from the exception handler, check to see that the CSR value is not changed. +* **Pass/Fail Criteria:** Self-Check +* **Test Type:** Directed SelfChk +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0 +* **Unique verification tag:** VP_CSR_VERIFICATION_F001_S001_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 002_CSR access in different privilege modes + +#### Item: 000 + +* **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CSR_CV32A60X.html +* **Feature Description** + + Accessing RISC-V Machine read only CSRs in different privilege modes (User, Supervisor and Machine modes). +* **Verification Goals** + + 1.Ensure that Machine mode read only CSRs can only be accessed in Machine mode according to the RISC-V specification and does not alter the value of the CSR. + + 2.Verify that trying to access a Machine read only CSRs in an lower privilege mode raises an illegal instruction exception. +* **Pass/Fail Criteria:** Self-Check +* **Test Type:** Directed SelfChk +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0 +* **Unique verification tag:** VP_CSR_VERIFICATION_F001_S002_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +## Feature: CVA6_Supervisor_mode_RW_CSRs(sstatus,stvec, sip, sie, scounteren, sscratch, sepc, scause, stval, satp) + +### Sub-feature: 000_Power-on-reset (POR) values of CSR + +#### Item: 000 + +* **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CSR_CV32A60X.html +* **Feature Description** + + Upon reset, RISC-V CVA6 Supervisor mode RW CSRs must initialize to their respective POR value. +* **Verification Goals** + + Verify that the Supervisor Mode RW CSRs POR value must match with the value specified in the RISC-V CVA6 user manual. +* **Pass/Fail Criteria:** Self-Check +* **Test Type:** Directed SelfChk +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0 +* **Unique verification tag:** VP_CSR_VERIFICATION_F004_S000_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 001_Testing CSR with inverted reset value + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + Check the behaviour of the RISC-V Supervisor mode CVA6 CSRs,when reset inverted values are written to respective CSRs. +* **Verification Goals** + + Ensure that the written value can be read back (that is, the R/W CSR actually stored the value of ~PoR). * **Pass/Fail Criteria:** Check RM * **Test Type:** Directed SelfChk -* **Coverage Method:** N/A +* **Coverage Method:** Functional Coverage * **Applicable Cores:** CV32A6_v0.1.0 -* **Unique verification tag:** VP_csr-test-ident_F000_S000_I000 +* **Unique verification tag:** Inverted PoR value * **Link to Coverage:** * **Comments** *(none)* -#### Item: 001 +### Sub-feature: 002_CSR write and read operations + +#### Item: 000 -* **Requirement location:** riscv-privileged-20211203 +* **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CSR_CV32A60X.html * **Feature Description** - Verifying R/W access of a MSCRATCH CSR by writing random valid data like 0xFFFFFFFF, 0XA5A5A5A5, 0X5A5A5A5A ... and Read back CSR values to check correctness. + Check the correctness of RISCV CVA6 Supervisor Mode RW CSR by writing random values like 0xa5a5a5a5, 0x5a5a5a5a, 0xffa1ae40.. and read using the CSR instructions defined in the instruction set architecture (ISA). * **Verification Goals** - The read values of MSCRATCH CSR should matches with written random data values. -* **Pass/Fail Criteria:** NDY (Not Defined Yet) -* **Test Type:** NDY (Not Defined Yet) + 1.Verify that CSR can be written using the appropriate CSR write instructions. + 2.Ensure correct read operations using CSR read instructions. + 3.Ensure that read values of the CSR should be as per CVA6 user manual. +* **Pass/Fail Criteria:** Self-Check +* **Test Type:** Directed SelfChk +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0 +* **Unique verification tag:** VP_CSR_VERIFICATION_F004_S001_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 003_CSR access in different privilege modes + +#### Item: 000 + +* **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CSR_CV32A60X.html +* **Feature Description** + + Accessing RISC-V CVA6 Supervisor Mode CSRs in different privilege modes (User,Supervisor and Machine modes). +* **Verification Goals** + + 1.Ensure that Supervisor Mode CSRs can only be accessed in supervisor mode and in higher privilege mode according to the RISCV specification. + 2.Verify that trying to access a Supervisor Mode CSR in an lower privilege mode raises an illegal instruction exception. +* **Pass/Fail Criteria:** Self-Check +* **Test Type:** Directed SelfChk +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0 +* **Unique verification tag:** VP_CSR_VERIFICATION_F004_S002_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +## Feature: CVA6_User_Mode_Counter_CSRs(cycle, instret, cycleh, instreth) + +### Sub-feature: 000_Power-on-reset (POR) values of CSR + +#### Item: 000 + +* **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CSR_CV32A60X.html +* **Feature Description** + + Upon reset, RISC-V CVA6 User mode counter CSRs must initialize to their respective POR value. +* **Verification Goals** + + Verify that the User Mode counter CSR POR value must match with the value specified in the RISC-V CVA6 user manual. + As cycle will increment on the posedge of each clock and instret will increment after every instruction is retired. For these CSRs, the best technique to check reset value is by "visual inspection" +* **Pass/Fail Criteria:** Self-Check +* **Test Type:** Directed SelfChk * **Coverage Method:** NDY (Not Defined Yet) * **Applicable Cores:** CV32A6_v0.1.0 -* **Unique verification tag:** VP_csr-test-ident_F000_S000_I001 +* **Unique verification tag:** VP_CSR_VERIFICATION_F003_S000_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 001_Counter _CSRs_functionality_checking + +#### Item: 000 + +* **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CSR_CV32A60X.html +* **Feature Description** + + This feature pertains to the verification of functionality of RISC-V cycle, cycleh, instret and instreth Control Status Register (CSR). In a RISC-V architecture + + 1.’cycle’ and ‘cycleh’ are user-level CSR that hold low 32 bits and high 32 bits respectively of the count of clock cycles executed by the processor. + 2.’instret’ and ‘instreth’ are also user-level CSR that count the total number of instructions executed by the processor. + + The functionality of user mode counter CSR is being tested by performing two continuous reads and checking whether the value in the second read is greater than the value in the first read. +* **Verification Goals** + + 1.Verify that these CSR are properly initialized. + 2.Initiate a second read from the counter CSR immediately after the first read. + 3.Ensure that the value of the second read from counter CSR is greater than the value of the initial read. + 4.Confirm that user mode counter CSRs are incrementing. + + Note: This algorithm is only an "approximate test" of the functionality of these CSRs. +* **Pass/Fail Criteria:** Self-Check +* **Test Type:** Directed SelfChk +* **Coverage Method:** NDY (Not Defined Yet) +* **Applicable Cores:** CV32A6_v0.1.0 +* **Unique verification tag:** VP_CSR_VERIFICATION_F003_S001_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 002_CSR access in different privilege modes + +#### Item: 000 + +* **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CSR_CV32A60X.html +* **Feature Description** + + Accessing RISC-V CVA6 user Mode counter CSR in different privilege modes (User, Supervisor and Machine modes). +* **Verification Goals** + + Ensure that User mode counter CSRs can be accessed in user and Supervisor modes by configuring MCOUNTEREN CSR. +* **Pass/Fail Criteria:** Self-Check +* **Test Type:** Directed SelfChk +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0 +* **Unique verification tag:** VP_CSR_VERIFICATION_F003_S002_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 003_Verify the user mode counter CSRs behaviour after reaching maximum values + + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + check the behaviour of the RISC-V User mode counter CSRs when it reaches to maximum value. +* **Verification Goals** + + Ensure that user mode counter CSRs is updated to reset value as mentioned in CVA6 user manual after reaching to maximum value. +* **Pass/Fail Criteria:** Self-Check +* **Test Type:** Directed SelfChk +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0 +* **Unique verification tag:** VP_csr-access_F003_S003_I000 * **Link to Coverage:** * **Comments** *(none)* -#### Item: 002 +## Feature: CVA6_Machine_mode_counter_csr(mcycle,mcycleh,minstret,minstreth) + +### Sub-feature: 000_Power-on-reset (POR) values of CSR + +#### Item: 000 + +* **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CSR_CV32A60X.html +* **Feature Description** + + Upon reset, RISC-V CVA6 Machine mode counter CSRs must initialize to their respective POR value. +* **Verification Goals** + + Verify that the Machine Mode counter CSR POR value must match with the value specified in the RISC-V CVA6 user manual. + As mcycle will increment on the posedge of each clock and minstret will increment after every instruction is retired. For these CSRs, the best technique to check reset value is by "visual inspection" +* **Pass/Fail Criteria:** Self-Check +* **Test Type:** Directed SelfChk +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0 +* **Unique verification tag:** VP_csr-access_F002_S000_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 001_Counter _CSRs_functionality_checking + + +#### Item: 000 + +* **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CSR_CV32A60X.html +* **Feature Description** + + This feature pertains to the verification of functionality of RISC-V mcycle, mcycleh, minstret and minstreth Control Status Register (CSR). In a RISC-V architecture + + 1.’mcycle’ and ‘mcycleh’ are machine-level CSRs that hold low 32 bits and high 32 bits respectively of the count of clock cycles executed by the processor. + + 2.’minstret’ and ‘minstreth’ are also machine-level CSR that count the total number of instructions executed by the processor. + + The functionality of machine mode counter CSR is being tested by performing two continuous reads and checking whether the value in the second read is greater than the value in the first read. +* **Verification Goals** + + 1.Verify that these CSR are properly initialized. + 2.Initiate a second read from the counter CSR immediately after the first read. + 3.Ensure that the value of the second read from counter CSR is greater than the value of the initial read. + 4.Confirm that Machine Mode counter CSRs are incrementing. + + Note: This algorithm is only an "approximate test" of the functionality of these CSRs. +* **Pass/Fail Criteria:** Self-Check +* **Test Type:** Directed SelfChk +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0 +* **Unique verification tag:** VP_csr-access_F002_S001_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 002_CSR access in different privilege modes + +#### Item: 000 + +* **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CSR_CV32A60X.html +* **Feature Description** + + Accessing RISC-V CVA6 user Machine mode counter CSRs in different privilege modes (User, Supervisor and Machine modes). +* **Verification Goals** + + 1.Ensure that Machine mode CSRs can only be accessed in the Machine mode according to the RISC-V specification. + 2.Verify that trying to access Machine Mode CSRs in lower privilege mode raises an illegal instruction exception. +* **Pass/Fail Criteria:** Self-Check +* **Test Type:** Directed SelfChk +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0 +* **Unique verification tag:** VP_csr-access_F002_S002_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 003_Verify the Machine mode counter CSRs behaviour after reaching maximum value + +#### Item: 000 * **Requirement location:** * **Feature Description** - Verifying MSCRATCH CSR in other privilige modes(supervisor, user) + check the behaviour of the RISC-V Machine mode counter CSRs when it reaches to maximum value. * **Verification Goals** - It is expected that accessing Machine Mode CSRs in lower privilige modes will raise an exception. -* **Pass/Fail Criteria:** Check RM + Ensure that Machine mode counter CSRs is updated to reset value as mentioned in CVA6 user manual after reaching it to maximum value. +* **Pass/Fail Criteria:** Self-Check * **Test Type:** Directed SelfChk -* **Coverage Method:** N/A +* **Coverage Method:** Functional Coverage * **Applicable Cores:** CV32A6_v0.1.0 -* **Unique verification tag:** VP_csr-test-ident_F000_S000_I002 +* **Unique verification tag:** VP_csr-access_F002_S003_I000 * **Link to Coverage:** * **Comments** diff --git a/verif/env/uvme/cvxif_vseq/custom_instructions_cvxif_1_0_0.rst b/verif/env/uvme/cvxif_vseq/custom_instructions_cvxif_1_0_0.rst index ee53871c86..406dd50142 100644 --- a/verif/env/uvme/cvxif_vseq/custom_instructions_cvxif_1_0_0.rst +++ b/verif/env/uvme/cvxif_vseq/custom_instructions_cvxif_1_0_0.rst @@ -70,25 +70,25 @@ Except for 4 of them using opcode `MADD, MSUB, NMADD, NMSUB` **Format**: addi rd, rs1, rs2, rs3 -> |rs3|00|rs2|rs1|000|rd|100_0111| - **Description**: add register rs1, rs2 to rs3, and store the result in rd. + **Description**: subtract register rs2 and rs3 from rs1 and store the result in rd. - **Pseudocode**: x[rd] = x[rs1] + x[rs2] + x[rs3] + **Pseudocode**: x[rd] = x[rs1] - x[rs2] - x[rs3] - **CUS_ADD_RS3_NMADD**: Custom Add with RS3 opcode == NMADD **Format**: addi rd, rs1, rs2, rs3 -> |rs3|00|rs2|rs1|000|rd|100_1111| - **Description**: add register rs1, rs2 to rs3, and store the result in rd. + **Description**: add register rs1, rs2 to rs3, negate the sum, and store the result in rd. - **Pseudocode**: x[rd] = x[rs1] + x[rs2] + x[rs3] + **Pseudocode**: x[rd] = ¬(x[rs1] + x[rs2] + x[rs3]) - **CUS_ADD_RS3_NMSUB**: Custom Add with RS3 opcode == NMSUB **Format**: addi rd, rs1, rs2, rs3 -> |rs3|00|rs2|rs1|000|rd|100_1011| - **Description**: add register rs1, rs2 to rs3, and store the result in rd. + **Description**: subtract register rs2 and rs3 from rs1, negate the difference, and store the result in rd. - **Pseudocode**: x[rd] = x[rs1] + x[rs2] + x[rs3] + **Pseudocode**: x[rd] = ¬(x[rs1] - x[rs2] - x[rs3]) - **CUS_ADD_RS3_RTYPE**: Custom Add with RS3, rd is x10 (a0) diff --git a/verif/env/uvme/cvxif_vseq/uvme_cvxif_vseq.sv b/verif/env/uvme/cvxif_vseq/uvme_cvxif_vseq.sv index ddb443c11b..de4da8a1d2 100644 --- a/verif/env/uvme/cvxif_vseq/uvme_cvxif_vseq.sv +++ b/verif/env/uvme/cvxif_vseq/uvme_cvxif_vseq.sv @@ -378,42 +378,42 @@ task uvme_cvxif_vseq_c::do_instr_result(); end "CUS_ADD_RS3_MSUB": begin if (req_item.register.rs_valid == 3'b111) begin - resp_item.result.data = req_item.register.rs[0] + req_item.register.rs[1] + req_item.register.rs[2]; + resp_item.result.data = req_item.register.rs[0] - req_item.register.rs[1] - req_item.register.rs[2]; resp_item.result.rd = req_item.issue_req.instr[11:7]; end else if (req_item.register.rs_valid == 2'b11) begin - resp_item.result.data = req_item.register.rs[0] + req_item.register.rs[1]; + resp_item.result.data = req_item.register.rs[0] - req_item.register.rs[1]; resp_item.result.rd = req_item.issue_req.instr[11:7]; end end "CUS_ADD_RS3_NMADD": begin if (req_item.register.rs_valid == 3'b111) begin - resp_item.result.data = req_item.register.rs[0] + req_item.register.rs[1] + req_item.register.rs[2]; + resp_item.result.data = ~(req_item.register.rs[0] + req_item.register.rs[1] + req_item.register.rs[2]); resp_item.result.rd = req_item.issue_req.instr[11:7]; end else if (req_item.register.rs_valid == 2'b11) begin - resp_item.result.data = req_item.register.rs[0] + req_item.register.rs[1]; + resp_item.result.data = ~(req_item.register.rs[0] + req_item.register.rs[1]); resp_item.result.rd = req_item.issue_req.instr[11:7]; end end "CUS_ADD_RS3_NMSUB": begin if (req_item.register.rs_valid == 3'b111) begin - resp_item.result.data = req_item.register.rs[0] + req_item.register.rs[1] + req_item.register.rs[2]; + resp_item.result.data = ~(req_item.register.rs[0] - req_item.register.rs[1] - req_item.register.rs[2]); resp_item.result.rd = req_item.issue_req.instr[11:7]; end else if (req_item.register.rs_valid == 2'b11) begin - resp_item.result.data = req_item.register.rs[0] + req_item.register.rs[1]; + resp_item.result.data = ~(req_item.register.rs[0] - req_item.register.rs[1]); resp_item.result.rd = req_item.issue_req.instr[11:7]; end end "CUS_ADD_RS3_RTYPE": begin if (req_item.register.rs_valid == 3'b111) begin resp_item.result.data = req_item.register.rs[0] + req_item.register.rs[1] + req_item.register.rs[2]; - resp_item.result.rd = 5'h10; + resp_item.result.rd = 5'hA; end else if (req_item.register.rs_valid == 2'b11) begin resp_item.result.data = req_item.register.rs[0] + req_item.register.rs[1]; - resp_item.result.rd = 5'h10; + resp_item.result.rd = 5'hA; end end "ILLEGAL": begin diff --git a/verif/env/uvme/uvme_cva6_cfg.sv b/verif/env/uvme/uvme_cva6_cfg.sv index 946c63b4b3..1f597e49c8 100644 --- a/verif/env/uvme/uvme_cva6_cfg.sv +++ b/verif/env/uvme/uvme_cva6_cfg.sv @@ -131,8 +131,7 @@ class uvme_cva6_cfg_c extends uvma_core_cntrl_cfg_c; HPDCache_supported == (RTLCVA6Cfg.DCacheType == 2); MmuPresent == RTLCVA6Cfg.MmuPresent; - // TODO : add RTL paramater related to this field fix issue#2500 - sw_int_supported == 0; + sw_int_supported == RTLCVA6Cfg.SoftwareInterruptEn; } constraint ext_const { diff --git a/verif/sim/Makefile b/verif/sim/Makefile index 01fffe13cc..642b83f31d 100644 --- a/verif/sim/Makefile +++ b/verif/sim/Makefile @@ -214,7 +214,7 @@ ALL_UVM_FLAGS = -lca -sverilog +incdir+$(VCS_HOME)/etc/uvm/src \ $(VCS_HOME)/etc/uvm/src/uvm_pkg.sv -ntb_opts uvm-1.2 -timescale=1ns/1ps \ -assert svaext -race=all -ignore unique_checks -full64 -q +incdir+$(VCS_HOME)/etc/uvm/src \ $(if $(DEBUG), -debug_access+all $(if $(VERDI), -kdb) $(if $(TRACE_COMPACT),+vcs+fsdbon)) \ - -cm_seqnoconst -diag noconst \ + -cm_seqnoconst -diag noconst -cm_cond arith \ ALL_SIMV_UVM_FLAGS = +vcs+lic+wait $(issrun_opts) \ diff --git a/verif/sim/cva6.py b/verif/sim/cva6.py index e30c798555..4c5075ec89 100644 --- a/verif/sim/cva6.py +++ b/verif/sim/cva6.py @@ -887,7 +887,7 @@ def load_config(args, cwd): elif base in ("cv64a6_imafdc_sv39_wb"): args.mabi = "lp64d" args.isa = "rv64gc_zba_zbb_zbs_zbc" - elif base in ("cv64a6_imafdc_sv39", "cv64a6_imafdc_sv39_hpdcache"): + elif base in ("cv64a6_imafdc_sv39", "cv64a6_imafdc_sv39_hpdcache", "cv64a6_imafdc_sv39_hpdcache_wb"): args.mabi = "lp64d" args.isa = "rv64gc_zba_zbb_zbs_zbc_zbkb" elif base == "cv32a60x":