diff --git a/boards/nordic/nrf7120pdk/Kconfig b/boards/nordic/nrf7120pdk/Kconfig new file mode 100644 index 000000000000..11eeb874c08c --- /dev/null +++ b/boards/nordic/nrf7120pdk/Kconfig @@ -0,0 +1,34 @@ +# nRF7120 PDK board configuration + +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + +if BOARD_NRF7120PDK_NRF7120_ENGA_CPUAPP_NS + +config NRF_MPC_REGION_SIZE + hex + default 0x1000 + help + Region size for the Memory Protection Controller (MPC) in bytes. + +config NRF_TRUSTZONE_FLASH_REGION_SIZE + hex + default NRF_MPC_REGION_SIZE + help + This defines the flash region size from the TRUSTZONE perspective. + It is used when configuring the TRUSTZONE and when setting alignments + requirements for the partitions. + This abstraction allows us to configure TRUSTZONE without depending + on peripheral specific symbols. + +config NRF_TRUSTZONE_RAM_REGION_SIZE + hex + default NRF_MPC_REGION_SIZE + help + This defines the RAM region size from the TRUSTZONE perspective. + It is used when configuring the TRUSTZONE and when setting alignments + requirements for the partitions. + This abstraction allows us to configure TRUSTZONE without depending + on peripheral specific symbols. + +endif # BOARD_NRF7120PDK_NRF7120_ENGA_CPUAPP_NS diff --git a/boards/nordic/nrf7120pdk/Kconfig.defconfig b/boards/nordic/nrf7120pdk/Kconfig.defconfig new file mode 100644 index 000000000000..b9935acf011f --- /dev/null +++ b/boards/nordic/nrf7120pdk/Kconfig.defconfig @@ -0,0 +1,37 @@ + +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause +if BOARD_NRF7120PDK_NRF7120_ENGA_CPUAPP +config BT_CTLR + default BT + +config ROM_START_OFFSET + default 0 if PARTITION_MANAGER_ENABLED + default 0x800 if BOOTLOADER_MCUBOOT + +endif # BOARD_NRF7120PDK_NRF7120_ENGA_CPUAPP + +if BOARD_NRF7120PDK_NRF7120_ENGA_CPUAPP_NS + +config BT_CTLR + default BT + +# By default, if we build for a Non-Secure version of the board, +# enable building with TF-M as the Secure Execution Environment. +config BUILD_WITH_TFM + default y + +# By default, if we build with TF-M, instruct build system to +# flash the combined TF-M (Secure) & Zephyr (Non Secure) image +config TFM_FLASH_MERGED_BINARY + default y + depends on BUILD_WITH_TFM + +endif # BOARD_NRF7120PDK_NRF7120_ENGA_CPUAPP_NS + +if BOARD_NRF7120PDK_NRF7120_ENGA_CPUFLPR || BOARD_NRF7120PDK_NRF7120_ENGA_CPUFLPR_XIP + +# As FLPR has limited memory most of tests does not fit with asserts enabled. +config ASSERT + default n if ZTEST +endif # BOARD_NRF7120PDK_NRF7120_ENGA_CPUFLPR || BOARD_NRF7120PDK_NRF7120_ENGA_CPUFLPR_XIP diff --git a/boards/nordic/nrf7120pdk/Kconfig.nrf7120pdk b/boards/nordic/nrf7120pdk/Kconfig.nrf7120pdk new file mode 100644 index 000000000000..9634c854483d --- /dev/null +++ b/boards/nordic/nrf7120pdk/Kconfig.nrf7120pdk @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause +config BOARD_NRF7120PDK + select SOC_NRF7120_ENGA_CPUAPP if BOARD_NRF7120PDK_NRF7120_ENGA_CPUAPP || \ + BOARD_NRF7120PDK_NRF7120_ENGA_CPUAPP_NS + select SOC_NRF7120_ENGA_CPUFLPR if BOARD_NRF7120PDK_NRF7120_ENGA_CPUFLPR || \ + BOARD_NRF7120PDK_NRF7120_ENGA_CPUFLPR_XIP diff --git a/boards/nordic/nrf7120pdk/board.cmake b/boards/nordic/nrf7120pdk/board.cmake new file mode 100644 index 000000000000..3218b93c4895 --- /dev/null +++ b/boards/nordic/nrf7120pdk/board.cmake @@ -0,0 +1,20 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + +if(CONFIG_SOC_NRF7120_ENGA_CPUAPP) + board_runner_args(jlink "--device=cortex-m33" "--speed=4000") +elseif(CONFIG_SOC_NRF7120_ENGA_CPUFLPR) + board_runner_args(jlink "--speed=4000") +endif() + +if(BOARD_NRF7120PDK_NRF7120_CPUAPP_NS) + set(TFM_PUBLIC_KEY_FORMAT "full") +endif() + +if(CONFIG_TFM_FLASH_MERGED_BINARY) + set_property(TARGET runners_yaml_props_target PROPERTY hex_file tfm_merged.hex) +endif() + +include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/nordic/nrf7120pdk/board.yml b/boards/nordic/nrf7120pdk/board.yml new file mode 100644 index 000000000000..1ec37ec390c9 --- /dev/null +++ b/boards/nordic/nrf7120pdk/board.yml @@ -0,0 +1,15 @@ +board: + name: nrf7120pdk + vendor: nordic + socs: + - name: nrf7120_enga + variants: + - name: xip + cpucluster: cpuflpr + - name: ns + cpucluster: cpuapp + revision: + format: major.minor.patch + default: "0.0.0" + revisions: + - name: "0.0.0" diff --git a/boards/nordic/nrf7120pdk/nrf7120_enga_cpuapp_common.dtsi b/boards/nordic/nrf7120pdk/nrf7120_enga_cpuapp_common.dtsi new file mode 100644 index 000000000000..fed9004b6c47 --- /dev/null +++ b/boards/nordic/nrf7120pdk/nrf7120_enga_cpuapp_common.dtsi @@ -0,0 +1,130 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + */ + +/* This file is common to the secure and non-secure domain */ + +#include "arm/nordic/nrf7120_enga_cpuapp.dtsi" +#include "nrf7120pdk_nrf7120_enga-common.dtsi" + +/ { + chosen { + zephyr,console = &uart20; + zephyr,shell-uart = &uart20; + zephyr,uart-mcumgr = &uart20; + zephyr,flash = &cpuapp_mram; + zephyr,ieee802154 = &ieee802154; + }; +}; + +&cpuapp_sram { + status = "okay"; +}; + +&grtc { + owned-channels = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>; + /* Channels 7-11 reserved for Zero Latency IRQs, 3-4 for FLPR */ + child-owned-channels = <3 4 7 8 9 10 11>; + status = "okay"; +}; + +&cpuapp_mram { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x0 DT_SIZE_K(64)>; + }; + + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x10000 DT_SIZE_K(960)>; + }; + + slot0_ns_partition: partition@100000 { + label = "image-0-nonsecure"; + reg = <0x100000 DT_SIZE_K(960)>; + }; + + slot1_partition: partition@1f0000 { + label = "image-1"; + reg = <0x1f0000 DT_SIZE_K(960)>; + }; + + slot1_ns_partition: partition@2e0000 { + label = "image-1-nonsecure"; + reg = <0x2e0000 DT_SIZE_K(960)>; + }; + + /* 32k from 0x3d0000 to 0x2d7fff reserved for TF-M partitions */ + storage_partition: partition@3d8000 { + label = "storage"; + reg = < 0x3d8000 DT_SIZE_K(36)>; + }; + }; +}; + +&uart20 { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&gpiote20 { + status = "okay"; +}; + +&gpiote30 { + status = "okay"; +}; + +&radio { + status = "okay"; +}; + +&ieee802154 { + status = "okay"; +}; + +&temp { + status = "okay"; +}; + +&clock { + status = "okay"; +}; + +&spi00 { + status = "okay"; + cs-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&spi00_default>; + pinctrl-1 = <&spi00_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&adc { + status = "okay"; +}; diff --git a/boards/nordic/nrf7120pdk/nrf7120pdk_nrf7120_enga-common.dtsi b/boards/nordic/nrf7120pdk/nrf7120pdk_nrf7120_enga-common.dtsi new file mode 100644 index 000000000000..bb65ba7cfe51 --- /dev/null +++ b/boards/nordic/nrf7120pdk/nrf7120pdk_nrf7120_enga-common.dtsi @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + */ + +#include "nrf7120pdk_nrf7120_enga-pinctrl.dtsi" + +/ { + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>; + label = "Green LED 0"; + }; + led1: led_1 { + gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + label = "Green LED 1"; + }; + led2: led_2 { + gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; + label = "Green LED 2"; + }; + led3: led_3 { + gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; + label = "Green LED 3"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + /* + * PWM signal can be exposed on GPIO pin only within same domain. + * There is only one domain which contains both PWM and GPIO: + * PWM20/21/22 and GPIO Port P1. + * Only LEDs connected to P1 can work with PWM, for example LED1. + */ + pwm_led1: pwm_led_1 { + pwms = <&pwm20 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + }; + }; + + buttons { + compatible = "gpio-keys"; + button0: button_0 { + gpios = <&gpio1 13 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 0"; + zephyr,code = ; + }; + button1: button_1 { + gpios = <&gpio1 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 1"; + zephyr,code = ; + }; + button2: button_2 { + gpios = <&gpio1 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 2"; + zephyr,code = ; + }; + button3: button_3 { + gpios = <&gpio0 4 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 3"; + zephyr,code = ; + }; + }; + + aliases { + led0 = &led0; + led1 = &led1; + led2 = &led2; + led3 = &led3; + pwm-led0 = &pwm_led1; + sw0 = &button0; + sw1 = &button1; + sw2 = &button2; + sw3 = &button3; + watchdog0 = &wdt31; + }; +}; + +&uart20 { + current-speed = <115200>; + pinctrl-0 = <&uart20_default>; + pinctrl-1 = <&uart20_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&uart30 { + current-speed = <115200>; + pinctrl-0 = <&uart30_default>; + pinctrl-1 = <&uart30_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&pwm20 { + status = "okay"; + pinctrl-0 = <&pwm20_default>; + pinctrl-1 = <&pwm20_sleep>; + pinctrl-names = "default", "sleep"; +}; diff --git a/boards/nordic/nrf7120pdk/nrf7120pdk_nrf7120_enga-pinctrl.dtsi b/boards/nordic/nrf7120pdk/nrf7120pdk_nrf7120_enga-pinctrl.dtsi new file mode 100644 index 000000000000..54c21b117483 --- /dev/null +++ b/boards/nordic/nrf7120pdk/nrf7120pdk_nrf7120_enga-pinctrl.dtsi @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor + * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + */ + +&pinctrl { + /omit-if-no-ref/ uart20_default: uart20_default { + group1 { + psels = , + ; + }; + group2 { + psels = , + ; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ uart20_sleep: uart20_sleep { + group1 { + psels = , + , + , + ; + low-power-enable; + }; + }; + + /omit-if-no-ref/ uart30_default: uart30_default { + group1 { + psels = , + ; + }; + group2 { + psels = , + ; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ uart30_sleep: uart30_sleep { + group1 { + psels = , + , + , + ; + low-power-enable; + }; + }; + + /omit-if-no-ref/ spi00_default: spi00_default { + group1 { + psels = , + , + ; + }; + }; + + /omit-if-no-ref/ spi00_sleep: spi00_sleep { + group1 { + psels = , + , + ; + low-power-enable; + }; + }; + + /omit-if-no-ref/ pwm20_default: pwm20_default { + group1 { + psels = ; + }; + }; + + /omit-if-no-ref/ pwm20_sleep: pwm20_sleep { + group1 { + psels = ; + low-power-enable; + }; + }; +}; diff --git a/boards/nordic/nrf7120pdk/nrf7120pdk_nrf7120_enga_cpuapp.dts b/boards/nordic/nrf7120pdk/nrf7120pdk_nrf7120_enga_cpuapp.dts new file mode 100644 index 000000000000..395278bcd071 --- /dev/null +++ b/boards/nordic/nrf7120pdk/nrf7120pdk_nrf7120_enga_cpuapp.dts @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + */ + +/dts-v1/; + +#include "nrf7120_enga_cpuapp_common.dtsi" + +/ { + compatible = "nordic,nrf7120pdk_nrf7120_enga-cpuapp"; + model = "Nordic nRF7120 PDK nRF7120_ENGA Application MCU"; + + chosen { + zephyr,sram = &cpuapp_sram; + }; +}; diff --git a/boards/nordic/nrf7120pdk/nrf7120pdk_nrf7120_enga_cpuapp.yaml b/boards/nordic/nrf7120pdk/nrf7120pdk_nrf7120_enga_cpuapp.yaml new file mode 100644 index 000000000000..add69ca4f40d --- /dev/null +++ b/boards/nordic/nrf7120pdk/nrf7120pdk_nrf7120_enga_cpuapp.yaml @@ -0,0 +1,23 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + +identifier: nrf7120pdk/nrf7120_enga/cpuapp +name: nRF7120-PDK-nRF7120_ENGA-Application +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +sysbuild: true +ram: 512 +flash: 960 +supported: + - adc + - counter + - gpio + - i2c + - pwm + - spi + - watchdog + - i2s diff --git a/boards/nordic/nrf7120pdk/nrf7120pdk_nrf7120_enga_cpuapp_defconfig b/boards/nordic/nrf7120pdk/nrf7120pdk_nrf7120_enga_cpuapp_defconfig new file mode 100644 index 000000000000..3ddd36b29991 --- /dev/null +++ b/boards/nordic/nrf7120pdk/nrf7120pdk_nrf7120_enga_cpuapp_defconfig @@ -0,0 +1,25 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# MPU-based null-pointer dereferencing detection cannot +# be applied as the (0x0 - 0x400) is unmapped for this target. +CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y + +# Start SYSCOUNTER on driver init +CONFIG_NRF_GRTC_START_SYSCOUNTER=y diff --git a/boards/nordic/nrf7120pdk/nrf7120pdk_nrf7120_enga_cpuapp_ns.dts b/boards/nordic/nrf7120pdk/nrf7120pdk_nrf7120_enga_cpuapp_ns.dts new file mode 100644 index 000000000000..961a4a94b6b3 --- /dev/null +++ b/boards/nordic/nrf7120pdk/nrf7120pdk_nrf7120_enga_cpuapp_ns.dts @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + */ + +/dts-v1/; + +#define USE_NON_SECURE_ADDRESS_MAP 1 + +#include "nrf7120_enga_cpuapp_common.dtsi" + +/ { + compatible = "nordic,nrf7120pdk_nrf7120_enga-cpuapp"; + model = "Nordic nRF7120 PDK nRF7120_ENGA Application MCU"; + + chosen { + zephyr,sram = &cpuapp_sram; + }; +}; + +&uart30 { + /* Disable so that TF-M can use this UART */ + status = "disabled"; + + current-speed = <115200>; + pinctrl-0 = <&uart30_default>; + pinctrl-1 = <&uart30_sleep>; + pinctrl-names = "default", "sleep"; +}; diff --git a/boards/nordic/nrf7120pdk/nrf7120pdk_nrf7120_enga_cpuapp_ns.yaml b/boards/nordic/nrf7120pdk/nrf7120pdk_nrf7120_enga_cpuapp_ns.yaml new file mode 100644 index 000000000000..15b9f55f5ff6 --- /dev/null +++ b/boards/nordic/nrf7120pdk/nrf7120pdk_nrf7120_enga_cpuapp_ns.yaml @@ -0,0 +1,22 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + +identifier: nrf7120pdk/nrf7120_enga/cpuapp/ns +name: nRF7120-PDK-nRF7120_ENGA-Application-Non-Secure +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 1024 +flash: 4088 +supported: + - adc + - gpio + - i2c + - spi + - counter + - watchdog + - adc + - i2s diff --git a/boards/nordic/nrf7120pdk/nrf7120pdk_nrf7120_enga_cpuapp_ns_defconfig b/boards/nordic/nrf7120pdk/nrf7120pdk_nrf7120_enga_cpuapp_ns_defconfig new file mode 100644 index 000000000000..70f01d7c9baf --- /dev/null +++ b/boards/nordic/nrf7120pdk/nrf7120pdk_nrf7120_enga_cpuapp_ns_defconfig @@ -0,0 +1,31 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# This Board implies building Non-Secure firmware +CONFIG_TRUSTED_EXECUTION_NONSECURE=y + +# Don't enable the cache in the non-secure image as it is a +# secure-only peripheral on 54l +CONFIG_CACHE_MANAGEMENT=n +CONFIG_EXTERNAL_CACHE=n + +CONFIG_UART_CONSOLE=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y + +# Enable GPIO +CONFIG_GPIO=y + +# Start SYSCOUNTER on driver init +CONFIG_NRF_GRTC_START_SYSCOUNTER=y diff --git a/boards/nordic/nrf7120pdk/nrf7120pdk_nrf7120_enga_cpuflpr.dts b/boards/nordic/nrf7120pdk/nrf7120pdk_nrf7120_enga_cpuflpr.dts new file mode 100644 index 000000000000..168a656ca124 --- /dev/null +++ b/boards/nordic/nrf7120pdk/nrf7120pdk_nrf7120_enga_cpuflpr.dts @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + */ + +/dts-v1/; + +#include "nordic/nrf7120_enga_cpuflpr.dtsi" +#include "nrf7120pdk_nrf7120_enga-common.dtsi" + +/ { + model = "Nordic nRF7120 PDK nRF7120_ENGA FLPR MCU"; + compatible = "nordic,nrf7120pdk_nrf7120_enga-cpuflpr"; + + chosen { + zephyr,console = &uart30; + zephyr,shell-uart = &uart30; + zephyr,code-partition = &cpuflpr_code_partition; + zephyr,flash = &cpuflpr_mram; + zephyr,sram = &cpuflpr_sram; + }; +}; + +&cpuflpr_sram { + status = "okay"; + reg = <0x200e0000 DT_SIZE_K(124)>; + ranges = <0x0 0x200e0000 0x1f000>; +}; + +&cpuflpr_mram { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + cpuflpr_code_partition: partition@0 { + label = "image-0"; + reg = <0 DT_SIZE_K(116)>; + }; + }; +}; + +&grtc { + owned-channels = <3 4>; + status = "okay"; +}; + +&uart30 { + status = "okay"; + hw-flow-control; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&gpiote20 { + status = "okay"; +}; + +&gpiote30 { + status = "okay"; +}; diff --git a/boards/nordic/nrf7120pdk/nrf7120pdk_nrf7120_enga_cpuflpr.yaml b/boards/nordic/nrf7120pdk/nrf7120pdk_nrf7120_enga_cpuflpr.yaml new file mode 100644 index 000000000000..a4a6262693d6 --- /dev/null +++ b/boards/nordic/nrf7120pdk/nrf7120pdk_nrf7120_enga_cpuflpr.yaml @@ -0,0 +1,18 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + +identifier: nrf7120pdk/nrf7120_enga/cpuflpr +name: nRF7120-PDK-nRF7120_ENGA-Fast-Lightweight-Peripheral-Processor +type: mcu +arch: riscv +toolchain: + - zephyr +sysbuild: true +ram: 124 +flash: 116 +supported: + - counter + - gpio + - i2c + - spi + - watchdog diff --git a/boards/nordic/nrf7120pdk/nrf7120pdk_nrf7120_enga_cpuflpr_defconfig b/boards/nordic/nrf7120pdk/nrf7120pdk_nrf7120_enga_cpuflpr_defconfig new file mode 100644 index 000000000000..3570482cd42e --- /dev/null +++ b/boards/nordic/nrf7120pdk/nrf7120pdk_nrf7120_enga_cpuflpr_defconfig @@ -0,0 +1,17 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable GPIO +CONFIG_GPIO=y + +CONFIG_USE_DT_CODE_PARTITION=y + +# Execute from SRAM +CONFIG_XIP=n diff --git a/boards/nordic/nrf7120pdk/nrf7120pdk_nrf7120_enga_cpuflpr_xip.dts b/boards/nordic/nrf7120pdk/nrf7120pdk_nrf7120_enga_cpuflpr_xip.dts new file mode 100644 index 000000000000..61b654ced09f --- /dev/null +++ b/boards/nordic/nrf7120pdk/nrf7120pdk_nrf7120_enga_cpuflpr_xip.dts @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + */ + +#include "nrf7120pdk_nrf7120_enga_cpuflpr.dts" + +&cpuflpr_sram { + reg = <0x200e0000 DT_SIZE_K(124)>; + ranges = <0x0 0x200e0000 0x1f000>; +}; diff --git a/boards/nordic/nrf7120pdk/nrf7120pdk_nrf7120_enga_cpuflpr_xip.yaml b/boards/nordic/nrf7120pdk/nrf7120pdk_nrf7120_enga_cpuflpr_xip.yaml new file mode 100644 index 000000000000..a5df716e2c3e --- /dev/null +++ b/boards/nordic/nrf7120pdk/nrf7120pdk_nrf7120_enga_cpuflpr_xip.yaml @@ -0,0 +1,18 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + +identifier: nrf7120pdk/nrf7120_enga/cpuflpr/xip +name: nRF7120-PDK-nRF7120_ENGA-Fast-Lightweight-Peripheral-Processor (RRAM XIP) +type: mcu +arch: riscv +toolchain: + - zephyr +sysbuild: true +ram: 124 +flash: 116 +supported: + - counter + - gpio + - i2c + - spi + - watchdog diff --git a/boards/nordic/nrf7120pdk/nrf7120pdk_nrf7120_enga_cpuflpr_xip_defconfig b/boards/nordic/nrf7120pdk/nrf7120pdk_nrf7120_enga_cpuflpr_xip_defconfig new file mode 100644 index 000000000000..6d8ff064f999 --- /dev/null +++ b/boards/nordic/nrf7120pdk/nrf7120pdk_nrf7120_enga_cpuflpr_xip_defconfig @@ -0,0 +1,15 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable GPIO +CONFIG_GPIO=y + +# Execute from RRAM +CONFIG_XIP=y diff --git a/dts/arm/nordic/nrf7120_enga.dtsi b/dts/arm/nordic/nrf7120_enga.dtsi new file mode 100644 index 000000000000..9c61297f7dbe --- /dev/null +++ b/dts/arm/nordic/nrf7120_enga.dtsi @@ -0,0 +1,901 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + */ + #include + #include + +/delete-node/ &sw_pwm; + +/ { + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpuapp: cpu@0 { + compatible = "arm,cortex-m33f"; + reg = <0>; + device_type = "cpu"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <1>; + itm: itm@e0000000 { + compatible = "arm,armv8m-itm"; + reg = <0xe0000000 0x1000>; + swo-ref-frequency = ; + }; + }; + + cpuflpr: cpu@1 { + compatible = "nordic,vpr"; + reg = <1>; + device_type = "cpu"; + clock-frequency = ; + riscv,isa = "rv32emc"; + nordic,bus-width = <32>; + }; + }; + + clocks { + lfxo: lfxo { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + hfxo: hfxo64m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = ; + }; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + nordic_reserved: memory@200ff000{ + #address-cells = <1>; + #size-cells = <1>; + compatible = "mmio-sram"; + reg = <0x200ff000 DT_SIZE_K(4)>; + ranges = <0x0 0x200ff000 0x1000>; + }; + + nrf_kmu_reserved_push_area: memory@200fff00{ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x200fff00 0x0100>; + compatible = "zephyr,memory-region", "mmio-sram"; + zephyr,memory-region = "NRF_KMU_RESERVED_PUSH"; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + + ficr: ficr@ffc000 { + compatible = "nordic,nrf-ficr"; + reg = <0xffc000 0x1000>; + status = "disabled"; + }; + +#ifdef USE_NON_SECURE_ADDRESS_MAP + /* Intentionally empty because uicr is hardware fixed to Secure */ +#else + uicr: uicr@ffd000 { + compatible = "nordic,nrf-uicr"; + reg = <0xffd000 0x1000>; + status = "disabled"; + }; +#endif + + cpuapp_mram: mram@0 { + compatible = "nordic,mram"; + reg = <0 DT_SIZE_K(3972)>; + erase-block-size = <4096>; + write-block-size = <4>; + }; + + cpuflpr_mram: mram@3e1000 { + compatible = "nordic,mram"; + reg = <0x3e1000 DT_SIZE_K(116)>; + erase-block-size = <4096>; + write-block-size = <4>; + }; + + cpuapp_sram: memory@20000000 { + compatible = "mmio-sram"; + reg = <0x20000000 DT_SIZE_K(512)>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x20000000 0x80000>; + }; + + ram01_sram: memory@20080000 { + compatible = "mmio-sram"; + reg = <0x20080000 DT_SIZE_K(256)>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x20080000 0x40000>; + }; + + ram02_sram: memory@200c0000 { + compatible = "mmio-sram"; + reg = <0x200c0000 DT_SIZE_K(128)>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x200c0000 0x20000>; + }; + + cpuflpr_sram: memory@200e0000 { + compatible = "mmio-sram"; + reg = <0x200e0000 DT_SIZE_K(124)>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x200e0000 0x1f000>; + }; + +#ifdef USE_NON_SECURE_ADDRESS_MAP + global_peripherals: peripheral@40000000 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x40000000 0x10000000>; +#else + global_peripherals: peripheral@50000000 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x50000000 0x10000000>; +#endif + +#ifdef USE_NON_SECURE_ADDRESS_MAP + /* Intentionally empty because spu00 is hardware fixed to Secure */ +#else + spu00: spu@40000 { + compatible = "nordic,nrf-spu"; + reg = <0x40000 0x1000>; + interrupts = <64 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + }; +#endif + + dppic00: dppic@42000 { + compatible = "nordic,nrf-dppic"; + reg = <0x42000 0x1000>; + status = "disabled"; + }; + + ppib00: ppib@44000 { + compatible = "nordic,nrf-ppib"; + reg = <0x44000 0x1000>; + status = "disabled"; + }; + + ppib01: ppib@45000 { + compatible = "nordic,nrf-ppib"; + reg = <0x45000 0x1000>; + status = "disabled"; + }; + +#ifdef USE_NON_SECURE_ADDRESS_MAP + /* Intentionally empty because kmu is hardware fixed to Secure */ +#else + kmu: kmu@49000 { + compatible = "nordic,nrf-kmu"; + reg = <0x49000 0x1000>; + status = "disabled"; + }; +#endif + + ccm00: ccm@4a000 { + compatible = "nordic,nrf-ccm"; + reg = <0x4a000 0x1000>; + interrupts = <74 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + }; + + ecb00: ecb@4b000 { + compatible = "nordic,nrf-ecb"; + reg = <0x4b000 0x1000>; + interrupts = <75 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + }; + + cpuflpr_vpr: vpr@4c000{ + compatible = "nordic,nrf-vpr-coprocessor"; + reg = <0x4c000 0x1000>; + ranges = <0x0 0x4c000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + cpuflpr_clic: interrupt-controller@f0000000 { + compatible = "nordic,nrf-clic"; + reg = <0xf0000000 0x1780>; + interrupt-controller; + #interrupt-cells = <2>; + #address-cells = <1>; + status = "disabled"; + }; + }; + + spi00: spi@4d000 { + compatible = "nordic,nrf-spim"; + reg = <0x4d000 0x1000>; + interrupts = <77 NRF_DEFAULT_IRQ_PRIORITY>; + #address-cells = <1>; + #size-cells = <0>; + max-frequency = ; + easydma-maxcnt-bits = <16>; + rx-delay-supported; + rx-delay = <1>; + status = "disabled"; + }; + + uart00: uart@4d000 { + compatible = "nordic,nrf-uarte"; + reg = <0x4d000 0x1000>; + interrupts = <77 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + endtx-stoptx-supported; + frame-timeout-supported; + }; + + gpio2: gpio@50400 { + compatible = "nordic,nrf-gpio"; + reg = <0x50400 0x200>; + gpio-controller; + #gpio-cells = <2>; + port = <2>; + ngpios = <12>; + status = "disabled"; + }; + + ctrlap: ctrlap@52000 { + compatible = "nordic,nrf-ctrlapperi"; + reg = <0x52000 0x1000>; + interrupts = <82 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + }; + + timer00: timer@55000 { + compatible = "nordic,nrf-timer"; + reg = <0x55000 0x1000>; + interrupts = <85 NRF_DEFAULT_IRQ_PRIORITY>; + max-frequency = ; + cc-num = <6>; + max-bit-width = <32>; + prescaler = <0>; + status = "disabled"; + }; + + egu00: egu@58000 { + compatible = "nordic,nrf-egu"; + reg = <0x58000 0x1000>; + interrupts = <88 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + }; + + spi01: spi@5d000 { + compatible = "nordic,nrf-spim"; + reg = <0x5d000 0x1000>; + interrupts = <93 NRF_DEFAULT_IRQ_PRIORITY>; + #address-cells = <1>; + #size-cells = <0>; + max-frequency = ; + easydma-maxcnt-bits = <16>; + rx-delay-supported; + rx-delay = <1>; + status = "disabled"; + }; + +#ifdef USE_NON_SECURE_ADDRESS_MAP + /* Intentionally empty because spu10 is hardware fixed to Secure */ +#else + spu10: spu@80000 { + compatible = "nordic,nrf-spu"; + reg = <0x80000 0x1000>; + interrupts = <128 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + }; +#endif + + dppic10: dppic@82000 { + compatible = "nordic,nrf-dppic"; + reg = <0x82000 0x1000>; + status = "disabled"; + }; + + ppib10: ppib@83000 { + compatible = "nordic,nrf-ppib"; + reg = <0x83000 0x1000>; + status = "disabled"; + }; + + ppib11: ppib@84000 { + compatible = "nordic,nrf-ppib"; + reg = <0x84000 0x1000>; + status = "disabled"; + }; + + timer10: timer@85000 { + compatible = "nordic,nrf-timer"; + reg = <0x85000 0x1000>; + interrupts = <133 NRF_DEFAULT_IRQ_PRIORITY>; + max-frequency = ; + cc-num = <8>; + max-bit-width = <32>; + prescaler = <0>; + status = "disabled"; + }; + + egu10: egu@87000 { + compatible = "nordic,nrf-egu"; + reg = <0x87000 0x1000>; + interrupts = <135 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + }; + + radio: radio@8a000 { + compatible = "nordic,nrf-radio"; + reg = <0x8a000 0x2000>; + interrupts = <138 NRF_DEFAULT_IRQ_PRIORITY>; + dfe-supported; + ieee802154-supported; + ble-2mbps-supported; + ble-coded-phy-supported; + status = "disabled"; + + ieee802154: ieee802154 { + compatible = "nordic,nrf-ieee802154"; + status = "disabled"; + }; + + bt_hci_sdc: bt_hci_sdc { + compatible = "nordic,bt-hci-sdc"; + status = "disabled"; + }; + + bt_hci_controller: bt_hci_controller { + compatible = "zephyr,bt-hci-ll-sw-split"; + status = "disabled"; + }; + + + }; + + ipct10: ipct@8d000 { + compatible = "nordic,nrf-ipct-global"; + reg = <0x8d000 0x1000>; + interrupts = <141 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + }; + +#ifdef USE_NON_SECURE_ADDRESS_MAP + /* Intentionally empty because spu20 is hardware fixed to Secure */ +#else + spu20: spu@c0000 { + compatible = "nordic,nrf-spu"; + reg = <0xc0000 0x1000>; + interrupts = <192 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + }; +#endif + + dppic20: dppic@c2000 { + compatible = "nordic,nrf-dppic"; + reg = <0xc2000 0x1000>; + status = "disabled"; + }; + + ppib20: ppib@c3000 { + compatible = "nordic,nrf-ppib"; + reg = <0xc3000 0x1000>; + status = "disabled"; + }; + + ppib21: ppib@c4000 { + compatible = "nordic,nrf-ppib"; + reg = <0xc4000 0x1000>; + status = "disabled"; + }; + + ppib22: ppib@c5000 { + compatible = "nordic,nrf-ppib"; + reg = <0xc5000 0x1000>; + status = "disabled"; + }; + + spi20: spi@c6000 { + compatible = "nordic,nrf-spim"; + reg = <0xc6000 0x1000>; + interrupts = <198 NRF_DEFAULT_IRQ_PRIORITY>; + #address-cells = <1>; + #size-cells = <0>; + max-frequency = ; + easydma-maxcnt-bits = <16>; + rx-delay-supported; + rx-delay = <1>; + status = "disabled"; + }; + + i2c20: i2c@c6000 { + compatible = "nordic,nrf-twim"; + reg = <0xc6000 0x1000>; + interrupts = <198 NRF_DEFAULT_IRQ_PRIORITY>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = ; + easydma-maxcnt-bits = <16>; + status = "disabled"; + }; + + uart20: uart@c6000 { + compatible = "nordic,nrf-uarte"; + reg = <0xc6000 0x1000>; + interrupts = <198 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + endtx-stoptx-supported; + frame-timeout-supported; + }; + + spi21: spi@c7000 { + compatible = "nordic,nrf-spim"; + reg = <0xc7000 0x1000>; + interrupts = <199 NRF_DEFAULT_IRQ_PRIORITY>; + #address-cells = <1>; + #size-cells = <0>; + max-frequency = ; + easydma-maxcnt-bits = <16>; + rx-delay-supported; + rx-delay = <1>; + status = "disabled"; + }; + + i2c21: i2c@c7000 { + compatible = "nordic,nrf-twim"; + reg = <0xc7000 0x1000>; + interrupts = <199 NRF_DEFAULT_IRQ_PRIORITY>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = ; + easydma-maxcnt-bits = <16>; + status = "disabled"; + }; + + uart21: uart@c7000 { + compatible = "nordic,nrf-uarte"; + reg = <0xc7000 0x1000>; + interrupts = <199 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + endtx-stoptx-supported; + frame-timeout-supported; + }; + + spi22: spi@c8000 { + compatible = "nordic,nrf-spim"; + reg = <0xc8000 0x1000>; + interrupts = <200 NRF_DEFAULT_IRQ_PRIORITY>; + #address-cells = <1>; + #size-cells = <0>; + max-frequency = ; + easydma-maxcnt-bits = <16>; + rx-delay-supported; + rx-delay = <1>; + status = "disabled"; + }; + + i2c22: i2c@c8000 { + compatible = "nordic,nrf-twim"; + reg = <0xc8000 0x1000>; + interrupts = <200 NRF_DEFAULT_IRQ_PRIORITY>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = ; + easydma-maxcnt-bits = <16>; + status = "disabled"; + }; + + uart22: uart@c8000 { + compatible = "nordic,nrf-uarte"; + reg = <0xc8000 0x1000>; + interrupts = <200 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + endtx-stoptx-supported; + frame-timeout-supported; + }; + + egu20: egu@c9000 { + compatible = "nordic,nrf-egu"; + reg = <0xc9000 0x1000>; + interrupts = <201 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + }; + + timer20: timer@ca000 { + compatible = "nordic,nrf-timer"; + reg = <0xca000 0x1000>; + interrupts = <202 NRF_DEFAULT_IRQ_PRIORITY>; + max-frequency = ; + cc-num = <6>; + max-bit-width = <32>; + prescaler = <0>; + status = "disabled"; + }; + + timer21: timer@cb000 { + compatible = "nordic,nrf-timer"; + reg = <0xcb000 0x1000>; + interrupts = <203 NRF_DEFAULT_IRQ_PRIORITY>; + max-frequency = ; + cc-num = <6>; + max-bit-width = <32>; + prescaler = <0>; + status = "disabled"; + }; + + timer22: timer@cc000 { + compatible = "nordic,nrf-timer"; + reg = <0xcc000 0x1000>; + interrupts = <204 NRF_DEFAULT_IRQ_PRIORITY>; + max-frequency = ; + cc-num = <6>; + max-bit-width = <32>; + prescaler = <0>; + status = "disabled"; + }; + + timer23: timer@cd000 { + compatible = "nordic,nrf-timer"; + reg = <0xcd000 0x1000>; + interrupts = <205 NRF_DEFAULT_IRQ_PRIORITY>; + max-frequency = ; + cc-num = <6>; + max-bit-width = <32>; + prescaler = <0>; + status = "disabled"; + }; + + timer24: timer@ce000 { + compatible = "nordic,nrf-timer"; + reg = <0xce000 0x1000>; + interrupts = <206 NRF_DEFAULT_IRQ_PRIORITY>; + max-frequency = ; + cc-num = <6>; + max-bit-width = <32>; + prescaler = <0>; + status = "disabled"; + }; + + pdm20: pdm@d0000 { + compatible = "nordic,nrf-pdm"; + reg = <0xd0000 0x1000>; + interrupts = <208 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + }; + + pdm21: pdm@d1000 { + compatible = "nordic,nrf-pdm"; + reg = <0xd1000 0x1000>; + interrupts = <209 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + }; + + pwm20: pwm@d2000 { + compatible = "nordic,nrf-pwm"; + reg = <0xd2000 0x1000>; + interrupts = <210 NRF_DEFAULT_IRQ_PRIORITY>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm21: pwm@d3000 { + compatible = "nordic,nrf-pwm"; + reg = <0xd3000 0x1000>; + interrupts = <211 NRF_DEFAULT_IRQ_PRIORITY>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm22: pwm@d4000 { + compatible = "nordic,nrf-pwm"; + reg = <0xd4000 0x1000>; + interrupts = <212 NRF_DEFAULT_IRQ_PRIORITY>; + #pwm-cells = <3>; + status = "disabled"; + }; + + adc: adc@d5000 { + compatible = "nordic,nrf-saadc"; + reg = <0xd5000 0x1000>; + interrupts = <213 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + #io-channel-cells = <1>; + }; + + nfct: nfct@d6000 { + compatible = "nordic,nrf-nfct"; + reg = <0xd6000 0x1000>; + interrupts = <214 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + }; + + temp: temp@d7000 { + compatible = "nordic,nrf-temp"; + reg = <0xd7000 0x1000>; + interrupts = <215 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + }; + + gpio1: gpio@d8200 { + compatible = "nordic,nrf-gpio"; + reg = <0xd8200 0x200>; + gpio-controller; + #gpio-cells = <2>; + port = <1>; + ngpios = <20>; + gpiote-instance = <&gpiote20>; + status = "disabled"; + }; + + gpio3: gpio@d8600 { + compatible = "nordic,nrf-gpio"; + reg = <0xd8600 0x200>; + gpio-controller; + #gpio-cells = <2>; + port = <3>; + ngpios = <13>; + gpiote-instance = <&gpiote20>; + status = "disabled"; + }; + + gpio4: gpio@d8800 { + compatible = "nordic,nrf-gpio"; + reg = <0xd8800 0x200>; + gpio-controller; + #gpio-cells = <2>; + port = <4>; + ngpios = <12>; + status = "disabled"; + }; + + gpiote20: gpiote@da000 { + compatible = "nordic,nrf-gpiote"; + reg = <0xda000 0x1000>; + instance = <20>; + status = "disabled"; + }; + + qdec20: qdec@e0000 { + compatible = "nordic,nrf-qdec"; + reg = <0xe0000 0x1000>; + interrupts = <224 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + }; + + qdec21: qdec@e1000 { + compatible = "nordic,nrf-qdec"; + reg = <0xe1000 0x1000>; + interrupts = <225 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + }; + + grtc: grtc@e2000 { + compatible = "nordic,nrf-grtc"; + reg = <0xe2000 0x1000>; + cc-num = <16>; + status = "disabled"; + }; + + spi23: spi@ed000 { + compatible = "nordic,nrf-spim"; + reg = <0xed000 0x1000>; + interrupts = <237 NRF_DEFAULT_IRQ_PRIORITY>; + #address-cells = <1>; + #size-cells = <0>; + max-frequency = ; + easydma-maxcnt-bits = <16>; + rx-delay-supported; + rx-delay = <1>; + status = "disabled"; + }; + + i2c23: i2c@ed000 { + compatible = "nordic,nrf-twim"; + reg = <0xed000 0x1000>; + interrupts = <237 NRF_DEFAULT_IRQ_PRIORITY>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = ; + easydma-maxcnt-bits = <16>; + status = "disabled"; + }; + + uart23: uart@ed000 { + compatible = "nordic,nrf-uarte"; + reg = <0xed000 0x1000>; + interrupts = <237 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + endtx-stoptx-supported; + frame-timeout-supported; + }; + + spi24: spi@ee000 { + compatible = "nordic,nrf-spim"; + reg = <0xee000 0x1000>; + interrupts = <238 NRF_DEFAULT_IRQ_PRIORITY>; + #address-cells = <1>; + #size-cells = <0>; + max-frequency = ; + easydma-maxcnt-bits = <16>; + rx-delay-supported; + rx-delay = <1>; + status = "disabled"; + }; + + i2c24: i2c@ee000 { + compatible = "nordic,nrf-twim"; + reg = <0xee000 0x1000>; + interrupts = <238 NRF_DEFAULT_IRQ_PRIORITY>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = ; + easydma-maxcnt-bits = <16>; + status = "disabled"; + }; + + uart24: uart@ee000 { + compatible = "nordic,nrf-uarte"; + reg = <0xee000 0x1000>; + interrupts = <238 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + endtx-stoptx-supported; + frame-timeout-supported; + }; + +#ifdef USE_NON_SECURE_ADDRESS_MAP + /* Intentionally empty because spu30 is hardware fixed to Secure */ +#else + spu30: spu@100000 { + compatible = "nordic,nrf-spu"; + reg = <0x100000 0x1000>; + interrupts = <256 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + }; +#endif + + dppic30: dppic@102000 { + compatible = "nordic,nrf-dppic"; + reg = <0x102000 0x1000>; + status = "disabled"; + }; + + ppib30: ppib@103000 { + compatible = "nordic,nrf-ppib"; + reg = <0x103000 0x1000>; + status = "disabled"; + }; + + spi30: spi@104000 { + compatible = "nordic,nrf-spim"; + reg = <0x104000 0x1000>; + interrupts = <260 NRF_DEFAULT_IRQ_PRIORITY>; + #address-cells = <1>; + #size-cells = <0>; + max-frequency = ; + easydma-maxcnt-bits = <16>; + rx-delay-supported; + rx-delay = <1>; + status = "disabled"; + }; + + i2c30: i2c@104000 { + compatible = "nordic,nrf-twim"; + reg = <0x104000 0x1000>; + interrupts = <260 NRF_DEFAULT_IRQ_PRIORITY>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = ; + easydma-maxcnt-bits = <16>; + status = "disabled"; + }; + + uart30: uart@104000 { + compatible = "nordic,nrf-uarte"; + reg = <0x104000 0x1000>; + interrupts = <260 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + endtx-stoptx-supported; + frame-timeout-supported; + }; + + comp: comp@106000 { + compatible = "nordic,nrf-comp"; + reg = <0x106000 0x1000>; + interrupts = <262 NRF_DEFAULT_IRQ_PRIORITY>; + #io-channels-cells = <1>; + status = "disabled"; + }; + +#ifdef USE_NON_SECURE_ADDRESS_MAP + /* Intentionally empty because wdt30 is hardware fixed to Secure */ +#else + wdt30: wdt@108000 { + compatible = "nordic,nrf-wdt"; + reg = <0x108000 0x1000>; + interrupts = <264 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + }; +#endif + + wdt31: wdt@109000 { + compatible = "nordic,nrf-wdt"; + reg = <0x109000 0x1000>; + interrupts = <265 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + }; + + gpio0: gpio@10a000 { + compatible = "nordic,nrf-gpio"; + reg = <0x10a000 0x200>; + gpio-controller; + #gpio-cells = <2>; + port = <0>; + ngpios = <10>; + gpiote-instance = <&gpiote30>; + status = "disabled"; + }; + + gpiote30: gpiote@10c000 { + compatible = "nordic,nrf-gpiote"; + reg = <0x10c000 0x1000>; + instance = <30>; + status = "disabled"; + }; + + clock: clock@10e000 { + compatible = "nordic,nrf-clock"; + reg = <0x10e000 0x1000>; + interrupts = <270 NRF_DEFAULT_IRQ_PRIORITY>; + status = "disabled"; + }; + + cpuapp_ppb: cpuapp-ppb-bus { + #address-cells = <1>; + #size-cells = <1>; + + cpuapp_nvic: interrupt-controller@e000e100 { + #address-cells = <1>; + compatible = "arm,v8m-nvic"; + reg = <0xe000e100 0xc00>; + arm,num-irq-priority-bits = <3>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + cpuapp_systick: timer@e000e010 { + compatible = "arm,armv8m-systick"; + reg = <0xe000e010 0x10>; + status = "disabled"; + }; + }; + }; + + wifi_bellboard: mailbox@40074000{ + reg = <0x40074000 0x1000>; + status = "disabled"; + #mbox-cells = <1>; + }; + + cpuapp_bellboard: mailbox@40078000{ + reg = <0x40078000 0x1000>; + status = "disabled"; + #mbox-cells = <1>; + }; + }; +}; diff --git a/dts/arm/nordic/nrf7120_enga_cpuapp.dtsi b/dts/arm/nordic/nrf7120_enga_cpuapp.dtsi new file mode 100644 index 000000000000..2ed356f5dd5b --- /dev/null +++ b/dts/arm/nordic/nrf7120_enga_cpuapp.dtsi @@ -0,0 +1,147 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + */ + + #include + +cpu: &cpuapp {}; +systick: &cpuapp_systick {}; +nvic: &cpuapp_nvic {}; + +/delete-node/ &cpuflpr; +/delete-node/ &cpuflpr_clic; + +/ { + chosen { + zephyr,bt-hci = &bt_hci_sdc; + zephyr,entropy = &psa_rng; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&cpuapp_nvic>; + ranges; + }; + + psa_rng: psa-rng { + compatible = "zephyr,psa-crypto-rng"; + status = "okay"; + }; +}; + +&bt_hci_sdc { + status = "okay"; +}; + +&cpuflpr_vpr { + cpuapp_vevif_rx: mailbox@1 { + compatible = "nordic,nrf-vevif-event-rx"; + reg = <0x0 0x1000>; + status = "disabled"; + interrupts = <76 NRF_DEFAULT_IRQ_PRIORITY>; + #mbox-cells = <1>; + nordic,events = <1>; + nordic,events-mask = <0x00100000>; + }; + + cpuapp_vevif_tx: mailbox@0 { + compatible = "nordic,nrf-vevif-task-tx"; + reg = <0x0 0x1000>; + #mbox-cells = <1>; + nordic,tasks = <7>; + nordic,tasks-mask = <0x007f0000>; + status = "disabled"; + }; +}; + +&cpuapp_ppb { + compatible = "simple-bus"; + ranges; +}; + +&grtc { +#ifdef USE_NON_SECURE_ADDRESS_MAP + interrupts = <227 NRF_DEFAULT_IRQ_PRIORITY>, +#else + interrupts = <228 NRF_DEFAULT_IRQ_PRIORITY>, +#endif + <229 NRF_DEFAULT_IRQ_PRIORITY>; /* reserved for Zero Latency IRQs */ +}; + +&gpiote20 { +#ifdef USE_NON_SECURE_ADDRESS_MAP + interrupts = <218 NRF_DEFAULT_IRQ_PRIORITY>; +#else + interrupts = <219 NRF_DEFAULT_IRQ_PRIORITY>; +#endif +}; + +&gpiote30 { +#ifdef USE_NON_SECURE_ADDRESS_MAP + interrupts = <268 NRF_DEFAULT_IRQ_PRIORITY>; +#else + interrupts = <269 NRF_DEFAULT_IRQ_PRIORITY>; +#endif +}; + +&dppic00 { + status = "okay"; +}; + +&dppic10 { + status = "okay"; +}; + +&dppic20 { + status = "okay"; +}; + +&dppic30 { + status = "okay"; +}; + +&ppib00 { + status = "okay"; +}; + +&ppib01 { + status = "okay"; +}; + +&ppib10 { + status = "okay"; +}; + +&ppib11 { + status = "okay"; +}; + +&ppib20 { + status = "okay"; +}; + +&ppib21 { + status = "okay"; +}; + +&ppib22 { + status = "okay"; +}; + +&ppib30 { + status = "okay"; +}; + +&wifi_bellboard { + compatible = "nordic,nrf-bellboard-tx"; +}; + +&cpuapp_bellboard { + compatible = "nordic,nrf-bellboard-rx"; + interrupts = <120 NRF_DEFAULT_IRQ_PRIORITY>, + <121 NRF_DEFAULT_IRQ_PRIORITY>; + interrupt-names = "irq0", "irq1"; + nordic,interrupt-mapping = <0x0000000f 0>, <0x0000000f 1>; +}; diff --git a/dts/riscv/nordic/nrf7120_enga_cpuflpr.dtsi b/dts/riscv/nordic/nrf7120_enga_cpuflpr.dtsi new file mode 100644 index 000000000000..327b2bd0dca1 --- /dev/null +++ b/dts/riscv/nordic/nrf7120_enga_cpuflpr.dtsi @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + */ + +#include + +cpu: &cpuflpr {}; +clic: &cpuflpr_clic {}; + +/delete-node/ &cpuapp; +/delete-node/ &cpuapp_ppb; +/delete-node/ &cpuapp_sram; +/delete-node/ &cpuapp_mram; + + +/ { + soc { + compatible = "simple-bus"; + interrupt-parent = <&cpuflpr_clic>; + ranges; + }; +}; + +&cpuflpr_vpr { + cpuflpr_vevif_tx: mailbox { + compatible = "nordic,nrf-vevif-event-tx"; + #mbox-cells = <1>; + nordic,events = <1>; + nordic,events-mask = <0x00100000>; + status = "disabled"; + }; +}; + +&cpuflpr_clic { + status = "okay"; +}; + +&wifi_bellboard { + compatible = "nordic,nrf-bellboard-rx"; + interrupts = <116 NRF_DEFAULT_IRQ_PRIORITY>, + <117 NRF_DEFAULT_IRQ_PRIORITY>, + <118 NRF_DEFAULT_IRQ_PRIORITY>, + <119 NRF_DEFAULT_IRQ_PRIORITY>; + interrupt-names = "irq0", "irq1", "irq2", "irq3"; + nordic,interrupt-mapping = <0x0000000f 0>, <0x0000000f 1>, + <0x0000000f 2>, <0x0000000f 3>; +}; + +&cpuapp_bellboard { + compatible = "nordic,nrf-bellboard-tx"; +}; + +&grtc { + interrupts = <226 NRF_DEFAULT_IRQ_PRIORITY>; +}; + +&gpiote20 { + interrupts = <218 NRF_DEFAULT_IRQ_PRIORITY>; +}; + +&gpiote30 { + interrupts = <268 NRF_DEFAULT_IRQ_PRIORITY>; +}; + diff --git a/soc/nordic/CMakeLists.txt b/soc/nordic/CMakeLists.txt new file mode 100644 index 000000000000..4bde2eb7ca01 --- /dev/null +++ b/soc/nordic/CMakeLists.txt @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + +zephyr_library() + +if(CONFIG_ARM) + set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "SoC Linker script") +endif() + + zephyr_library_sources( + ${ZEPHYR_BASE}/soc/nordic/validate_base_addresses.c + ${ZEPHYR_BASE}/soc/nordic/validate_binding_headers.c + ${ZEPHYR_BASE}/soc/nordic/validate_enabled_instances.c + ) + +# Include dt-bindings headers into the build. This lets us validate all required +# DT values against the MDK, without having to conditionally include different +# headers for different SoCs. +set(dt_binding_includes ${DTS_INCLUDE_FILES}) +list(FILTER dt_binding_includes INCLUDE REGEX "/dt-bindings/.*\.h$") +list(TRANSFORM dt_binding_includes PREPEND "-include;") +set_source_files_properties( + validate_binding_headers.c + DIRECTORY ${CMAKE_CURRENT_LIST_DIR} + PROPERTIES COMPILE_OPTIONS "${dt_binding_includes}" +) + +if(CONFIG_SOC_HAS_TIMING_FUNCTIONS AND NOT CONFIG_BOARD_HAS_TIMING_FUNCTIONS) + if(CONFIG_TIMING_FUNCTIONS) + # Use nRF-specific timing calculations only if DWT is not present + if(NOT CONFIG_CORTEX_M_DWT) + zephyr_library_sources(${ZEPHYR_BASE}/soc/nordic/timing.c) + endif() + endif() +endif() + +if(CONFIG_BUILD_WITH_TFM) + set_property(TARGET zephyr_property_target + APPEND PROPERTY TFM_CMAKE_OPTIONS -DHAL_NORDIC_PATH=${ZEPHYR_HAL_NORDIC_MODULE_DIR} + ) + + set_property(TARGET zephyr_property_target + APPEND PROPERTY TFM_CMAKE_OPTIONS -DZEPHYR_BASE=${ZEPHYR_BASE} + ) + + set_property(TARGET zephyr_property_target + APPEND PROPERTY TFM_CMAKE_OPTIONS -DNRF_NS_STORAGE=${CONFIG_TFM_NRF_NS_STORAGE} + ) +endif() + +add_subdirectory(${SOC_SERIES}) +include_directories(${ZEPHYR_BASE}/soc/nordic/common) diff --git a/soc/nordic/Kconfig b/soc/nordic/Kconfig new file mode 100644 index 000000000000..81155d0143e6 --- /dev/null +++ b/soc/nordic/Kconfig @@ -0,0 +1,18 @@ +# Nordic Semiconductor nRFx MCU line + +# Copyright (c) 2016-2018 Nordic Semiconductor ASA +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + +# This file is contains Zephyr build system Kconfig references and is not +# re-usable outside the Zephyr tree. + +config SOC_FAMILY_NORDIC_NRF + select SOC_COMPATIBLE_NRF + select SOC_RESET_HOOK if ARM + +if SOC_FAMILY_NORDIC_NRF + +rsource "*/Kconfig" +source "$ZEPHYR_BASE/soc/nordic/Kconfig" + +endif # SOC_FAMILY_NORDIC_NRF diff --git a/soc/nordic/Kconfig.defconfig b/soc/nordic/Kconfig.defconfig new file mode 100644 index 000000000000..879a7ea083c8 --- /dev/null +++ b/soc/nordic/Kconfig.defconfig @@ -0,0 +1,45 @@ +# Nordic Semiconductor nRFx MCU line + +# Copyright (c) 2016-2018 Nordic Semiconductor ASA +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + +if SOC_FAMILY_NORDIC_NRF + +rsource "*/Kconfig.defconfig" + +# If the kernel has timer support, enable clock control +if SYS_CLOCK_EXISTS + +config CLOCK_CONTROL + default y + +endif # SYS_CLOCK_EXISTS + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 1000000 if NRF_GRTC_TIMER + default 32768 + +config SYS_CLOCK_TICKS_PER_SEC + default 128 if !TICKLESS_KERNEL + default 10000 if NRF_GRTC_TIMER + default 32768 + +config ARCH_HAS_CUSTOM_BUSY_WAIT + default y if ARM && !QEMU_TARGET + +config BUILD_OUTPUT_HEX + default y + +if !CORTEX_M_DWT && NRF_RTC_TIMER +config SOC_HAS_TIMING_FUNCTIONS + default y +endif + +config GPIO + default y + depends on SPI + +config UART_USE_RUNTIME_CONFIGURE + default n + +endif # SOC_FAMILY_NORDIC_NRF diff --git a/soc/nordic/Kconfig.soc b/soc/nordic/Kconfig.soc new file mode 100644 index 000000000000..30db0e972a48 --- /dev/null +++ b/soc/nordic/Kconfig.soc @@ -0,0 +1,20 @@ +# Copyright (c) 2022 Nordic Semiconductor ASA + +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + +config SOC_SERIES + default "nrf71" if SOC_SERIES_NRF71X + +config SOC_FAMILY_NORDIC_NRF + bool + +config SOC_FAMILY + default "nordic_nrf" if SOC_FAMILY_NORDIC_NRF + +config SOC_SERIES_NRF71X + bool + select SOC_FAMILY_NORDIC_NRF + help + Nordic Semiconductor nRF71 series MCU + +rsource "*/Kconfig.soc" diff --git a/soc/nordic/nrf71/CMakeLists.txt b/soc/nordic/nrf71/CMakeLists.txt new file mode 100644 index 000000000000..9949bb50fe92 --- /dev/null +++ b/soc/nordic/nrf71/CMakeLists.txt @@ -0,0 +1,22 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + +zephyr_library_sources( + soc.c + ) +zephyr_include_directories(.) +add_subdirectory(${ZEPHYR_BASE}/soc/nordic/common ${CMAKE_BINARY_DIR}/common) + +# Ensure that image size aligns with 16 bytes so that MRAMC finalizes all writes +# for the image correctly +zephyr_linker_sources(SECTIONS SORT_KEY zzz_place_align_at_end align.ld) + +# We need a buffer in memory in a static location which can be used by +# the KMU peripheral. The KMU has a static destination address, we chose +# this address to be 0x20000000, which is the first address in the SRAM. +if(NOT CONFIG_BUILD_WITH_TFM AND CONFIG_PSA_NEED_CRACEN_KMU_DRIVER) +# Exclamation mark is printable character with the lowest number in ASCII table. +# We are sure that this file will be included first. +zephyr_linker_sources(RAM_SECTIONS SORT_KEY ! kmu_push_area_section.ld) +endif() + diff --git a/soc/nordic/nrf71/Kconfig b/soc/nordic/nrf71/Kconfig new file mode 100644 index 000000000000..df9f73c43e77 --- /dev/null +++ b/soc/nordic/nrf71/Kconfig @@ -0,0 +1,26 @@ +# Nordic Semiconductor nRF71 MCU line + +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + +config SOC_SERIES_NRF71X + select SOC_COMPATIBLE_NRF71X + select HAS_NRFX + select HAS_NORDIC_DRIVERS + select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE + select SOC_EARLY_INIT_HOOK + select SOC_RESET_HOOK + +config SOC_NRF7120_ENGA_CPUAPP + select ARM + select ARMV8_M_DSP + select CPU_CORTEX_M33 + select CPU_HAS_ARM_MPU + select CPU_HAS_ICACHE + select CPU_HAS_ARM_SAU + select CPU_HAS_FPU + select HAS_HW_NRF_RADIO_IEEE802154 + select HAS_POWEROFF + +config SOC_NRF7120_ENGA_CPUFLPR + select RISCV_CORE_NORDIC_VPR diff --git a/soc/nordic/nrf71/Kconfig.defconfig b/soc/nordic/nrf71/Kconfig.defconfig new file mode 100644 index 000000000000..e651c16ae96e --- /dev/null +++ b/soc/nordic/nrf71/Kconfig.defconfig @@ -0,0 +1,28 @@ +# Nordic Semiconductor nRF71 MCU line + +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + +if SOC_SERIES_NRF71X + + rsource "Kconfig.defconfig.nrf71*" + + if ARM + config CORTEX_M_SYSTICK + default !NRF_GRTC_TIMER + + config CACHE_NRF_CACHE + default y if EXTERNAL_CACHE + endif # ARM + + if RISCV + DT_CHOSEN_Z_SRAM = zephyr,sram + DT_CHOSEN_Z_CODE = zephyr,code-partition + + config BUILD_OUTPUT_ADJUST_LMA + depends on !XIP + default "$(dt_chosen_partition_addr_hex,$(DT_CHOSEN_Z_CODE)) - \ + $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_SRAM))" + endif # RISCV + +endif # SOC_SERIES_NRF71X diff --git a/soc/nordic/nrf71/Kconfig.defconfig.nrf7120_enga_cpuapp b/soc/nordic/nrf71/Kconfig.defconfig.nrf7120_enga_cpuapp new file mode 100644 index 000000000000..734ef05a7611 --- /dev/null +++ b/soc/nordic/nrf71/Kconfig.defconfig.nrf7120_enga_cpuapp @@ -0,0 +1,10 @@ +# Nordic Semiconductor nRF7120 MCU + +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + +if SOC_NRF7120_ENGA_CPUAPP +config NUM_IRQS + default 293 + +endif # SOC_NRF7120_ENGA_CPUAPP diff --git a/soc/nordic/nrf71/Kconfig.defconfig.nrf7120_enga_cpuflpr b/soc/nordic/nrf71/Kconfig.defconfig.nrf7120_enga_cpuflpr new file mode 100644 index 000000000000..05bcd6c4ac62 --- /dev/null +++ b/soc/nordic/nrf71/Kconfig.defconfig.nrf7120_enga_cpuflpr @@ -0,0 +1,10 @@ +# Nordic Semiconductor nRF7120 MCU + +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + +if SOC_NRF7120_ENGA_CPUFLPR +config NUM_IRQS + default 293 + +endif # SOC_NRF7120_ENGA_CPUFLPR diff --git a/soc/nordic/nrf71/Kconfig.soc b/soc/nordic/nrf71/Kconfig.soc new file mode 100644 index 000000000000..b6c2db7c7d3d --- /dev/null +++ b/soc/nordic/nrf71/Kconfig.soc @@ -0,0 +1,25 @@ +# Nordic Semiconductor nRF71 MCU line + +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + +config SOC_NRF7120_ENGA + bool + select SOC_SERIES_NRF71X + help + NRF7120_ENGA + +config SOC_NRF7120_ENGA_CPUAPP + bool + select SOC_NRF7120_ENGA + help + NRF7120_ENGA CPUAPP + +config SOC_NRF7120_ENGA_CPUFLPR + bool + select SOC_NRF7120_ENGA + help + NRF7120_ENGA CPUFLPR + +config SOC + default "nrf7120" if SOC_NRF7120_ENGA diff --git a/soc/nordic/nrf71/align.ld b/soc/nordic/nrf71/align.ld new file mode 100644 index 000000000000..6f8b7589b237 --- /dev/null +++ b/soc/nordic/nrf71/align.ld @@ -0,0 +1,10 @@ + +/* + * Copyright (c) 2025 Nordic Semiconductor ASA. + * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + */ +SECTION_PROLOGUE(.align16,,) +{ + . = (ALIGN(16) > 0 ? ALIGN(16) : 16) - 1; + BYTE(0); +} GROUP_LINK_IN(ROMABLE_REGION) diff --git a/soc/nordic/nrf71/kmu_push_area_section.ld b/soc/nordic/nrf71/kmu_push_area_section.ld new file mode 100644 index 000000000000..e8c8cd9f09ad --- /dev/null +++ b/soc/nordic/nrf71/kmu_push_area_section.ld @@ -0,0 +1,19 @@ +# This section must be loaded first of all the +# custom sections because we want it to be placed +# at the top address of RAM. +SECTION_PROLOGUE(NRF_KMU_RESERVED_PUSH_SECTION,(NOLOAD) ,) +{ + __nrf_kmu_reserved_push_area = .; + *(.nrf_kmu_reserved_push_area) + __nrf_kmu_reserved_push_area_end = .; +} GROUP_NOLOAD_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) + +# It doesn't seem to be possible to enforce placing a section +# at a specific address in memory using the Zephyr SECTION macros. +# So this assert is necessary to avoid accidentatly moving this +# section to a different address. +ASSERT(__nrf_kmu_reserved_push_area == RAM_ADDR, "Error: \ + The section NRF_KMU_RESERVED_PUSH_SECTION needs to be \ + placed on the top RAM address but it is not, please edit \ + your linker scripts to make sure that it is placed on \ + the to RAM address.") diff --git a/soc/nordic/nrf71/soc.c b/soc/nordic/nrf71/soc.c new file mode 100644 index 000000000000..87895f152e74 --- /dev/null +++ b/soc/nordic/nrf71/soc.c @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + */ + +/** + * @file + * @brief System/hardware module for Nordic Semiconductor nRF71 family processor + * + * This module provides routines to initialize and support board-level hardware + * for the Nordic Semiconductor nRF71 family processor. + */ + +#ifdef __NRF_TFM__ +#include +#endif + +#include +#include +#include +#include + +#ifndef __NRF_TFM__ +#include +#endif + +#if defined(NRF_APPLICATION) +#include +#include +#endif +#include + +#include + +LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL); + +void soc_early_init_hook(void) +{ + /* Update the SystemCoreClock global variable with current core clock + * retrieved from hardware state. + */ +#if !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) || defined(__NRF_TFM__) + /* Currently not supported for non-secure */ + SystemCoreClockUpdate(); +#endif + +#ifdef __NRF_TFM__ + /* TF-M enables the instruction cache from target_cfg.c, so we + * don't need to enable it here. + */ +#else + /* Enable ICACHE */ + sys_cache_instr_enable(); +#endif + +} + +void arch_busy_wait(uint32_t time_us) +{ + nrfx_coredep_delay_us(time_us); +} + +#ifdef CONFIG_SOC_RESET_HOOK +void soc_reset_hook(void) +{ + SystemInit(); +} +#endif diff --git a/soc/nordic/nrf71/soc.h b/soc/nordic/nrf71/soc.h new file mode 100644 index 000000000000..c3cd276e5f45 --- /dev/null +++ b/soc/nordic/nrf71/soc.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + */ + +/** + * @file SoC configuration macros for the Nordic Semiconductor NRF71 family processors. + */ + +#ifndef _NORDICSEMI_NRF71_SOC_H_ +#define _NORDICSEMI_NRF71_SOC_H_ + +#include + +#define FLASH_PAGE_ERASE_MAX_TIME_US 42000UL +#define FLASH_PAGE_MAX_CNT 381UL + +#endif /* _NORDICSEMI_NRF71_SOC_H_ */ diff --git a/soc/nordic/soc.yml b/soc/nordic/soc.yml new file mode 100644 index 000000000000..3793405664db --- /dev/null +++ b/soc/nordic/soc.yml @@ -0,0 +1,9 @@ +family: + - name: nordic_nrf + series: + - name: nrf71 + socs: + - name: nrf7120_enga + cpuclusters: + - name: cpuapp + - name: cpuflpr diff --git a/zephyr/module.yml b/zephyr/module.yml index 78530759aa8e..e0d797d1aa9c 100644 --- a/zephyr/module.yml +++ b/zephyr/module.yml @@ -4,6 +4,7 @@ build: sysbuild-cmake: sysbuild sysbuild-kconfig: sysbuild/Kconfig.sysbuild settings: + soc_root: . board_root: . dts_root: . module_ext_root: .