diff --git a/www/features.html.in b/www/features.html.in index ea55d59f4..8d522541b 100644 --- a/www/features.html.in +++ b/www/features.html.in @@ -410,4 +410,557 @@ table below. +
+NVC supports the "simple subset" of IEEE 1850-2010. PSL directives may +be written directly in VHDL if using VHDL-2008 or later, or embedded in +comments. Not all features are currently supported, please consult the +table below. +
+ +LRM Section | Feature | Status |
---|---|---|
5 | +Boolean Layer | +|
5.1 | +Boolean expressions | +master | +
5.1.1 | +Bit expressions | +master | +
5.1.2 | +Boolean expressions | +master | +
5.1.3 | +Bit Vector expressions | +master | +
5.1.4 | +Numeric expressions | +master | +
5.1.5 | +String expressions | +master | +
5.2 | +Expression forms | +master | +
5.2.1 | +HDL expressions | +master | +
5.2.2 | +PSL expressions | ++ |
5.2.3 | +Built-in functions | +master | +
5.2.3.1 | +prev() | ++ |
5.2.3.2 | +next() | ++ |
5.2.3.3 | +stable() | ++ |
5.2.3.4 | +rose() | ++ |
5.2.3.5 | +fell() | ++ |
5.2.3.6 | +ended() | ++ |
5.2.3.7 | +isunknown() | +master | +
5.2.3.8 | +countones() | +master | +
5.2.3.9 | +nondet() | ++ |
5.2.3.10 | +nondet_vector() | ++ |
5.2.3.11 | +onehot(), onehot0() | ++ |
5.2.4 | +Union expressions | ++ |
5.3 | +Clock expressions | ++ |
5.4 | +Default clock declaration | +master | +
6 | +Temporal Layer | +|
6.1 | +Sequential Expressions | +master | +
6.1.1 | +Sequential Extended Regular Expressions (SEREs) | +master | +
6.1.1.1 | +Simple SEREs | +master | +
6.1.1.1.1 | +SERE concatenation (;) | +master | +
6.1.1.1.2 | +SERE fusion (:) | +master | +
6.1.1.2 | +Compound SEREs | ++ |
6.1.1.2.1 | +SERE or (|) | ++ |
6.1.1.2.2 | +SERE non-length-matching and (&) | ++ |
6.1.1.2.3 | +SERE length-matching and (&&) | +master | +
6.1.1.2.4 | +SERE within | ++ |
6.1.1.2.5 | +Parameterized SERE | ++ |
6.1.2 | +Sequences | +master | +
6.1.2.1 | +SERE consecutive repetition ([* ]) | +master | +
6.1.2.2 | +SERE non-consecutive repetition ([= ]) | +master | +
6.1.2.3 | +SERE goto repetition ([-> ]) | +master | +
6.1.2.4 | +Braced SERE | +master | +
6.1.2.5 | +Clocked SERE (@) | ++ |
6.2 | +Properties | +master | +
6.2.1 | +FL Properties | +master | +
6.2.1.1 | +Sequential FL Properties | +master | +
6.2.1.2 | +Clocked FL Properties | ++ |
6.2.1.3 | +Simple FL Properties | +master | +
6.2.1.3.1 | +always | +master | +
6.2.1.3.2 | +never | +master | +
6.2.1.3.3 | +eventually! | +master | +
6.2.1.3.4 | +next | +master | +
6.2.1.4 | +Extended next FL Properties | ++ |
6.2.1.4.1 | +next_a | ++ |
6.2.1.4.2 | +next_e | ++ |
6.2.1.4.3 | +next_event | ++ |
6.2.1.4.4 | +next_event_a | ++ |
6.2.1.4.5 | +next_event_e | ++ |
6.2.1.5 | +Compound FL Properties | +master | +
6.2.1.5.1 | +abort, async_abort and sync_abort | +master | +
6.2.1.5.2 | +before | +master | +
6.2.1.5.3 | +until | +master | +
6.2.1.6 | +Sequence-based FL Properties | +master | +
6.2.1.6.1 | +Suffix implication | +master | +
6.2.1.7 | +Logical FL Properties | ++ |
6.2.1.7.1 | +Parametrized property | ++ |
6.2.1.7.2 | +Logical implication | ++ |
6.2.1.7.3 | +Logical iff | ++ |
6.2.1.7.4 | +Logical and | ++ |
6.2.1.7.5 | +Logical or | ++ |
6.2.1.7.6 | +Logical not | ++ |
6.2.1.8 | +LTL operators | ++ |
6.2.2 | +Optional Branching Extension (OBE) properties | +N/A | +
6.2.3 | +Replicated properties | ++ |
6.3 | +Local variables | ++ |
6.4 | +Procedural blocks | ++ |
6.5 | +Property and sequence declarations | ++ |
6.5.1 | +Parameters | ++ |
6.5.1.1 | +PSL formal parameter type classes | ++ |
6.5.1.2 | +HDL formal parameter type classes | ++ |
6.5.2 | +Declarations | ++ |
6.5.2.1 | +Sequence Declarations | ++ |
6.5.2.2 | +Property Declaration | ++ |
6.5.3 | +Instantiation | ++ |
6.5.3.1 | +Sequence instantiation | ++ |
6.5.3.2 | +Property instantiation | ++ |
7 | +Verification Layer | +|
7.1 | +Verification directives | +master | +
7.1.1 | +assert | +master | +
7.1.2 | +assume | ++ |
7.1.3 | +restrict | ++ |
7.1.4 | +restrict! | ++ |
7.1.5 | +cover | +master | +
7.1.6 | +fairness and strong_fairness | ++ |
7.2 | +Verification units | ++ |
7.2.1 | +Verification unit binding | ++ |
7.2.2 | +Verification unit instantiation | ++ |
7.2.3 | +Verification unit inheritance | ++ |
7.2.4 | +Overriding assignments | ++ |
7.2.4.1 | +Simple case | ++ |
7.2.4.2 | +Multiple unrelated vunits | ++ |
7.2.4.3 | +Multiple overrides to the same signal | ++ |
8 | +Modeling layer | +|
8.1 | +Integer ranges | ++ |
8.2 | +Structures | ++ |
8 | +Scope and visibility rules | +|
9.1 | +Immediate scope | ++ |
9.2 | +Extended scope | ++ |
9.3 | +Direct and indirect name references | ++ |