Here are a bunch of SystemVerilog Resources in no particular order:
Please note that some of these teach verilog instead of systemverilog. (Both are essentially the same, but some of the syntax we use in systemverilog is different. However, a lot of the concepts are the same)
- https://hdlbits.01xz.net/wiki/Main_Page
- https://users.ece.cmu.edu/~jhoe/course/ece447/S09handouts/LV.pdf
- https://www.tutorialspoint.com/vlsi_design/vlsi_design_verilog_introduction.htm
- http://www.asic-world.com/verilog/art_testbench_writing.html
- https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=a_short_intro_to_modelsim_verilog_simulator