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ExtractKtaParameters.vhf
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--------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.7
-- \ \ Application : sch2hdl
-- / / Filename : ExtractKtaParameters.vhf
-- /___/ /\ Timestamp : 06/19/2023 15:05:25
-- \ \ / \
-- \___\/\___\
--
--Command: sch2hdl -sympath /home/user/workspace/melexis_mlx90641/ipcore_dir -intstyle ise -family virtex4 -flat -suppress -vhdl /home/user/workspace/melexis_mlx90641/ExtractKtaParameters.vhf -w /home/user/workspace/melexis_mlx90641/ExtractKtaParameters.sch
--Design Name: ExtractKtaParameters
--Device: virtex4
--Purpose:
-- This vhdl netlist is translated from an ECS schematic. It can be
-- synthesized and simulated, but it should not be modified.
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity rom_signed8bit_MUSER_ExtractKtaParameters is
port ( i_clock : in std_logic;
i_reset : in std_logic;
i_value : in std_logic_vector (7 downto 0);
o_value : out std_logic_vector (31 downto 0));
end rom_signed8bit_MUSER_ExtractKtaParameters;
architecture BEHAVIORAL of rom_signed8bit_MUSER_ExtractKtaParameters is
attribute DOA_REG : string ;
attribute DOB_REG : string ;
attribute INIT_00 : string ;
attribute INIT_01 : string ;
attribute INIT_02 : string ;
attribute INIT_03 : string ;
attribute INIT_04 : string ;
attribute INIT_05 : string ;
attribute INIT_06 : string ;
attribute INIT_07 : string ;
attribute INIT_08 : string ;
attribute INIT_09 : string ;
attribute INIT_0A : string ;
attribute INIT_0B : string ;
attribute INIT_0C : string ;
attribute INIT_0D : string ;
attribute INIT_0E : string ;
attribute INIT_0F : string ;
attribute INIT_10 : string ;
attribute INIT_11 : string ;
attribute INIT_12 : string ;
attribute INIT_13 : string ;
attribute INIT_14 : string ;
attribute INIT_15 : string ;
attribute INIT_16 : string ;
attribute INIT_17 : string ;
attribute INIT_18 : string ;
attribute INIT_19 : string ;
attribute INIT_1A : string ;
attribute INIT_1B : string ;
attribute INIT_1C : string ;
attribute INIT_1D : string ;
attribute INIT_1E : string ;
attribute INIT_1F : string ;
attribute INIT_20 : string ;
attribute INIT_21 : string ;
attribute INIT_22 : string ;
attribute INIT_23 : string ;
attribute INIT_24 : string ;
attribute INIT_25 : string ;
attribute INIT_26 : string ;
attribute INIT_27 : string ;
attribute INIT_28 : string ;
attribute INIT_29 : string ;
attribute INIT_2A : string ;
attribute INIT_2B : string ;
attribute INIT_2C : string ;
attribute INIT_2D : string ;
attribute INIT_2E : string ;
attribute INIT_2F : string ;
attribute INIT_30 : string ;
attribute INIT_31 : string ;
attribute INIT_32 : string ;
attribute INIT_33 : string ;
attribute INIT_34 : string ;
attribute INIT_35 : string ;
attribute INIT_36 : string ;
attribute INIT_37 : string ;
attribute INIT_38 : string ;
attribute INIT_39 : string ;
attribute INIT_3A : string ;
attribute INIT_3B : string ;
attribute INIT_3C : string ;
attribute INIT_3D : string ;
attribute INIT_3E : string ;
attribute INIT_3F : string ;
attribute INIT_A : string ;
attribute INIT_B : string ;
attribute INITP_00 : string ;
attribute INITP_01 : string ;
attribute INITP_02 : string ;
attribute INITP_03 : string ;
attribute INITP_04 : string ;
attribute INITP_05 : string ;
attribute INITP_06 : string ;
attribute INITP_07 : string ;
attribute INIT_FILE : string ;
attribute INVERT_CLK_DOA_REG : string ;
attribute INVERT_CLK_DOB_REG : string ;
attribute RAM_EXTENSION_A : string ;
attribute RAM_EXTENSION_B : string ;
attribute READ_WIDTH_A : string ;
attribute READ_WIDTH_B : string ;
attribute SRVAL_A : string ;
attribute SRVAL_B : string ;
attribute WRITE_MODE_A : string ;
attribute WRITE_MODE_B : string ;
attribute WRITE_WIDTH_A : string ;
attribute WRITE_WIDTH_B : string ;
attribute SIM_COLLISION_CHECK : string ;
attribute BOX_TYPE : string ;
signal XLXN_2 : std_logic_vector (14 downto 0);
signal XLXN_13 : std_logic;
signal mem_signed8bit_ADDRB_openSignal : std_logic_vector (14 downto 0);
signal mem_signed8bit_CASCADEINA_openSignal : std_logic;
signal mem_signed8bit_CASCADEINB_openSignal : std_logic;
signal mem_signed8bit_CLKB_openSignal : std_logic;
signal mem_signed8bit_DIA_openSignal : std_logic_vector (31 downto 0);
signal mem_signed8bit_DIB_openSignal : std_logic_vector (31 downto 0);
signal mem_signed8bit_DIPA_openSignal : std_logic_vector (3 downto 0);
signal mem_signed8bit_DIPB_openSignal : std_logic_vector (3 downto 0);
signal mem_signed8bit_ENB_openSignal : std_logic;
signal mem_signed8bit_REGCEA_openSignal : std_logic;
signal mem_signed8bit_REGCEB_openSignal : std_logic;
signal mem_signed8bit_SSRB_openSignal : std_logic;
signal mem_signed8bit_WEA_openSignal : std_logic_vector (3 downto 0);
signal mem_signed8bit_WEB_openSignal : std_logic_vector (3 downto 0);
component RAMB16
-- synopsys translate_off
generic( DOA_REG : integer := 0;
DOB_REG : integer := 0;
INIT_00 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_A : bit_vector := x"000000000";
INIT_B : bit_vector := x"000000000";
INITP_00 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_FILE : string := "NONE";
INVERT_CLK_DOA_REG : boolean := FALSE;
INVERT_CLK_DOB_REG : boolean := FALSE;
RAM_EXTENSION_A : string := "NONE";
RAM_EXTENSION_B : string := "NONE";
READ_WIDTH_A : integer := 0;
READ_WIDTH_B : integer := 0;
SRVAL_A : bit_vector := x"000000000";
SRVAL_B : bit_vector := x"000000000";
WRITE_MODE_A : string := "WRITE_FIRST";
WRITE_MODE_B : string := "WRITE_FIRST";
WRITE_WIDTH_A : integer := 0;
WRITE_WIDTH_B : integer := 0;
SIM_COLLISION_CHECK : string := "ALL");
-- synopsys translate_on
port ( ADDRA : in std_logic_vector (14 downto 0);
ADDRB : in std_logic_vector (14 downto 0);
CASCADEINA : in std_logic;
CASCADEINB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
DIA : in std_logic_vector (31 downto 0);
DIB : in std_logic_vector (31 downto 0);
DIPA : in std_logic_vector (3 downto 0);
DIPB : in std_logic_vector (3 downto 0);
ENA : in std_logic;
REGCEA : in std_logic;
REGCEB : in std_logic;
ENB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
WEA : in std_logic_vector (3 downto 0);
WEB : in std_logic_vector (3 downto 0);
CASCADEOUTA : out std_logic;
CASCADEOUTB : out std_logic;
DOA : out std_logic_vector (31 downto 0);
DOB : out std_logic_vector (31 downto 0);
DOPA : out std_logic_vector (3 downto 0);
DOPB : out std_logic_vector (3 downto 0));
end component;
attribute DOA_REG of RAMB16 : component is "0";
attribute DOB_REG of RAMB16 : component is "0";
attribute INIT_00 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_01 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_02 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_03 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_04 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_05 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_06 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_07 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_08 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_09 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0A of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0B of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0C of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0D of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0E of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0F of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_10 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_11 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_12 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_13 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_14 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_15 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_16 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_17 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_18 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_19 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1A of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1B of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1C of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1D of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1E of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1F of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_20 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_21 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_22 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_23 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_24 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_25 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_26 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_27 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_28 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_29 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2A of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2B of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2C of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2D of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2E of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2F of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_30 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_31 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_32 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_33 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_34 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_35 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_36 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_37 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_38 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_39 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3A of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3B of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3C of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3D of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3E of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3F of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_A of RAMB16 : component is "000000000";
attribute INIT_B of RAMB16 : component is "000000000";
attribute INITP_00 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_01 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_02 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_03 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_04 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_05 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_06 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_07 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_FILE of RAMB16 : component is "NONE";
attribute INVERT_CLK_DOA_REG of RAMB16 : component is "FALSE";
attribute INVERT_CLK_DOB_REG of RAMB16 : component is "FALSE";
attribute RAM_EXTENSION_A of RAMB16 : component is "NONE";
attribute RAM_EXTENSION_B of RAMB16 : component is "NONE";
attribute READ_WIDTH_A of RAMB16 : component is "0";
attribute READ_WIDTH_B of RAMB16 : component is "0";
attribute SRVAL_A of RAMB16 : component is "000000000";
attribute SRVAL_B of RAMB16 : component is "000000000";
attribute WRITE_MODE_A of RAMB16 : component is "WRITE_FIRST";
attribute WRITE_MODE_B of RAMB16 : component is "WRITE_FIRST";
attribute WRITE_WIDTH_A of RAMB16 : component is "0";
attribute WRITE_WIDTH_B of RAMB16 : component is "0";
attribute SIM_COLLISION_CHECK of RAMB16 : component is "ALL";
attribute BOX_TYPE of RAMB16 : component is "BLACK_BOX";
component GND
port ( G : out std_logic);
end component;
attribute BOX_TYPE of GND : component is "BLACK_BOX";
component BUF
port ( I : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of BUF : component is "BLACK_BOX";
component VCC
port ( P : out std_logic);
end component;
attribute BOX_TYPE of VCC : component is "BLACK_BOX";
attribute WRITE_WIDTH_B of mem_signed8bit : label is "36";
attribute WRITE_WIDTH_A of mem_signed8bit : label is "36";
attribute WRITE_MODE_B of mem_signed8bit : label is "READ_FIRST";
attribute WRITE_MODE_A of mem_signed8bit : label is "READ_FIRST";
attribute READ_WIDTH_B of mem_signed8bit : label is "36";
attribute READ_WIDTH_A of mem_signed8bit : label is "36";
attribute INIT_1F of mem_signed8bit : label is
"bf800000c0000000c0400000c0800000c0a00000c0c00000c0e00000c1000000";
attribute INIT_1E of mem_signed8bit : label is
"c1100000c1200000c1300000c1400000c1500000c1600000c1700000c1800000";
attribute INIT_1D of mem_signed8bit : label is
"c1880000c1900000c1980000c1a00000c1a80000c1b00000c1b80000c1c00000";
attribute INIT_1C of mem_signed8bit : label is
"c1c80000c1d00000c1d80000c1e00000c1e80000c1f00000c1f80000c2000000";
attribute INIT_1B of mem_signed8bit : label is
"c2040000c2080000c20c0000c2100000c2140000c2180000c21c0000c2200000";
attribute INIT_1A of mem_signed8bit : label is
"c2240000c2280000c22c0000c2300000c2340000c2380000c23c0000c2400000";
attribute INIT_19 of mem_signed8bit : label is
"c2440000c2480000c24c0000c2500000c2540000c2580000c25c0000c2600000";
attribute INIT_18 of mem_signed8bit : label is
"c2640000c2680000c26c0000c2700000c2740000c2780000c27c0000c2800000";
attribute INIT_17 of mem_signed8bit : label is
"c2820000c2840000c2860000c2880000c28a0000c28c0000c28e0000c2900000";
attribute INIT_16 of mem_signed8bit : label is
"c2920000c2940000c2960000c2980000c29a0000c29c0000c29e0000c2a00000";
attribute INIT_15 of mem_signed8bit : label is
"c2a20000c2a40000c2a60000c2a80000c2aa0000c2ac0000c2ae0000c2b00000";
attribute INIT_14 of mem_signed8bit : label is
"c2b20000c2b40000c2b60000c2b80000c2ba0000c2bc0000c2be0000c2c00000";
attribute INIT_13 of mem_signed8bit : label is
"c2c20000c2c40000c2c60000c2c80000c2ca0000c2cc0000c2ce0000c2d00000";
attribute INIT_12 of mem_signed8bit : label is
"c2d20000c2d40000c2d60000c2d80000c2da0000c2dc0000c2de0000c2e00000";
attribute INIT_11 of mem_signed8bit : label is
"c2e20000c2e40000c2e60000c2e80000c2ea0000c2ec0000c2ee0000c2f00000";
attribute INIT_10 of mem_signed8bit : label is
"c2f20000c2f40000c2f60000c2f80000c2fa0000c2fc0000c2fe0000c3000000";
attribute INIT_0F of mem_signed8bit : label is
"42fe000042fc000042fa000042f8000042f6000042f4000042f2000042f00000";
attribute INIT_0E of mem_signed8bit : label is
"42ee000042ec000042ea000042e8000042e6000042e4000042e2000042e00000";
attribute INIT_0D of mem_signed8bit : label is
"42de000042dc000042da000042d8000042d6000042d4000042d2000042d00000";
attribute INIT_0C of mem_signed8bit : label is
"42ce000042cc000042ca000042c8000042c6000042c4000042c2000042c00000";
attribute INIT_0B of mem_signed8bit : label is
"42be000042bc000042ba000042b8000042b6000042b4000042b2000042b00000";
attribute INIT_0A of mem_signed8bit : label is
"42ae000042ac000042aa000042a8000042a6000042a4000042a2000042a00000";
attribute INIT_09 of mem_signed8bit : label is
"429e0000429c0000429a00004298000042960000429400004292000042900000";
attribute INIT_08 of mem_signed8bit : label is
"428e0000428c0000428a00004288000042860000428400004282000042800000";
attribute INIT_07 of mem_signed8bit : label is
"427c0000427800004274000042700000426c0000426800004264000042600000";
attribute INIT_06 of mem_signed8bit : label is
"425c0000425800004254000042500000424c0000424800004244000042400000";
attribute INIT_05 of mem_signed8bit : label is
"423c0000423800004234000042300000422c0000422800004224000042200000";
attribute INIT_04 of mem_signed8bit : label is
"421c0000421800004214000042100000420c0000420800004204000042000000";
attribute INIT_03 of mem_signed8bit : label is
"41f8000041f0000041e8000041e0000041d8000041d0000041c8000041c00000";
attribute INIT_02 of mem_signed8bit : label is
"41b8000041b0000041a8000041a0000041980000419000004188000041800000";
attribute INIT_01 of mem_signed8bit : label is
"4170000041600000415000004140000041300000412000004110000041000000";
attribute INIT_00 of mem_signed8bit : label is
"40e0000040c0000040a000004080000040400000400000003f80000000000000";
begin
mem_signed8bit : RAMB16
-- synopsys translate_off
generic map( WRITE_WIDTH_B => 36,
WRITE_WIDTH_A => 36,
WRITE_MODE_B => "READ_FIRST",
WRITE_MODE_A => "READ_FIRST",
READ_WIDTH_B => 36,
READ_WIDTH_A => 36,
INIT_1F =>
x"bf800000c0000000c0400000c0800000c0a00000c0c00000c0e00000c1000000",
INIT_1E =>
x"c1100000c1200000c1300000c1400000c1500000c1600000c1700000c1800000",
INIT_1D =>
x"c1880000c1900000c1980000c1a00000c1a80000c1b00000c1b80000c1c00000",
INIT_1C =>
x"c1c80000c1d00000c1d80000c1e00000c1e80000c1f00000c1f80000c2000000",
INIT_1B =>
x"c2040000c2080000c20c0000c2100000c2140000c2180000c21c0000c2200000",
INIT_1A =>
x"c2240000c2280000c22c0000c2300000c2340000c2380000c23c0000c2400000",
INIT_19 =>
x"c2440000c2480000c24c0000c2500000c2540000c2580000c25c0000c2600000",
INIT_18 =>
x"c2640000c2680000c26c0000c2700000c2740000c2780000c27c0000c2800000",
INIT_17 =>
x"c2820000c2840000c2860000c2880000c28a0000c28c0000c28e0000c2900000",
INIT_16 =>
x"c2920000c2940000c2960000c2980000c29a0000c29c0000c29e0000c2a00000",
INIT_15 =>
x"c2a20000c2a40000c2a60000c2a80000c2aa0000c2ac0000c2ae0000c2b00000",
INIT_14 =>
x"c2b20000c2b40000c2b60000c2b80000c2ba0000c2bc0000c2be0000c2c00000",
INIT_13 =>
x"c2c20000c2c40000c2c60000c2c80000c2ca0000c2cc0000c2ce0000c2d00000",
INIT_12 =>
x"c2d20000c2d40000c2d60000c2d80000c2da0000c2dc0000c2de0000c2e00000",
INIT_11 =>
x"c2e20000c2e40000c2e60000c2e80000c2ea0000c2ec0000c2ee0000c2f00000",
INIT_10 =>
x"c2f20000c2f40000c2f60000c2f80000c2fa0000c2fc0000c2fe0000c3000000",
INIT_0F =>
x"42fe000042fc000042fa000042f8000042f6000042f4000042f2000042f00000",
INIT_0E =>
x"42ee000042ec000042ea000042e8000042e6000042e4000042e2000042e00000",
INIT_0D =>
x"42de000042dc000042da000042d8000042d6000042d4000042d2000042d00000",
INIT_0C =>
x"42ce000042cc000042ca000042c8000042c6000042c4000042c2000042c00000",
INIT_0B =>
x"42be000042bc000042ba000042b8000042b6000042b4000042b2000042b00000",
INIT_0A =>
x"42ae000042ac000042aa000042a8000042a6000042a4000042a2000042a00000",
INIT_09 =>
x"429e0000429c0000429a00004298000042960000429400004292000042900000",
INIT_08 =>
x"428e0000428c0000428a00004288000042860000428400004282000042800000",
INIT_07 =>
x"427c0000427800004274000042700000426c0000426800004264000042600000",
INIT_06 =>
x"425c0000425800004254000042500000424c0000424800004244000042400000",
INIT_05 =>
x"423c0000423800004234000042300000422c0000422800004224000042200000",
INIT_04 =>
x"421c0000421800004214000042100000420c0000420800004204000042000000",
INIT_03 =>
x"41f8000041f0000041e8000041e0000041d8000041d0000041c8000041c00000",
INIT_02 =>
x"41b8000041b0000041a8000041a0000041980000419000004188000041800000",
INIT_01 =>
x"4170000041600000415000004140000041300000412000004110000041000000",
INIT_00 =>
x"40e0000040c0000040a000004080000040400000400000003f80000000000000")
-- synopsys translate_on
port map (ADDRA(14 downto 0)=>XLXN_2(14 downto 0),
ADDRB(14 downto 0)=>mem_signed8bit_ADDRB_openSignal(14 downto 0),
CASCADEINA=>mem_signed8bit_CASCADEINA_openSignal,
CASCADEINB=>mem_signed8bit_CASCADEINB_openSignal,
CLKA=>i_clock,
CLKB=>mem_signed8bit_CLKB_openSignal,
DIA(31 downto 0)=>mem_signed8bit_DIA_openSignal(31 downto 0),
DIB(31 downto 0)=>mem_signed8bit_DIB_openSignal(31 downto 0),
DIPA(3 downto 0)=>mem_signed8bit_DIPA_openSignal(3 downto 0),
DIPB(3 downto 0)=>mem_signed8bit_DIPB_openSignal(3 downto 0),
ENA=>XLXN_13,
ENB=>mem_signed8bit_ENB_openSignal,
REGCEA=>mem_signed8bit_REGCEA_openSignal,
REGCEB=>mem_signed8bit_REGCEB_openSignal,
SSRA=>i_reset,
SSRB=>mem_signed8bit_SSRB_openSignal,
WEA(3 downto 0)=>mem_signed8bit_WEA_openSignal(3 downto 0),
WEB(3 downto 0)=>mem_signed8bit_WEB_openSignal(3 downto 0),
CASCADEOUTA=>open,
CASCADEOUTB=>open,
DOA(31 downto 0)=>o_value(31 downto 0),
DOB=>open,
DOPA=>open,
DOPB=>open);
XLXI_3_0 : GND
port map (G=>XLXN_2(13));
XLXI_3_1 : GND
port map (G=>XLXN_2(14));
XLXI_4_0 : GND
port map (G=>XLXN_2(0));
XLXI_4_1 : GND
port map (G=>XLXN_2(1));
XLXI_4_2 : GND
port map (G=>XLXN_2(2));
XLXI_4_3 : GND
port map (G=>XLXN_2(3));
XLXI_4_4 : GND
port map (G=>XLXN_2(4));
XLXI_5_0 : BUF
port map (I=>i_value(0),
O=>XLXN_2(5));
XLXI_5_1 : BUF
port map (I=>i_value(1),
O=>XLXN_2(6));
XLXI_5_2 : BUF
port map (I=>i_value(2),
O=>XLXN_2(7));
XLXI_5_3 : BUF
port map (I=>i_value(3),
O=>XLXN_2(8));
XLXI_5_4 : BUF
port map (I=>i_value(4),
O=>XLXN_2(9));
XLXI_5_5 : BUF
port map (I=>i_value(5),
O=>XLXN_2(10));
XLXI_5_6 : BUF
port map (I=>i_value(6),
O=>XLXN_2(11));
XLXI_5_7 : BUF
port map (I=>i_value(7),
O=>XLXN_2(12));
XLXI_6 : VCC
port map (P=>XLXN_13);
end BEHAVIORAL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity M2_1_MXILINX_ExtractKtaParameters is
port ( D0 : in std_logic;
D1 : in std_logic;
S0 : in std_logic;
O : out std_logic);
end M2_1_MXILINX_ExtractKtaParameters;
architecture BEHAVIORAL of M2_1_MXILINX_ExtractKtaParameters is
attribute BOX_TYPE : string ;
signal M0 : std_logic;
signal M1 : std_logic;
component AND2B1
port ( I0 : in std_logic;
I1 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND2B1 : component is "BLACK_BOX";
component OR2
port ( I0 : in std_logic;
I1 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of OR2 : component is "BLACK_BOX";
component AND2
port ( I0 : in std_logic;
I1 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND2 : component is "BLACK_BOX";
begin
I_36_7 : AND2B1
port map (I0=>S0,
I1=>D0,
O=>M0);
I_36_8 : OR2
port map (I0=>M1,
I1=>M0,
O=>O);
I_36_9 : AND2
port map (I0=>D1,
I1=>S0,
O=>M1);
end BEHAVIORAL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity ExtractKtaParameters is
port ( addfpr : in std_logic_vector (31 downto 0);
addfprdy : in std_logic;
divfpr : in std_logic_vector (31 downto 0);
divfprdy : in std_logic;
i_addr : in std_logic_vector (9 downto 0);
i_clock : in std_logic;
i_reset : in std_logic;
i_run : in std_logic;
i2c_mem_douta : in std_logic_vector (7 downto 0);
mulfpr : in std_logic_vector (31 downto 0);
mulfprdy : in std_logic;
addfpa : out std_logic_vector (31 downto 0);
addfpb : out std_logic_vector (31 downto 0);
addfpce : out std_logic;
addfpond : out std_logic;
addfpsclr : out std_logic;
divfpa : out std_logic_vector (31 downto 0);
divfpb : out std_logic_vector (31 downto 0);
divfpce : out std_logic;
divfpond : out std_logic;
divfpsclr : out std_logic;
i2c_mem_addra : out std_logic_vector (11 downto 0);
i2c_mem_ena : out std_logic;
mulfpa : out std_logic_vector (31 downto 0);
mulfpb : out std_logic_vector (31 downto 0);
mulfpce : out std_logic;
mulfpond : out std_logic;
mulfpsclr : out std_logic;
o_do : out std_logic_vector (31 downto 0);
o_rdy : out std_logic);
end ExtractKtaParameters;
architecture BEHAVIORAL of ExtractKtaParameters is
attribute DOA_REG : string ;
attribute DOB_REG : string ;
attribute INIT_00 : string ;
attribute INIT_01 : string ;
attribute INIT_02 : string ;
attribute INIT_03 : string ;
attribute INIT_04 : string ;
attribute INIT_05 : string ;
attribute INIT_06 : string ;
attribute INIT_07 : string ;
attribute INIT_08 : string ;
attribute INIT_09 : string ;
attribute INIT_0A : string ;
attribute INIT_0B : string ;
attribute INIT_0C : string ;
attribute INIT_0D : string ;
attribute INIT_0E : string ;
attribute INIT_0F : string ;
attribute INIT_10 : string ;
attribute INIT_11 : string ;
attribute INIT_12 : string ;
attribute INIT_13 : string ;
attribute INIT_14 : string ;
attribute INIT_15 : string ;
attribute INIT_16 : string ;
attribute INIT_17 : string ;
attribute INIT_18 : string ;
attribute INIT_19 : string ;
attribute INIT_1A : string ;
attribute INIT_1B : string ;
attribute INIT_1C : string ;
attribute INIT_1D : string ;
attribute INIT_1E : string ;
attribute INIT_1F : string ;
attribute INIT_20 : string ;
attribute INIT_21 : string ;
attribute INIT_22 : string ;
attribute INIT_23 : string ;
attribute INIT_24 : string ;
attribute INIT_25 : string ;
attribute INIT_26 : string ;
attribute INIT_27 : string ;
attribute INIT_28 : string ;
attribute INIT_29 : string ;
attribute INIT_2A : string ;
attribute INIT_2B : string ;
attribute INIT_2C : string ;
attribute INIT_2D : string ;
attribute INIT_2E : string ;
attribute INIT_2F : string ;
attribute INIT_30 : string ;
attribute INIT_31 : string ;
attribute INIT_32 : string ;
attribute INIT_33 : string ;
attribute INIT_34 : string ;
attribute INIT_35 : string ;
attribute INIT_36 : string ;
attribute INIT_37 : string ;
attribute INIT_38 : string ;
attribute INIT_39 : string ;
attribute INIT_3A : string ;
attribute INIT_3B : string ;
attribute INIT_3C : string ;
attribute INIT_3D : string ;
attribute INIT_3E : string ;
attribute INIT_3F : string ;
attribute INIT_A : string ;
attribute INIT_B : string ;
attribute INITP_00 : string ;
attribute INITP_01 : string ;
attribute INITP_02 : string ;
attribute INITP_03 : string ;
attribute INITP_04 : string ;
attribute INITP_05 : string ;
attribute INITP_06 : string ;
attribute INITP_07 : string ;
attribute INIT_FILE : string ;
attribute INVERT_CLK_DOA_REG : string ;
attribute INVERT_CLK_DOB_REG : string ;
attribute RAM_EXTENSION_A : string ;
attribute RAM_EXTENSION_B : string ;
attribute READ_WIDTH_A : string ;
attribute READ_WIDTH_B : string ;
attribute SRVAL_A : string ;
attribute SRVAL_B : string ;
attribute WRITE_MODE_A : string ;
attribute WRITE_MODE_B : string ;
attribute WRITE_WIDTH_A : string ;
attribute WRITE_WIDTH_B : string ;
attribute SIM_COLLISION_CHECK : string ;
attribute BOX_TYPE : string ;
attribute HU_SET : string ;
signal mux_addr1 : std_logic_vector (9 downto
0);
signal o_write_enable : std_logic;
signal XLXN_44 : std_logic_vector (14
downto 0);
signal XLXN_45 : std_logic_vector (14
downto 0);
signal XLXN_59 : std_logic;
signal XLXN_78 : std_logic_vector (31
downto 0);
signal XLXN_79 : std_logic_vector (31
downto 0);
signal XLXN_88 : std_logic_vector (31
downto 0);
signal XLXN_139 : std_logic_vector (3 downto
0);
signal XLXN_173 : std_logic_vector (31
downto 0);
signal XLXN_178 : std_logic_vector (31
downto 0);
signal XLXN_196 : std_logic_vector (7 downto
0);
signal XLXN_197 : std_logic_vector (3 downto
0);
signal XLXN_200 : std_logic_vector (31
downto 0);
signal XLXN_201 : std_logic_vector (3 downto
0);
signal XLXN_235 : std_logic_vector (2 downto
0);
signal XLXN_238 : std_logic_vector (31
downto 0);
signal XLXN_239 : std_logic_vector (0 to 4);
signal XLXN_240 : std_logic_vector (0 to 4);
signal XLXN_243 : std_logic;
signal XLXN_244 : std_logic;
signal XLXN_245 : std_logic_vector (7 downto
0);
signal XLXN_246 : std_logic_vector (7 downto
0);
signal XLXN_247 : std_logic_vector (7 downto
0);
signal XLXN_248 : std_logic_vector (7 downto
0);
signal XLXN_253 : std_logic_vector (7 downto
0);
signal XLXN_254 : std_logic_vector (9 downto
0);
signal o_rdy_DUMMY : std_logic;
signal mem_extrktaparam_1_ADDRB_openSignal : std_logic_vector (14
downto 0);
signal mem_extrktaparam_1_CASCADEINA_openSignal : std_logic;
signal mem_extrktaparam_1_CASCADEINB_openSignal : std_logic;
signal mem_extrktaparam_1_CLKB_openSignal : std_logic;
signal mem_extrktaparam_1_DIB_openSignal : std_logic_vector (31
downto 0);
signal mem_extrktaparam_1_DIPA_openSignal : std_logic_vector (3 downto
0);
signal mem_extrktaparam_1_DIPB_openSignal : std_logic_vector (3 downto
0);
signal mem_extrktaparam_1_ENB_openSignal : std_logic;
signal mem_extrktaparam_1_REGCEA_openSignal : std_logic;
signal mem_extrktaparam_1_REGCEB_openSignal : std_logic;
signal mem_extrktaparam_1_SSRB_openSignal : std_logic;
signal mem_extrktaparam_1_WEB_openSignal : std_logic_vector (3 downto
0);
signal mem_extrktaparam_2_ADDRB_openSignal : std_logic_vector (14
downto 0);
signal mem_extrktaparam_2_CASCADEINA_openSignal : std_logic;