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oceanMusic.ptx
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//
// Generated by NVIDIA NVVM Compiler
//
// Compiler Build ID: CL-24330188
// Cuda compilation tools, release 9.2, V9.2.148
// Based on LLVM 3.4svn
//
.version 6.2
.target sm_30
.address_size 64
// .globl buildFrequencyDataKernel
.const .align 4 .b8 __cudart_i2opi_f[24] = {65, 144, 67, 60, 153, 149, 98, 219, 192, 221, 52, 245, 209, 87, 39, 252, 41, 21, 68, 78, 110, 131, 249, 162};
.visible .entry buildFrequencyDataKernel(
.param .u64 buildFrequencyDataKernel_param_0,
.param .u64 buildFrequencyDataKernel_param_1,
.param .u64 buildFrequencyDataKernel_param_2,
.param .u32 buildFrequencyDataKernel_param_3,
.param .u32 buildFrequencyDataKernel_param_4,
.param .u32 buildFrequencyDataKernel_param_5,
.param .u32 buildFrequencyDataKernel_param_6,
.param .f32 buildFrequencyDataKernel_param_7
)
{
.reg .pred %p<4>;
.reg .f32 %f<5>;
.reg .b32 %r<21>;
.reg .b64 %rd<13>;
ld.param.u64 %rd1, [buildFrequencyDataKernel_param_0];
ld.param.u64 %rd2, [buildFrequencyDataKernel_param_1];
ld.param.u64 %rd3, [buildFrequencyDataKernel_param_2];
ld.param.u32 %r3, [buildFrequencyDataKernel_param_3];
ld.param.u32 %r4, [buildFrequencyDataKernel_param_4];
ld.param.u32 %r5, [buildFrequencyDataKernel_param_5];
mov.u32 %r6, %ctaid.x;
mov.u32 %r7, %ntid.x;
mov.u32 %r8, %tid.x;
mad.lo.s32 %r1, %r7, %r6, %r8;
mov.u32 %r9, %ntid.y;
mov.u32 %r10, %ctaid.y;
mov.u32 %r11, %tid.y;
mad.lo.s32 %r2, %r9, %r10, %r11;
setp.lt.u32 %p1, %r1, %r4;
setp.lt.u32 %p2, %r2, %r5;
and.pred %p3, %p1, %p2;
@!%p3 bra BB0_2;
bra.uni BB0_1;
BB0_1:
shr.u32 %r12, %r3, 1;
add.s32 %r13, %r1, %r12;
rem.u32 %r14, %r13, %r3;
add.s32 %r15, %r14, 1;
cvta.to.global.u64 %rd4, %rd2;
mul.wide.u32 %rd5, %r15, 4;
add.s64 %rd6, %rd4, %rd5;
add.s32 %r16, %r3, -1;
add.s32 %r17, %r2, %r12;
rem.u32 %r18, %r17, %r3;
sub.s32 %r19, %r16, %r18;
cvta.to.global.u64 %rd7, %rd3;
mul.wide.u32 %rd8, %r19, 4;
add.s64 %rd9, %rd7, %rd8;
ld.global.f32 %f1, [%rd9];
ld.global.f32 %f2, [%rd6];
mul.f32 %f3, %f2, %f1;
mad.lo.s32 %r20, %r2, %r4, %r1;
cvta.to.global.u64 %rd10, %rd1;
mul.wide.u32 %rd11, %r20, 8;
add.s64 %rd12, %rd10, %rd11;
mul.f32 %f4, %f3, 0f42C80000;
st.global.v2.f32 [%rd12], {%f4, %f4};
BB0_2:
ret;
}
// .globl buildFrequencyDataKernel2
.visible .entry buildFrequencyDataKernel2(
.param .u64 buildFrequencyDataKernel2_param_0,
.param .u64 buildFrequencyDataKernel2_param_1,
.param .u64 buildFrequencyDataKernel2_param_2,
.param .u32 buildFrequencyDataKernel2_param_3,
.param .u32 buildFrequencyDataKernel2_param_4,
.param .u32 buildFrequencyDataKernel2_param_5,
.param .u32 buildFrequencyDataKernel2_param_6,
.param .f32 buildFrequencyDataKernel2_param_7
)
{
.reg .pred %p<6>;
.reg .f32 %f<12>;
.reg .b32 %r<21>;
.reg .b64 %rd<13>;
ld.param.u64 %rd1, [buildFrequencyDataKernel2_param_0];
ld.param.u64 %rd2, [buildFrequencyDataKernel2_param_1];
ld.param.u64 %rd3, [buildFrequencyDataKernel2_param_2];
ld.param.u32 %r4, [buildFrequencyDataKernel2_param_3];
ld.param.u32 %r5, [buildFrequencyDataKernel2_param_4];
ld.param.u32 %r6, [buildFrequencyDataKernel2_param_5];
mov.u32 %r7, %ctaid.x;
mov.u32 %r8, %ntid.x;
mov.u32 %r9, %tid.x;
mad.lo.s32 %r1, %r8, %r7, %r9;
mov.u32 %r10, %ntid.y;
mov.u32 %r11, %ctaid.y;
mov.u32 %r12, %tid.y;
mad.lo.s32 %r2, %r10, %r11, %r12;
setp.lt.u32 %p1, %r1, %r5;
setp.lt.u32 %p2, %r2, %r6;
and.pred %p3, %p1, %p2;
@!%p3 bra BB1_6;
bra.uni BB1_1;
BB1_1:
shr.u32 %r13, %r4, 1;
add.s32 %r14, %r1, %r13;
rem.u32 %r15, %r14, %r4;
add.s32 %r16, %r15, 1;
cvta.to.global.u64 %rd4, %rd2;
mul.wide.u32 %rd5, %r16, 4;
add.s64 %rd6, %rd4, %rd5;
add.s32 %r17, %r4, -1;
add.s32 %r18, %r2, %r13;
rem.u32 %r19, %r18, %r4;
sub.s32 %r20, %r17, %r19;
cvta.to.global.u64 %rd7, %rd3;
mul.wide.u32 %rd8, %r20, 4;
add.s64 %rd9, %rd7, %rd8;
ld.global.f32 %f5, [%rd9];
ld.global.f32 %f6, [%rd6];
mul.f32 %f7, %f6, %f5;
mul.f32 %f1, %f7, 0f41200000;
setp.gt.f32 %p4, %f1, 0f3F800000;
mad.lo.s32 %r3, %r2, %r5, %r1;
@%p4 bra BB1_4;
bra.uni BB1_2;
BB1_4:
sqrt.rn.f32 %f11, %f1;
bra.uni BB1_5;
BB1_2:
setp.geu.f32 %p5, %f1, 0fBF800000;
@%p5 bra BB1_5;
neg.f32 %f9, %f1;
sqrt.rn.f32 %f10, %f9;
neg.f32 %f11, %f10;
BB1_5:
cvta.to.global.u64 %rd10, %rd1;
mul.wide.u32 %rd11, %r3, 8;
add.s64 %rd12, %rd10, %rd11;
st.global.v2.f32 [%rd12], {%f11, %f11};
BB1_6:
ret;
}
// .globl generateSpectrumKernel
.visible .entry generateSpectrumKernel(
.param .u64 generateSpectrumKernel_param_0,
.param .u64 generateSpectrumKernel_param_1,
.param .u64 generateSpectrumKernel_param_2,
.param .u32 generateSpectrumKernel_param_3,
.param .u32 generateSpectrumKernel_param_4,
.param .u32 generateSpectrumKernel_param_5,
.param .f32 generateSpectrumKernel_param_6,
.param .f32 generateSpectrumKernel_param_7,
.param .f32 generateSpectrumKernel_param_8
)
{
.local .align 4 .b8 __local_depot2[28];
.reg .b64 %SP;
.reg .b64 %SPL;
.reg .pred %p<56>;
.reg .f32 %f<256>;
.reg .b32 %r<397>;
.reg .b64 %rd<67>;
mov.u64 %SPL, __local_depot2;
cvta.local.u64 %SP, %SPL;
ld.param.u64 %rd25, [generateSpectrumKernel_param_0];
ld.param.u64 %rd26, [generateSpectrumKernel_param_1];
ld.param.u64 %rd27, [generateSpectrumKernel_param_2];
ld.param.u32 %r139, [generateSpectrumKernel_param_3];
ld.param.u32 %r140, [generateSpectrumKernel_param_4];
ld.param.u32 %r141, [generateSpectrumKernel_param_5];
ld.param.f32 %f74, [generateSpectrumKernel_param_6];
ld.param.f32 %f73, [generateSpectrumKernel_param_7];
ld.param.f32 %f75, [generateSpectrumKernel_param_8];
mov.u32 %r142, %ntid.x;
mov.u32 %r143, %ctaid.x;
mov.u32 %r144, %tid.x;
mad.lo.s32 %r145, %r142, %r143, %r144;
mov.u32 %r146, %ntid.y;
mov.u32 %r147, %ctaid.y;
mov.u32 %r148, %tid.y;
mad.lo.s32 %r149, %r146, %r147, %r148;
neg.s32 %r150, %r140;
cvt.rn.f32.s32 %f76, %r150;
cvt.rn.f32.u32 %f77, %r145;
fma.rn.f32 %f78, %f76, 0f3F000000, %f77;
mov.f32 %f79, 0f40C90FDB;
div.rn.f32 %f80, %f79, %f75;
mul.f32 %f81, %f78, %f80;
neg.s32 %r151, %r141;
cvt.rn.f32.s32 %f82, %r151;
cvt.rn.f32.u32 %f83, %r149;
fma.rn.f32 %f84, %f82, 0f3F000000, %f83;
mul.f32 %f85, %f80, %f84;
mul.f32 %f86, %f85, %f85;
fma.rn.f32 %f87, %f81, %f81, %f86;
sqrt.rn.f32 %f88, %f87;
mul.f32 %f89, %f88, 0f411CF5C3;
sqrt.rn.f32 %f90, %f89;
mul.f32 %f1, %f90, %f74;
abs.f32 %f2, %f1;
setp.neu.f32 %p1, %f2, 0f7F800000;
mov.f32 %f232, %f1;
@%p1 bra BB2_2;
mov.f32 %f91, 0f00000000;
mul.rn.f32 %f232, %f1, %f91;
BB2_2:
mul.f32 %f92, %f232, 0f3F22F983;
cvt.rni.s32.f32 %r366, %f92;
cvt.rn.f32.s32 %f93, %r366;
neg.f32 %f94, %f93;
mov.f32 %f95, 0f3FC90FDA;
fma.rn.f32 %f96, %f94, %f95, %f232;
mov.f32 %f97, 0f33A22168;
fma.rn.f32 %f98, %f94, %f97, %f96;
mov.f32 %f99, 0f27C234C5;
fma.rn.f32 %f233, %f94, %f99, %f98;
abs.f32 %f100, %f232;
setp.leu.f32 %p2, %f100, 0f47CE4780;
@%p2 bra BB2_13;
mov.b32 %r2, %f232;
shl.b32 %r154, %r2, 8;
or.b32 %r3, %r154, -2147483648;
add.u64 %rd29, %SP, 0;
cvta.to.local.u64 %rd60, %rd29;
mov.u32 %r358, 0;
mov.u64 %rd59, __cudart_i2opi_f;
mov.u32 %r357, -6;
BB2_4:
.pragma "nounroll";
ld.const.u32 %r157, [%rd59];
// inline asm
{
mad.lo.cc.u32 %r155, %r157, %r3, %r358;
madc.hi.u32 %r358, %r157, %r3, 0;
}
// inline asm
st.local.u32 [%rd60], %r155;
add.s64 %rd60, %rd60, 4;
add.s64 %rd59, %rd59, 4;
add.s32 %r357, %r357, 1;
setp.ne.s32 %p3, %r357, 0;
@%p3 bra BB2_4;
bfe.u32 %r160, %r2, 23, 8;
add.s32 %r161, %r160, -128;
shr.u32 %r162, %r161, 5;
and.b32 %r8, %r2, -2147483648;
cvta.to.local.u64 %rd31, %rd29;
st.local.u32 [%rd31+24], %r358;
bfe.u32 %r9, %r2, 23, 5;
mov.u32 %r163, 6;
sub.s32 %r164, %r163, %r162;
mul.wide.s32 %rd32, %r164, 4;
add.s64 %rd6, %rd31, %rd32;
ld.local.u32 %r359, [%rd6];
ld.local.u32 %r360, [%rd6+-4];
setp.eq.s32 %p4, %r9, 0;
@%p4 bra BB2_7;
mov.u32 %r165, 32;
sub.s32 %r166, %r165, %r9;
shr.u32 %r167, %r360, %r166;
shl.b32 %r168, %r359, %r9;
add.s32 %r359, %r167, %r168;
ld.local.u32 %r169, [%rd6+-8];
shr.u32 %r170, %r169, %r166;
shl.b32 %r171, %r360, %r9;
add.s32 %r360, %r170, %r171;
BB2_7:
shr.u32 %r172, %r360, 30;
shl.b32 %r173, %r359, 2;
add.s32 %r361, %r172, %r173;
shl.b32 %r17, %r360, 2;
shr.u32 %r174, %r361, 31;
shr.u32 %r175, %r359, 30;
add.s32 %r18, %r174, %r175;
setp.eq.s32 %p5, %r174, 0;
@%p5 bra BB2_8;
not.b32 %r176, %r361;
neg.s32 %r363, %r17;
setp.eq.s32 %p6, %r17, 0;
selp.u32 %r177, 1, 0, %p6;
add.s32 %r361, %r177, %r176;
xor.b32 %r362, %r8, -2147483648;
bra.uni BB2_10;
BB2_8:
mov.u32 %r362, %r8;
mov.u32 %r363, %r17;
BB2_10:
clz.b32 %r365, %r361;
setp.eq.s32 %p7, %r365, 0;
shl.b32 %r178, %r361, %r365;
mov.u32 %r179, 32;
sub.s32 %r180, %r179, %r365;
shr.u32 %r181, %r363, %r180;
add.s32 %r182, %r181, %r178;
selp.b32 %r26, %r361, %r182, %p7;
mov.u32 %r183, -921707870;
mul.hi.u32 %r364, %r26, %r183;
setp.eq.s32 %p8, %r8, 0;
neg.s32 %r184, %r18;
selp.b32 %r366, %r18, %r184, %p8;
setp.lt.s32 %p9, %r364, 1;
@%p9 bra BB2_12;
mul.lo.s32 %r185, %r26, -921707870;
shr.u32 %r186, %r185, 31;
shl.b32 %r187, %r364, 1;
add.s32 %r364, %r186, %r187;
add.s32 %r365, %r365, 1;
BB2_12:
mov.u32 %r188, 126;
sub.s32 %r189, %r188, %r365;
shl.b32 %r190, %r189, 23;
add.s32 %r191, %r364, 1;
shr.u32 %r192, %r191, 7;
add.s32 %r193, %r192, 1;
shr.u32 %r194, %r193, 1;
add.s32 %r195, %r194, %r190;
or.b32 %r196, %r195, %r362;
mov.b32 %f233, %r196;
BB2_13:
mul.rn.f32 %f8, %f233, %f233;
add.s32 %r34, %r366, 1;
and.b32 %r35, %r34, 1;
setp.eq.s32 %p10, %r35, 0;
@%p10 bra BB2_15;
mov.f32 %f101, 0fBAB6061A;
mov.f32 %f102, 0f37CCF5CE;
fma.rn.f32 %f234, %f102, %f8, %f101;
bra.uni BB2_16;
BB2_15:
mov.f32 %f103, 0f3C08839E;
mov.f32 %f104, 0fB94CA1F9;
fma.rn.f32 %f234, %f104, %f8, %f103;
BB2_16:
@%p10 bra BB2_18;
mov.f32 %f105, 0f3D2AAAA5;
fma.rn.f32 %f106, %f234, %f8, %f105;
mov.f32 %f107, 0fBF000000;
fma.rn.f32 %f235, %f106, %f8, %f107;
bra.uni BB2_19;
BB2_18:
mov.f32 %f108, 0fBE2AAAA3;
fma.rn.f32 %f109, %f234, %f8, %f108;
mov.f32 %f110, 0f00000000;
fma.rn.f32 %f235, %f109, %f8, %f110;
BB2_19:
fma.rn.f32 %f236, %f235, %f233, %f233;
@%p10 bra BB2_21;
mov.f32 %f111, 0f3F800000;
fma.rn.f32 %f236, %f235, %f8, %f111;
BB2_21:
and.b32 %r197, %r34, 2;
setp.eq.s32 %p13, %r197, 0;
@%p13 bra BB2_23;
mov.f32 %f112, 0f00000000;
mov.f32 %f113, 0fBF800000;
fma.rn.f32 %f236, %f236, %f113, %f112;
BB2_23:
mov.f32 %f238, %f1;
@%p1 bra BB2_25;
mov.f32 %f114, 0f00000000;
mul.rn.f32 %f238, %f1, %f114;
BB2_25:
mul.f32 %f115, %f238, 0f3F22F983;
cvt.rni.s32.f32 %r376, %f115;
cvt.rn.f32.s32 %f116, %r376;
neg.f32 %f117, %f116;
fma.rn.f32 %f119, %f117, %f95, %f238;
fma.rn.f32 %f121, %f117, %f97, %f119;
fma.rn.f32 %f239, %f117, %f99, %f121;
abs.f32 %f123, %f238;
setp.leu.f32 %p15, %f123, 0f47CE4780;
@%p15 bra BB2_36;
mov.b32 %r37, %f238;
shl.b32 %r200, %r37, 8;
or.b32 %r38, %r200, -2147483648;
add.u64 %rd34, %SP, 0;
cvta.to.local.u64 %rd62, %rd34;
mov.u32 %r368, 0;
mov.u64 %rd61, __cudart_i2opi_f;
mov.u32 %r367, -6;
BB2_27:
.pragma "nounroll";
ld.const.u32 %r203, [%rd61];
// inline asm
{
mad.lo.cc.u32 %r201, %r203, %r38, %r368;
madc.hi.u32 %r368, %r203, %r38, 0;
}
// inline asm
st.local.u32 [%rd62], %r201;
add.s64 %rd62, %rd62, 4;
add.s64 %rd61, %rd61, 4;
add.s32 %r367, %r367, 1;
setp.ne.s32 %p16, %r367, 0;
@%p16 bra BB2_27;
bfe.u32 %r206, %r37, 23, 8;
add.s32 %r207, %r206, -128;
shr.u32 %r208, %r207, 5;
and.b32 %r43, %r37, -2147483648;
cvta.to.local.u64 %rd36, %rd34;
st.local.u32 [%rd36+24], %r368;
bfe.u32 %r44, %r37, 23, 5;
mov.u32 %r209, 6;
sub.s32 %r210, %r209, %r208;
mul.wide.s32 %rd37, %r210, 4;
add.s64 %rd12, %rd36, %rd37;
ld.local.u32 %r369, [%rd12];
ld.local.u32 %r370, [%rd12+-4];
setp.eq.s32 %p17, %r44, 0;
@%p17 bra BB2_30;
mov.u32 %r211, 32;
sub.s32 %r212, %r211, %r44;
shr.u32 %r213, %r370, %r212;
shl.b32 %r214, %r369, %r44;
add.s32 %r369, %r213, %r214;
ld.local.u32 %r215, [%rd12+-8];
shr.u32 %r216, %r215, %r212;
shl.b32 %r217, %r370, %r44;
add.s32 %r370, %r216, %r217;
BB2_30:
shr.u32 %r218, %r370, 30;
shl.b32 %r219, %r369, 2;
add.s32 %r371, %r218, %r219;
shl.b32 %r52, %r370, 2;
shr.u32 %r220, %r371, 31;
shr.u32 %r221, %r369, 30;
add.s32 %r53, %r220, %r221;
setp.eq.s32 %p18, %r220, 0;
@%p18 bra BB2_31;
not.b32 %r222, %r371;
neg.s32 %r373, %r52;
setp.eq.s32 %p19, %r52, 0;
selp.u32 %r223, 1, 0, %p19;
add.s32 %r371, %r223, %r222;
xor.b32 %r372, %r43, -2147483648;
bra.uni BB2_33;
BB2_31:
mov.u32 %r372, %r43;
mov.u32 %r373, %r52;
BB2_33:
clz.b32 %r375, %r371;
setp.eq.s32 %p20, %r375, 0;
shl.b32 %r224, %r371, %r375;
mov.u32 %r225, 32;
sub.s32 %r226, %r225, %r375;
shr.u32 %r227, %r373, %r226;
add.s32 %r228, %r227, %r224;
selp.b32 %r61, %r371, %r228, %p20;
mov.u32 %r229, -921707870;
mul.hi.u32 %r374, %r61, %r229;
setp.eq.s32 %p21, %r43, 0;
neg.s32 %r230, %r53;
selp.b32 %r376, %r53, %r230, %p21;
setp.lt.s32 %p22, %r374, 1;
@%p22 bra BB2_35;
mul.lo.s32 %r231, %r61, -921707870;
shr.u32 %r232, %r231, 31;
shl.b32 %r233, %r374, 1;
add.s32 %r374, %r232, %r233;
add.s32 %r375, %r375, 1;
BB2_35:
mov.u32 %r234, 126;
sub.s32 %r235, %r234, %r375;
shl.b32 %r236, %r235, 23;
add.s32 %r237, %r374, 1;
shr.u32 %r238, %r237, 7;
add.s32 %r239, %r238, 1;
shr.u32 %r240, %r239, 1;
add.s32 %r241, %r240, %r236;
or.b32 %r242, %r241, %r372;
mov.b32 %f239, %r242;
BB2_36:
mul.rn.f32 %f25, %f239, %f239;
and.b32 %r69, %r376, 1;
setp.eq.s32 %p23, %r69, 0;
@%p23 bra BB2_38;
mov.f32 %f124, 0fBAB6061A;
mov.f32 %f125, 0f37CCF5CE;
fma.rn.f32 %f240, %f125, %f25, %f124;
bra.uni BB2_39;
BB2_38:
mov.f32 %f126, 0f3C08839E;
mov.f32 %f127, 0fB94CA1F9;
fma.rn.f32 %f240, %f127, %f25, %f126;
BB2_39:
@%p23 bra BB2_41;
mov.f32 %f128, 0f3D2AAAA5;
fma.rn.f32 %f129, %f240, %f25, %f128;
mov.f32 %f130, 0fBF000000;
fma.rn.f32 %f241, %f129, %f25, %f130;
bra.uni BB2_42;
BB2_41:
mov.f32 %f131, 0fBE2AAAA3;
fma.rn.f32 %f132, %f240, %f25, %f131;
mov.f32 %f133, 0f00000000;
fma.rn.f32 %f241, %f132, %f25, %f133;
BB2_42:
fma.rn.f32 %f242, %f241, %f239, %f239;
@%p23 bra BB2_44;
mov.f32 %f134, 0f3F800000;
fma.rn.f32 %f242, %f241, %f25, %f134;
BB2_44:
and.b32 %r243, %r376, 2;
setp.eq.s32 %p26, %r243, 0;
@%p26 bra BB2_46;
mov.f32 %f135, 0f00000000;
mov.f32 %f136, 0fBF800000;
fma.rn.f32 %f242, %f242, %f136, %f135;
BB2_46:
neg.f32 %f250, %f1;
abs.f32 %f38, %f250;
setp.neu.f32 %p27, %f38, 0f7F800000;
mov.f32 %f244, %f250;
@%p27 bra BB2_48;
mov.f32 %f137, 0f00000000;
mul.rn.f32 %f244, %f250, %f137;
BB2_48:
mul.f32 %f138, %f244, 0f3F22F983;
cvt.rni.s32.f32 %r386, %f138;
cvt.rn.f32.s32 %f139, %r386;
neg.f32 %f140, %f139;
fma.rn.f32 %f142, %f140, %f95, %f244;
fma.rn.f32 %f144, %f140, %f97, %f142;
fma.rn.f32 %f245, %f140, %f99, %f144;
abs.f32 %f146, %f244;
setp.leu.f32 %p28, %f146, 0f47CE4780;
@%p28 bra BB2_59;
mov.b32 %r71, %f244;
shl.b32 %r246, %r71, 8;
or.b32 %r72, %r246, -2147483648;
add.u64 %rd39, %SP, 0;
cvta.to.local.u64 %rd64, %rd39;
mov.u32 %r378, 0;
mov.u64 %rd63, __cudart_i2opi_f;
mov.u32 %r377, -6;
BB2_50:
.pragma "nounroll";
ld.const.u32 %r249, [%rd63];
// inline asm
{
mad.lo.cc.u32 %r247, %r249, %r72, %r378;
madc.hi.u32 %r378, %r249, %r72, 0;
}
// inline asm
st.local.u32 [%rd64], %r247;
add.s64 %rd64, %rd64, 4;
add.s64 %rd63, %rd63, 4;
add.s32 %r377, %r377, 1;
setp.ne.s32 %p29, %r377, 0;
@%p29 bra BB2_50;
bfe.u32 %r252, %r71, 23, 8;
add.s32 %r253, %r252, -128;
shr.u32 %r254, %r253, 5;
and.b32 %r77, %r71, -2147483648;
cvta.to.local.u64 %rd41, %rd39;
st.local.u32 [%rd41+24], %r378;
bfe.u32 %r78, %r71, 23, 5;
mov.u32 %r255, 6;
sub.s32 %r256, %r255, %r254;
mul.wide.s32 %rd42, %r256, 4;
add.s64 %rd18, %rd41, %rd42;
ld.local.u32 %r379, [%rd18];
ld.local.u32 %r380, [%rd18+-4];
setp.eq.s32 %p30, %r78, 0;
@%p30 bra BB2_53;
mov.u32 %r257, 32;
sub.s32 %r258, %r257, %r78;
shr.u32 %r259, %r380, %r258;
shl.b32 %r260, %r379, %r78;
add.s32 %r379, %r259, %r260;
ld.local.u32 %r261, [%rd18+-8];
shr.u32 %r262, %r261, %r258;
shl.b32 %r263, %r380, %r78;
add.s32 %r380, %r262, %r263;
BB2_53:
shr.u32 %r264, %r380, 30;
shl.b32 %r265, %r379, 2;
add.s32 %r381, %r264, %r265;
shl.b32 %r86, %r380, 2;
shr.u32 %r266, %r381, 31;
shr.u32 %r267, %r379, 30;
add.s32 %r87, %r266, %r267;
setp.eq.s32 %p31, %r266, 0;
@%p31 bra BB2_54;
not.b32 %r268, %r381;
neg.s32 %r383, %r86;
setp.eq.s32 %p32, %r86, 0;
selp.u32 %r269, 1, 0, %p32;
add.s32 %r381, %r269, %r268;
xor.b32 %r382, %r77, -2147483648;
bra.uni BB2_56;
BB2_54:
mov.u32 %r382, %r77;
mov.u32 %r383, %r86;
BB2_56:
clz.b32 %r385, %r381;
setp.eq.s32 %p33, %r385, 0;
shl.b32 %r270, %r381, %r385;
mov.u32 %r271, 32;
sub.s32 %r272, %r271, %r385;
shr.u32 %r273, %r383, %r272;
add.s32 %r274, %r273, %r270;
selp.b32 %r95, %r381, %r274, %p33;
mov.u32 %r275, -921707870;
mul.hi.u32 %r384, %r95, %r275;
setp.eq.s32 %p34, %r77, 0;
neg.s32 %r276, %r87;
selp.b32 %r386, %r87, %r276, %p34;
setp.lt.s32 %p35, %r384, 1;
@%p35 bra BB2_58;
mul.lo.s32 %r277, %r95, -921707870;
shr.u32 %r278, %r277, 31;
shl.b32 %r279, %r384, 1;
add.s32 %r384, %r278, %r279;
add.s32 %r385, %r385, 1;
BB2_58:
mov.u32 %r280, 126;
sub.s32 %r281, %r280, %r385;
shl.b32 %r282, %r281, 23;
add.s32 %r283, %r384, 1;
shr.u32 %r284, %r283, 7;
add.s32 %r285, %r284, 1;
shr.u32 %r286, %r285, 1;
add.s32 %r287, %r286, %r282;
or.b32 %r288, %r287, %r382;
mov.b32 %f245, %r288;
BB2_59:
mul.rn.f32 %f44, %f245, %f245;
add.s32 %r103, %r386, 1;
and.b32 %r104, %r103, 1;
setp.eq.s32 %p36, %r104, 0;
@%p36 bra BB2_61;
mov.f32 %f147, 0fBAB6061A;
mov.f32 %f148, 0f37CCF5CE;
fma.rn.f32 %f246, %f148, %f44, %f147;
bra.uni BB2_62;
BB2_61:
mov.f32 %f149, 0f3C08839E;
mov.f32 %f150, 0fB94CA1F9;
fma.rn.f32 %f246, %f150, %f44, %f149;
BB2_62:
@%p36 bra BB2_64;
mov.f32 %f151, 0f3D2AAAA5;
fma.rn.f32 %f152, %f246, %f44, %f151;
mov.f32 %f153, 0fBF000000;
fma.rn.f32 %f247, %f152, %f44, %f153;
bra.uni BB2_65;
BB2_64:
mov.f32 %f154, 0fBE2AAAA3;
fma.rn.f32 %f155, %f246, %f44, %f154;
mov.f32 %f156, 0f00000000;
fma.rn.f32 %f247, %f155, %f44, %f156;
BB2_65:
fma.rn.f32 %f248, %f247, %f245, %f245;
@%p36 bra BB2_67;
mov.f32 %f157, 0f3F800000;
fma.rn.f32 %f248, %f247, %f44, %f157;
BB2_67:
and.b32 %r289, %r103, 2;
setp.eq.s32 %p39, %r289, 0;
@%p39 bra BB2_69;
mov.f32 %f158, 0f00000000;
mov.f32 %f159, 0fBF800000;
fma.rn.f32 %f248, %f248, %f159, %f158;
BB2_69:
@%p27 bra BB2_71;
mov.f32 %f160, 0f00000000;
mul.rn.f32 %f250, %f250, %f160;
BB2_71:
mul.f32 %f161, %f250, 0f3F22F983;
cvt.rni.s32.f32 %r396, %f161;
cvt.rn.f32.s32 %f162, %r396;
neg.f32 %f163, %f162;
fma.rn.f32 %f165, %f163, %f95, %f250;
fma.rn.f32 %f167, %f163, %f97, %f165;
fma.rn.f32 %f251, %f163, %f99, %f167;
abs.f32 %f169, %f250;
setp.leu.f32 %p41, %f169, 0f47CE4780;
@%p41 bra BB2_82;
mov.b32 %r106, %f250;
shl.b32 %r292, %r106, 8;
or.b32 %r107, %r292, -2147483648;
add.u64 %rd44, %SP, 0;
cvta.to.local.u64 %rd66, %rd44;
mov.u32 %r388, 0;
mov.u64 %rd65, __cudart_i2opi_f;
mov.u32 %r387, -6;
BB2_73:
.pragma "nounroll";
ld.const.u32 %r295, [%rd65];
// inline asm
{
mad.lo.cc.u32 %r293, %r295, %r107, %r388;
madc.hi.u32 %r388, %r295, %r107, 0;
}
// inline asm
st.local.u32 [%rd66], %r293;
add.s64 %rd66, %rd66, 4;
add.s64 %rd65, %rd65, 4;
add.s32 %r387, %r387, 1;
setp.ne.s32 %p42, %r387, 0;
@%p42 bra BB2_73;
bfe.u32 %r298, %r106, 23, 8;
add.s32 %r299, %r298, -128;
shr.u32 %r300, %r299, 5;
and.b32 %r112, %r106, -2147483648;
cvta.to.local.u64 %rd46, %rd44;
st.local.u32 [%rd46+24], %r388;
bfe.u32 %r113, %r106, 23, 5;
mov.u32 %r301, 6;
sub.s32 %r302, %r301, %r300;
mul.wide.s32 %rd47, %r302, 4;
add.s64 %rd24, %rd46, %rd47;
ld.local.u32 %r389, [%rd24];
ld.local.u32 %r390, [%rd24+-4];
setp.eq.s32 %p43, %r113, 0;
@%p43 bra BB2_76;
mov.u32 %r303, 32;
sub.s32 %r304, %r303, %r113;
shr.u32 %r305, %r390, %r304;
shl.b32 %r306, %r389, %r113;
add.s32 %r389, %r305, %r306;
ld.local.u32 %r307, [%rd24+-8];
shr.u32 %r308, %r307, %r304;
shl.b32 %r309, %r390, %r113;
add.s32 %r390, %r308, %r309;
BB2_76:
shr.u32 %r310, %r390, 30;
shl.b32 %r311, %r389, 2;
add.s32 %r391, %r310, %r311;
shl.b32 %r121, %r390, 2;
shr.u32 %r312, %r391, 31;
shr.u32 %r313, %r389, 30;
add.s32 %r122, %r312, %r313;
setp.eq.s32 %p44, %r312, 0;
@%p44 bra BB2_77;
not.b32 %r314, %r391;
neg.s32 %r393, %r121;
setp.eq.s32 %p45, %r121, 0;
selp.u32 %r315, 1, 0, %p45;
add.s32 %r391, %r315, %r314;
xor.b32 %r392, %r112, -2147483648;
bra.uni BB2_79;
BB2_77:
mov.u32 %r392, %r112;
mov.u32 %r393, %r121;
BB2_79:
clz.b32 %r395, %r391;
setp.eq.s32 %p46, %r395, 0;
shl.b32 %r316, %r391, %r395;
mov.u32 %r317, 32;
sub.s32 %r318, %r317, %r395;
shr.u32 %r319, %r393, %r318;
add.s32 %r320, %r319, %r316;
selp.b32 %r130, %r391, %r320, %p46;
mov.u32 %r321, -921707870;
mul.hi.u32 %r394, %r130, %r321;
setp.eq.s32 %p47, %r112, 0;
neg.s32 %r322, %r122;
selp.b32 %r396, %r122, %r322, %p47;
setp.lt.s32 %p48, %r394, 1;
@%p48 bra BB2_81;
mul.lo.s32 %r323, %r130, -921707870;
shr.u32 %r324, %r323, 31;
shl.b32 %r325, %r394, 1;
add.s32 %r394, %r324, %r325;
add.s32 %r395, %r395, 1;
BB2_81:
mov.u32 %r326, 126;
sub.s32 %r327, %r326, %r395;
shl.b32 %r328, %r327, 23;
add.s32 %r329, %r394, 1;
shr.u32 %r330, %r329, 7;
add.s32 %r331, %r330, 1;
shr.u32 %r332, %r331, 1;
add.s32 %r333, %r332, %r328;
or.b32 %r334, %r333, %r392;
mov.b32 %f251, %r334;
BB2_82:
mul.rn.f32 %f61, %f251, %f251;
and.b32 %r138, %r396, 1;
setp.eq.s32 %p49, %r138, 0;
@%p49 bra BB2_84;
mov.f32 %f170, 0fBAB6061A;
mov.f32 %f171, 0f37CCF5CE;
fma.rn.f32 %f252, %f171, %f61, %f170;
bra.uni BB2_85;
BB2_84:
mov.f32 %f172, 0f3C08839E;
mov.f32 %f173, 0fB94CA1F9;
fma.rn.f32 %f252, %f173, %f61, %f172;
BB2_85:
@%p49 bra BB2_87;
mov.f32 %f174, 0f3D2AAAA5;
fma.rn.f32 %f175, %f252, %f61, %f174;
mov.f32 %f176, 0fBF000000;
fma.rn.f32 %f253, %f175, %f61, %f176;
bra.uni BB2_88;
BB2_87:
mov.f32 %f177, 0fBE2AAAA3;
fma.rn.f32 %f178, %f252, %f61, %f177;
mov.f32 %f179, 0f00000000;
fma.rn.f32 %f253, %f178, %f61, %f179;
BB2_88:
fma.rn.f32 %f254, %f253, %f251, %f251;
@%p49 bra BB2_90;
mov.f32 %f180, 0f3F800000;
fma.rn.f32 %f254, %f253, %f61, %f180;
BB2_90:
and.b32 %r335, %r396, 2;
setp.eq.s32 %p52, %r335, 0;
@%p52 bra BB2_92;
mov.f32 %f181, 0f00000000;
mov.f32 %f182, 0fBF800000;
fma.rn.f32 %f254, %f254, %f182, %f181;
BB2_92:
setp.lt.u32 %p53, %r145, %r140;
setp.lt.u32 %p54, %r149, %r141;
and.pred %p55, %p53, %p54;
@!%p55 bra BB2_94;
bra.uni BB2_93;
BB2_93:
cvta.to.global.u64 %rd48, %rd26;
mad.lo.s32 %r352, %r149, %r139, %r145;
cvta.to.global.u64 %rd49, %rd25;
mul.wide.u32 %rd50, %r352, 8;
add.s64 %rd51, %rd49, %rd50;
sub.s32 %r353, %r140, %r145;
sub.s32 %r354, %r141, %r149;
mad.lo.s32 %r355, %r354, %r139, %r353;
mul.wide.u32 %rd52, %r355, 8;
add.s64 %rd53, %rd49, %rd52;
cvta.to.global.u64 %rd54, %rd27;
add.s64 %rd55, %rd54, %rd50;
add.s64 %rd56, %rd54, %rd52;
ld.global.v2.f32 {%f183, %f184}, [%rd51];
mul.f32 %f187, %f236, %f183;
mul.f32 %f188, %f242, %f184;
sub.f32 %f189, %f187, %f188;
mul.f32 %f190, %f236, %f184;
fma.rn.f32 %f191, %f242, %f183, %f190;
ld.global.v2.f32 {%f192, %f193}, [%rd53];
mul.f32 %f196, %f254, %f193;
fma.rn.f32 %f197, %f248, %f192, %f196;
mul.f32 %f198, %f254, %f192;
mul.f32 %f199, %f248, %f193;
sub.f32 %f200, %f198, %f199;
add.f32 %f201, %f189, %f197;
add.f32 %f202, %f191, %f200;
ld.global.v2.f32 {%f203, %f204}, [%rd55];
mul.f32 %f207, %f236, %f203;
mul.f32 %f208, %f242, %f204;
sub.f32 %f209, %f207, %f208;
mul.f32 %f210, %f236, %f204;
fma.rn.f32 %f211, %f242, %f203, %f210;
ld.global.v2.f32 {%f212, %f213}, [%rd56];
mul.f32 %f216, %f254, %f213;
fma.rn.f32 %f217, %f248, %f212, %f216;
mul.f32 %f218, %f254, %f212;
mul.f32 %f219, %f248, %f213;
sub.f32 %f220, %f218, %f219;
add.f32 %f221, %f209, %f217;
add.f32 %f222, %f211, %f220;
mul.f32 %f223, %f201, %f221;
mul.f32 %f224, %f202, %f222;
sub.f32 %f225, %f223, %f224;
mul.f32 %f226, %f202, %f221;
fma.rn.f32 %f227, %f201, %f222, %f226;
mad.lo.s32 %r356, %r149, %r140, %r145;
sub.f32 %f228, %f225, %f201;
sub.f32 %f229, %f227, %f202;
mul.wide.u32 %rd57, %r356, 8;
add.s64 %rd58, %rd48, %rd57;
fma.rn.f32 %f230, %f228, %f73, %f201;
fma.rn.f32 %f231, %f229, %f73, %f202;
st.global.v2.f32 [%rd58], {%f230, %f231};
BB2_94:
ret;
}
// .globl generateSpectrumKernel2