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tjtag.c
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// vim: ts=3:sw=3:expandtab:sts=3
//
// tjtag.c - EJTAG Debrick Utility v3.0.1 - Tornado MOD
// Copyright (C) 2004 HairyDairyMaid (a.k.a. Lightbulb)
// <[email protected]>
// Copyright (C) 2004 William "Bill" Henderson (a.k.a. Tornado)
// <[email protected]>
// Copyright (C) 2013 Mansour Behabadi <[email protected]>
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
// Default is Compile for Linux (both #define's below should be commented out)
//#define WINDOWS_VERSION // uncomment only this for Windows Compile / MS Visual C Compiler
//#define __FreeBSD__ // uncomment only this for FreeBSD
#ifdef WINDOWS_VERSION
#include <windows.h> // Only for Windows Compile
#define strcasecmp stricmp
#define strncasecmp strnicmp
#include <conio.h>
#define _CRT_SECURE_NO_WARNINGS
#endif
#ifdef WINDOWS_VERSION
#define tnano(seconds) Sleep((seconds) / 1000000)
#define tmicro(seconds) Sleep((seconds) * 1000)
/* Windows sleep is milliseconds, time/1000000 gives us nanoseconds */
#else
//ulseep is in microseconds
#define tnano(seconds) sleep((seconds) / 1000000000)
#define tmicro(seconds) usleep(seconds)
#endif
#include <inttypes.h>
#include <ctype.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include <errno.h>
#include <assert.h>
#include "tjtag.h"
#include "spi.h"
#define TRUE 1
#define FALSE 0
#ifdef RASPPI
// I/O access
volatile unsigned *gpio;
#define INP_GPIO(g) *(gpio+((g)/10)) &= ~(7<<(((g)%10)*3))
#define OUT_GPIO(g) *(gpio+((g)/10)) |= (1<<(((g)%10)*3))
#define SET_GPIO_ALT(g,a) *(gpio+(((g)/10))) |= (((a)<=3?(a)+4:(a)==4?3:2)<<(((g)%10)*3))
#define GPIO_SET *(gpio+7) // sets bits which are 1 ignores bits which are 0
#define GPIO_CLR *(gpio+10) // clears bits which are 1 ignores bits which are 0
#define GPIO_GET *(gpio+0xd) // get bits
#endif
static unsigned int ctrl_reg;
volatile unsigned int dcounter;
int pfd;
int instruction_length;
int issue_reset = 1;
int issue_enable_mw = 1;
int issue_watchdog = 1;
int issue_break = 1;
int issue_erase = 1;
int issue_timestamp = 1;
int issue_reboot = 0;
int force_dma = 0;
int force_nodma = 0;
int selected_fc = 0;
unsigned int selected_window = 0;
unsigned int selected_start = 0;
unsigned int selected_length = 0;
int custom_options = 0;
int silent_mode = 0;
int skipdetect = 0;
int instrlen = 0;
int wiggler = 0;
int speedtouch = 0;
int DEBUG = 0;
int Flash_DEBUG = 0;
int probe_options = 0;
unsigned int flash_size = 0;
int block_total = 0;
unsigned int block_addr = 0;
unsigned int cmd_type = 0;
int ejtag_version = 0;
int bypass = 0;
int USE_DMA = 0;
char flash_part[128];
unsigned int blocks[1024];
char AREA_NAME[128];
unsigned int AREA_START;
unsigned int AREA_LENGTH;
unsigned int FLASH_MEMORY_START;
unsigned int vendid;
unsigned int devid;
unsigned int data_register;
unsigned int address_register;
unsigned int proc_id;
unsigned int xbit = 0;
unsigned int delay = 0;
unsigned int bcmproc = 0;
unsigned int swap_endian=0;
unsigned int bigendian=0;
unsigned int spi_flash_read;
unsigned int spi_flash_mmr;
unsigned int spi_flash_mmr_size;
unsigned int spi_flash_ctl;
unsigned int spi_flash_opcode;
unsigned int spi_flash_data;
unsigned int spi_ctl_start;
unsigned int spi_ctl_busy;
#define CID_ID_MASK 0x0000ffff
struct STAT_REG_BITS p;
typedef struct _processor_chip_type
{
unsigned int chip_id; // Processor Chip ID
int instr_length; // EJTAG Instruction Length
char* chip_descr; // Processor Chip Description
} processor_chip_type;
processor_chip_type processor_chip_list[] =
{
{ 0x0471017F, 5, "Broadcom BCM4702 Rev 1 CPU" },
{ 0x9470417F, 8, "Broadcom BCM4704 KPBG Rev 9 CPU"}, // Tornado WRT150N
{ 0x0470417F, 8, "Broadcom BCM4704 Rev 8 CPU" }, // BCM4704 chip (used in the WRTSL54GS units)
{ 0x1471217F, 8, "Broadcom BCM4712 Rev 1 CPU" },
{ 0x2471217F, 8, "Broadcom BCM4712 Rev 2 CPU" },
{ 0x1471617F, 8, "Broadcom BCM4716 Rev 1 CPU" }, // Eko BCM4718A1KFBG
{ 0x0478517F, 8, "Broadcom BCM4785 Rev 1 CPU" }, // Tornado WRT350N
{ 0x0535017F, 8, "Broadcom BCM5350 Rev 1 CPU" },
{ 0x0535217F, 8, "Broadcom BCM5352 Rev 1 CPU" },
{ 0x1535417F, 8, "Broadcom BCM5354 KFBG Rev 1 CPU" }, // Tornado - WRT54G GV8/GSV7
{ 0x2535417F, 8, "Broadcom BCM5354 KFBG Rev 2 CPU" }, // Tornado - Gv8/GSv7
{ 0x3535417F, 8, "Broadcom BCM5354 KFBG Rev 3 CPU" }, // Tornado - WRG54G2
{ 0x0334517F, 5, "Broadcom BCM3345 KPB Rev 1 CPU" }, // Eko QAMLink BCM3345 KPB SB4200
{ 0x0536517F, 8, "Broadcom BCM5365 Rev 1 CPU" }, // BCM5365 Not Completely Verified Yet
{ 0x1536517F, 8, "Broadcom BCM5365 Rev 1 CPU" }, // Eko....ASUS WL 500 G Deluxe
{ 0x0634517F, 5, "Broadcom BCM6345 Rev 1 CPU" }, // BCM6345 Not Completely Verified Yet
{ 0x0634817F, 5, "Broadcom BCM6348 Rev 1 CPU" },
{ 0x0633817F, 5, "Broadcom BCM6338 Rev 1 CPU" }, // Speedtouch
{ 0x0635817F, 5, "Broadcom BCM6358 Rev 1 CPU" }, // brjtag Fully Tested
{ 0x0636817F, 5, "Broadcom BCM6368 Rev 1 CPU" }, // brjtag
{ 0x1432117F, 5, "Broadcom BCM4321 RADIO STOP" }, // Radio JP3 on a WRT300N V1.1
{ 0x3432117F, 5, "Broadcom BCM4321L RADIO STOP"}, // EKO Radio on WRT300n
{ 0x0000100F, 5, "TI AR7 TNETD7x00 Rev 1 CPU" }, // Verified for Linksys ADSL2MUE, same code for 7200 and 7300 chips
{ 0x102002E1, 5, "BRECIS MSP2007-CA-A1 CPU" }, // BRECIS chip - Not Completely Verified Yet
{ 0x0B52D02F, 5, "TI TNETV1060GDW CPU" }, // Fox WRTP54G
{ 0x00217067, 5, "Linkstation 2 with RISC K4C chip" }, // Not verified
{ 0x00000001, 5, "Atheros AR531X/231X CPU" }, // WHR-HP-AG108
{ 0x19277013, 7, "XScale IXP42X 266mhz" }, // GW2348-2 Eko Gateworks Avila GW234X (IXP42X 266MHz) BE
{ 0x19275013, 7, "XScale IXP42X 400mhz" },
{ 0x19274013, 7, "XScale IXP42X 533mhz" },
{ 0x10940027, 4, "ARM 940T"}, // Eko Linksys BEFSX41
{ 0x07926041, 4, "Marvell Feroceon 88F5181" },
{ 0x1438000D, 5, "LX4380"},
{
0, 0, 0
}
};
typedef struct _flash_area_type
{
unsigned int chip_size;
char* area_name;
unsigned int area_start;
unsigned int area_length;
} flash_area_type;
flash_area_type flash_area_list[] =
{
//--------- ---------- ----------- ------------
//chip_size area_name area_start area_length
//--------- ---------- ----------- ------------
{ size1MB, "CFE", 0x1FC00000, 0x40000 },
{ size2MB, "CFE", 0x1FC00000, 0x40000 },
{ size4MB, "CFE", 0x1FC00000, 0x40000 },//256Kb
{ size8MB, "CFE", 0x1C000000, 0x40000 },
{ size16MB, "CFE", 0x1F000000, 0x40000 }, //tornado - for alice
{ size8MB, "AR-CFE", 0xA8000000, 0x40000 },
{ size16MB, "AR-CFE", 0xA8000000, 0x40000 },
{ size1MB, "CFE128", 0x1FC00000, 0x20000 },
{ size2MB, "CFE128", 0x1FC00000, 0x20000 },
{ size4MB, "CFE128", 0x1FC00000, 0x20000 },//128Kb
{ size8MB, "CFE128", 0x1C000000, 0x20000 },
{ size16MB, "CFE128", 0x1C000000, 0x20000 },
{ size1MB, "CF1", 0x1FC00000, 0x2000 },
{ size2MB, "CF1", 0x1FC00000, 0x2000 },
{ size4MB, "CF1", 0x1FC00000, 0x2000 },//8Kb
{ size8MB, "CF1", 0x1C000000, 0x2000 },
{ size16MB, "CF1", 0x1C000000, 0x2000 },
{ size1MB, "KERNEL", 0x1FC40000, 0xB0000 },
{ size2MB, "KERNEL", 0x1FC40000, 0x1B0000 },
{ size4MB, "KERNEL", 0x1FC40000, 0x3B0000 },//3776Kb
{ size8MB, "KERNEL", 0x1C040000, 0x7A0000 },
{ size16MB, "KERNEL", 0x1C040000, 0x7A0000 },
{ size8MB, "AR-KERNEL", 0xA8040000, 0x7A0000 },
{ size16MB, "AR-KERNEL", 0xA8040000, 0x7A0000 },
{ size1MB, "NVRAM", 0x1FCF0000, 0x10000 },
{ size2MB, "NVRAM", 0x1FDF0000, 0x10000 },
{ size4MB, "NVRAM", 0x1FFF0000, 0x10000 },//64kb
{ size8MB, "NVRAM", 0x1C7E0000, 0x20000 },
{ size16MB, "NVRAM", 0x1C7E0000, 0x20000 },
{ size8MB, "AR-NVRAM", 0xA87E0000, 0x20000 },
{ size16MB, "AR-NVRAM", 0xA87E0000, 0x20000 },
{ size2MB, "WGRV9NVRAM", 0x1FDFC000, 0x4000 },
{ size2MB, "WGRV9BDATA", 0x1FDFB000, 0x1000 },
{ size4MB, "WGRV8BDATA", 0x1FFE0000, 0x10000 },//64kb
{ size1MB, "WHOLEFLASH", 0x1FC00000, 0x100000 },
{ size2MB, "WHOLEFLASH", 0x1FC00000, 0x200000 },
{ size4MB, "WHOLEFLASH", 0x1FC00000, 0x400000 },//4Mb
{ size8MB, "WHOLEFLASH", 0x1C000000, 0x800000 },
// { size16MB, "WHOLEFLASH", 0x1C000000, 0x1000000 },
{ size16MB, "WHOLEFLASH", 0x1F000000, 0x1000000 },
{ size8MB, "AR-WHOLEFLASH", 0xA8000000, 0x800000 },
{ size16MB, "AR-WHOLEFLASH", 0xA8000000, 0x1000000 },
{ size1MB, "BSP", 0x1FC00000, 0x50000 },
{ size2MB, "BSP", 0x1FC00000, 0x50000 },
{ size4MB, "BSP", 0x1FC00000, 0x50000 },
{ size8MB, "BSP", 0x1C000000, 0x50000 },
{ size16MB, "BSP", 0x1C000000, 0x50000 },
{ size8MB, "AR-BSP", 0xA8000000, 0x50000 },
{ size16MB, "AR-BSP", 0xA8000000, 0x50000 },
{ size1MB, "RED", 0x50000000, 0x50000 },
{ size2MB, "RED", 0x50000000, 0x50000 },
{ size4MB, "RED", 0x50000000, 0x50000 },
{ size8MB, "AR-RED", 0xA8000000, 0x30000 },
{ size8MB, "RED", 0x50000000, 0x50000 },
{ size16MB, "RED", 0x50000000, 0x50000 },
/* extras for Ti AR7 */
{ size1MB, "MTD2", 0x90000000, 0x10000 },
{ size2MB, "MTD2", 0x90000000, 0x10000 },
{ size4MB, "MTD2", 0x90000000, 0x10000 },
{ size1MB, "MTD3", 0x90010000, 0x10000 },// only for pspboot, its at the other end for adam2
{ size2MB, "MTD3", 0x90010000, 0x10000 },
{ size4MB, "MTD3", 0x90010000, 0x10000 },
{ size1MB, "MTD4", 0x90020000, 0xE0000 },
{ size2MB, "MTD4", 0x90020000, 0x1E0000 },
{ size4MB, "MTD4", 0x90020000, 0x3E0000 },
{ size1MB, "FULL", 0x90020000, 0x100000 },
{ size2MB, "FULL", 0x90020000, 0x200000 },
{ size4MB, "FULL", 0x90020000, 0x400000 },
{ 0, 0, 0, 0 }
};
typedef struct _flash_chip_type
{
unsigned int vendid; // Manufacturer Id
unsigned int devid; // Device Id
unsigned int flash_size; // Total size in MBytes
unsigned int cmd_type; // Device CMD TYPE
char* flash_part; // Flash Chip Description
unsigned int region1_num; // Region 1 block count
unsigned int region1_size; // Region 1 block size
unsigned int region2_num; // Region 2 block count
unsigned int region2_size; // Region 2 block size
unsigned int region3_num; // Region 3 block count
unsigned int region3_size; // Region 3 block size
unsigned int region4_num; // Region 4 block count
unsigned int region4_size; // Region 4 block size
} flash_chip_type;
flash_chip_type flash_chip_list[] =
{
/* AMD, Spansion */
{ 0x00C2, 0x22DA, size1MB, CMD_TYPE_AMD, "MX29LV800BTC 512kx16 TopB (1MB)" ,15,size32K, 1,size16K, 2,size4K, 1,size8K },
{ 0x00C2, 0x225B, size1MB, CMD_TYPE_AMD, "MX29LV800BTC 512kx16 BotB (1MB)" ,1,size8K, 2,size4K, 1,size16K, 15,size32K },
{ 0x0001, 0x2249, size2MB, CMD_TYPE_AMD, "AMD 29lv160DB 1Mx16 BotB (2MB)" ,1,size16K, 2,size8K, 1,size32K, 31,size64K }, /* bypass */
{ 0x0001, 0x22c4, size2MB, CMD_TYPE_AMD, "AMD 29lv160DT 1Mx16 TopB (2MB)" ,31,size64K, 1,size32K, 2,size8K, 1,size16K },
{ 0x007F, 0x2249, size2MB, CMD_TYPE_AMD, "EON EN29LV160A 1Mx16 BotB (2MB)" ,1,size16K, 2,size8K, 1,size32K, 31,size64K }, /* bypass */
{ 0x007F, 0x22C4, size2MB, CMD_TYPE_AMD, "EON EN29LV160A 1Mx16 TopB (2MB)" ,31,size64K, 1,size32K, 2,size8K, 1,size16K },
{ 0x0004, 0x2249, size2MB, CMD_TYPE_AMD, "MBM29LV160B 1Mx16 BotB (2MB)" ,1,size16K, 2,size8K, 1,size32K, 31,size64K },
{ 0x0004, 0x22c4, size2MB, CMD_TYPE_AMD, "MBM29LV160T 1Mx16 TopB (2MB)" ,31,size64K, 1,size32K, 2,size8K, 1,size16K },
{ 0x00C2, 0x2249, size2MB, CMD_TYPE_AMD, "MX29LV160CB 1Mx16 BotB (2MB)" ,1,size16K, 2,size8K, 1,size32K, 31,size64K },
{ 0x00C2, 0x22c4, size2MB, CMD_TYPE_AMD, "MX29LV160CT 1Mx16 TopB (2MB)" ,31,size64K, 1,size32K, 2,size8K, 1,size16K },
{ 0x00EC, 0x2275, size2MB, CMD_TYPE_AMD, "K8D1716UTC 1Mx16 TopB (2MB)" ,31,size64K, 8,size8K, 0,0, 0,0 },
{ 0x00EC, 0x2277, size2MB, CMD_TYPE_AMD, "K8D1716UBC 1Mx16 BotB (2MB)" ,8,size8K, 31,size64K, 0,0, 0,0 }, /* bypass */
{ 0x0020, 0x2249, size2MB, CMD_TYPE_AMD, "ST M29W160EB 1Mx16 BotB (2MB)" ,1,size16K, 2,size8K, 1,size32K, 31,size64K },
{ 0x0020, 0x22c4, size2MB, CMD_TYPE_AMD, "ST M29W160ET 1Mx16 TopB (2MB)" ,31,size64K, 1,size32K, 2,size8K, 1,size16K },
{ 0x00C2, 0x0014, size2MB, CMD_TYPE_SPI, "Macronix MX25L160A (2MB) Serial" ,32,size64K, 0,0, 0,0, 0,0 }, /* new */
{ 0x001f, 0x2600, size2MB, CMD_TYPE_SPI, "Atmel AT45DB161B (2MB) Serial" ,512,sizeA4K, 0,0, 0,0, 0,0 }, /* new */
{ 0x0040, 0x0000, size2MB, CMD_TYPE_SPI, "Atmel AT45DB161B (2MB) Serial" ,512,sizeA4K, 0,0, 0,0, 0,0 }, /* new */
{ 0x00EC, 0x22A0, size4MB, CMD_TYPE_AMD, "K8D3216UTC 2Mx16 TopB (4MB)" ,63,size64K, 8,size8K, 0,0, 0,0 },
{ 0x00EC, 0x22A2, size4MB, CMD_TYPE_AMD, "K8D3216UBC 2Mx16 BotB (4MB)" ,8,size8K, 63,size64K, 0,0, 0,0 },
{ 0x00C2, 0x2015, size2MB, CMD_TYPE_SPI, "Macronix MX25L1605D (2MB) Serial" ,32,size64K, 0,0, 0,0, 0,0 }, /* new */
{ 0x00C2, 0x2016, size4MB, CMD_TYPE_SPI, "Macronix MX25L3205D (4MB) Serial" ,64,size64K, 0,0, 0,0, 0,0 }, /* new */
{ 0x00C2, 0x2017, size8MB, CMD_TYPE_SPI, "Macronix MX25L6405D (8MB) Serial" ,128,size64K, 0,0, 0,0, 0,0 }, /* new */
{ 0x0020, 0x2015, size2MB, CMD_TYPE_SPI, "STMicro M25P16 (2MB) Serial" ,32,size64K, 0,0, 0,0, 0,0 }, /* new */
{ 0x0020, 0x2016, size4MB, CMD_TYPE_SPI, "STMicro M25P32 (4MB) Serial" ,64,size64K, 0,0, 0,0, 0,0 }, /* new */
{ 0x0020, 0x2017, size8MB, CMD_TYPE_SPI, "STMicro M25P64 (8MB) Serial" ,128,size64K, 0,0, 0,0, 0,0 }, /* new */
{ 0x0020, 0x2018, size16MB, CMD_TYPE_SPI, "STMicro M25P128 (16MB) Serial" ,32,size256K, 0,0, 0,0, 0,0 }, /* new */
{ 0x0001, 0x2200, size4MB, CMD_TYPE_AMD, "AMD 29lv320MB 2Mx16 BotB (4MB)" ,8,size8K, 63,size64K, 0,0, 0,0 },
{ 0x0001, 0x227E, size4MB, CMD_TYPE_AMD, "AMD 29lv320MT 2Mx16 TopB (4MB)" ,63,size64K, 8,size8K, 0,0, 0,0 },
{ 0x0001, 0x2201, size4MB, CMD_TYPE_AMD, "AMD 29lv320MT 2Mx16 TopB (4MB)" ,63,size64K, 8,size8K, 0,0, 0,0 },
{ 0x0098, 0x009C, size4MB, CMD_TYPE_AMD, "TC58FVB321 2Mx16 BotB (4MB)" ,1,size16K, 2,size8K, 1,size32K, 63,size64K },
{ 0x0098, 0x009A, size4MB, CMD_TYPE_AMD, "TC58FVT321 2Mx16 TopB (4MB)" ,63,size64K, 1,size32K, 2,size8K, 1,size16K },
{ 0x001F, 0x00C0, size4MB, CMD_TYPE_AMD, "AT49BV/LV16X 2Mx16 BotB (4MB)" ,8,size8K, 63,size64K, 0,0, 0,0 },
{ 0x001F, 0x00C2, size4MB, CMD_TYPE_AMD, "AT49BV/LV16XT 2Mx16 TopB (4MB)" ,63,size64K, 8,size8K, 0,0, 0,0 },
{ 0x0004, 0x2253, size4MB, CMD_TYPE_AMD, "MBM29DL323BE 2Mx16 BotB (4MB)" ,8,size8K, 63,size64K, 0,0, 0,0 },
{ 0x0004, 0x2250, size4MB, CMD_TYPE_AMD, "MBM29DL323TE 2Mx16 TopB (4MB)" ,63,size64K, 8,size8K, 0,0, 0,0 },
{ 0x0001, 0x22f9, size4MB, CMD_TYPE_AMD, "AMD 29lv320DB 2Mx16 BotB (4MB)" ,8,size8K, 63,size64K, 0,0, 0,0 },
{ 0x0001, 0x22f6, size4MB, CMD_TYPE_AMD, "AMD 29lv320DT 2Mx16 TopB (4MB)" ,63,size64K, 8,size8K, 0,0, 0,0 },
{ 0x0004, 0x22F9, size4MB, CMD_TYPE_AMD, "MBM29LV320BE 2Mx16 BotB (4MB)" ,1,size16K, 2,size8K, 1,size32K, 63,size64K },
{ 0x0004, 0x22F6, size4MB, CMD_TYPE_AMD, "MBM29LV320TE 2Mx16 TopB (4MB)" ,63,size64K, 1,size32K, 2,size8K, 1,size16K },
{ 0x00C2, 0x22A8, size4MB, CMD_TYPE_AMD, "MX29LV320B 2Mx16 BotB (4MB)" ,8,size8K, 63,size64K, 0,0, 0,0 },
{ 0x00C2, 0x00A8, size4MB, CMD_TYPE_AMD, "MX29LV320B 2Mx16 BotB (4MB)" ,8,size8K, 63,size64K, 0,0, 0,0 },
{ 0x00C2, 0x00A7, size4MB, CMD_TYPE_AMD, "MX29LV320T 2Mx16 TopB (4MB)" ,63,size64K, 8,size8K, 0,0, 0,0 },
{ 0x00C2, 0x22A7, size4MB, CMD_TYPE_AMD, "MX29LV320T 2Mx16 TopB (4MB)" ,63,size64K, 8,size8K, 0,0, 0,0 },
{ 0x0020, 0x22CB, size4MB, CMD_TYPE_AMD, "ST 29w320DB 2Mx16 BotB (4MB)" ,1,size16K, 2,size8K, 1,size32K, 63,size64K },
{ 0x0020, 0x22CA, size4MB, CMD_TYPE_AMD, "ST 29w320DT 2Mx16 TopB (4MB)" ,63,size64K, 1,size32K, 2,size8K, 1,size16K },
{ 0x00C2, 0x22C9, size16MB, CMD_TYPE_AMD, "MX29LV640B 4Mx16 TopB (16MB)" ,127,size64K, 8,size8K, 0,0, 0,0 },
{ 0x00C2, 0x22CB, size16MB, CMD_TYPE_AMD, "MX29LV640B 4Mx16 BotB (16MB)" ,8,size8K, 127,size64K, 0,0, 0,0 },
{ 0x00DA, 0x22BA, size4MB, CMD_TYPE_AMD, "W19B(L)320ST 2Mx16 TopB (4MB)" ,63,size64K, 8,size8K, 0,0, 0,0 }, /* new */
{ 0x00DA, 0x222A, size4MB, CMD_TYPE_AMD, "W19B(L)320SB 2Mx16 BotB (4MB)" ,8,size8K, 63,size64K, 0,0, 0,0 }, /* new */
{ 0x22DA, 0x222A, size4MB, CMD_TYPE_AMD, "W19B(L)320SB 2Mx16 BotB (4MB)" ,8,size8K, 63,size64K, 0,0, 0,0 },
{ 0x0020, 0x225C, size4MB, CMD_TYPE_AMD, "M29DW324DT 2Mx16 TopB (4MB)" ,63,size64K, 8,size8K, 0,0, 0,0 }, /* new */
{ 0x0020, 0x225D, size4MB, CMD_TYPE_AMD, "M29DW324DB 2Mx16 BotB (4MB)" ,8,size8K, 63,size64K, 0,0, 0,0 }, /* new */
{ 0x0098, 0x0057, size8MB, CMD_TYPE_AMD, "TC58FVM6T2A 4Mx16 TopB (8MB)" ,127,size64K, 8,size8K, 0,0, 0,0 }, /* new */
{ 0x0098, 0x0058, size8MB, CMD_TYPE_AMD, "TC58FVM6B2A 4Mx16 BopB (8MB)" ,8,size8K, 127,size64K, 0,0, 0,0 }, /* new */
{ 0x00EC, 0x22E0, size8MB, CMD_TYPE_AMD, "K8D6316UTM 4Mx16 TopB (8MB)" ,127,size64K, 8,size8K, 0,0, 0,0 }, /* new */
{ 0x00EC, 0x22E2, size8MB, CMD_TYPE_AMD, "K8D6316UBM 4Mx16 BotB (8MB)" ,8,size8K, 127,size64K, 0,0, 0,0 }, /* new */
/* BSC */
{ 0x0089, 0x8891, size2MB, CMD_TYPE_BSC, "Intel 28F160B3 1Mx16 BotB (2MB)" ,8,size8K, 31,size64K, 0,0, 0,0 },
{ 0x0089, 0x8890, size2MB, CMD_TYPE_BSC, "Intel 28F160B3 1Mx16 TopB (2MB)" ,31,size64K, 8,size8K, 0,0, 0,0 },
{ 0x0089, 0x88C3, size2MB, CMD_TYPE_BSC, "Intel 28F160C3 1Mx16 BotB (2MB)" ,8,size8K, 31,size64K, 0,0, 0,0 },
{ 0x0089, 0x88C2, size2MB, CMD_TYPE_BSC, "Intel 28F160C3 1Mx16 TopB (2MB)" ,31,size64K, 8,size8K, 0,0, 0,0 },
{ 0x0089, 0x8897, size4MB, CMD_TYPE_BSC, "Intel 28F320B3 2Mx16 BotB (4MB)" ,8,size8K, 63,size64K, 0,0, 0,0 },
{ 0x0089, 0x8896, size4MB, CMD_TYPE_BSC, "Intel 28F320B3 2Mx16 TopB (4MB)" ,63,size64K, 8,size8K, 0,0, 0,0 },
{ 0x0089, 0x88C5, size4MB, CMD_TYPE_BSC, "Intel 28F320C3 2Mx16 BotB (4MB)" ,8,size8K, 63,size64K, 0,0, 0,0 },
{ 0x0089, 0x88C4, size4MB, CMD_TYPE_BSC, "Intel 28F320C3 2Mx16 TopB (4MB)" ,63,size64K, 8,size8K, 0,0, 0,0 },
{ 0x00b0, 0x00e3, size4MB, CMD_TYPE_BSC, "Sharp 28F320BJE 2Mx16 BotB (4MB)" ,8,size8K, 63,size64K, 0,0, 0,0 },
{ 0x0089, 0x8899, size8MB, CMD_TYPE_BSC, "Intel 28F640B3 4Mx16 BotB (8MB)" ,8,size8K, 127,size64K, 0,0, 0,0 },
{ 0x0089, 0x8898, size8MB, CMD_TYPE_BSC, "Intel 28F640B3 4Mx16 TopB (8MB)" ,127,size64K, 8,size8K, 0,0, 0,0 },
{ 0x0089, 0x88CD, size8MB, CMD_TYPE_BSC, "Intel 28F640C3 4Mx16 BotB (8MB)" ,8,size8K, 127,size64K, 0,0, 0,0 },
{ 0x0089, 0x88CC, size8MB, CMD_TYPE_BSC, "Intel 28F640C3 4Mx16 TopB (8MB)" ,127,size64K, 8,size8K, 0,0, 0,0 },
/* SCS */
{ 0x00b0, 0x00d0, size2MB, CMD_TYPE_SCS, "Intel 28F160S3/5 1Mx16 (2MB)" ,32,size64K, 0,0, 0,0, 0,0 },
{ 0x0089, 0x0016, size4MB, CMD_TYPE_SCS, "Intel 28F320J3 2Mx16 (4MB)" ,32,size128K, 0,0, 0,0, 0,0 },
{ 0x0089, 0x0014, size4MB, CMD_TYPE_SCS, "Intel 28F320J5 2Mx16 (4MB)" ,32,size128K, 0,0, 0,0, 0,0 },
{ 0x00b0, 0x00d4, size4MB, CMD_TYPE_SCS, "Intel 28F320S3/5 2Mx16 (4MB)" ,64,size64K, 0,0, 0,0, 0,0 },
{ 0x0089, 0x0017, size8MB, CMD_TYPE_SCS, "Intel 28F640J3 4Mx16 (8MB)" ,64,size128K, 0,0, 0,0, 0,0 },
{ 0x0089, 0x0015, size8MB, CMD_TYPE_SCS, "Intel 28F640J5 4Mx16 (8MB)" ,64,size128K, 0,0, 0,0, 0,0 },
{ 0x0089, 0x0018, size16MB, CMD_TYPE_SCS, "Intel 28F128J3 8Mx16 (16MB)" ,128,size128K, 0,0, 0,0, 0,0 },
/* SST */
{ 0x00BF, 0x234B, size2MB, CMD_TYPE_SST, "SST39VF1601 1Mx16 BotB (2MB)" ,8,size8K, 31,size64K, 0,0, 0,0 },
{ 0x00BF, 0x234A, size2MB, CMD_TYPE_SST, "SST39VF1602 1Mx16 TopB (2MB)" ,31,size64K, 8,size8K, 0,0, 0,0 },
{ 0x00BF, 0x235B, size4MB, CMD_TYPE_SST, "SST39VF3201 2Mx16 BotB (4MB)" ,8,size8K, 63,size64K, 0,0, 0,0 },
{ 0x00BF, 0x235A, size4MB, CMD_TYPE_SST, "SST39VF3202 2Mx16 TopB (4MB)" ,63,size64K, 8,size8K, 0,0, 0,0 },
{ 0x00BF, 0x236B, size8MB, CMD_TYPE_SST, "SST39VF6401 4Mx16 BotB (8MB)" ,8,size8K, 127,size64K, 0,0, 0,0 },
{ 0x00BF, 0x236A, size8MB, CMD_TYPE_SST, "SST39VF6402 4Mx16 TopB (8MB)" ,127,size64K, 8,size8K, 0,0, 0,0 },
{ 0x00BF, 0x236D, size8MB, CMD_TYPE_SST, "SST39VF6401B 4Mx16 BotB (8MB)" ,8,size8K, 127,size64K, 0,0, 0,0 },
{ 0x00BF, 0x236C, size8MB, CMD_TYPE_SST, "SST39VF6402B 4Mx16 TopB (8MB)" ,127,size64K, 8,size8K, 0,0, 0,0 },
// See Spansion hack details for reasoning for the unusual vendid
{ 0x017E, 0x1A00, size4MB, CMD_TYPE_AMD, "Spansion S29GL032M BotB (4MB)" ,8,size8K, 63,size64K, 0,0, 0,0 },
{ 0x017E, 0x1A01, size4MB, CMD_TYPE_AMD, "Spansion S29GL032M TopB (4MB)" ,63,size64K, 8,size8K, 0,0, 0,0 },
{ 0x017E, 0x1000, size8MB, CMD_TYPE_AMD, "Spansion S29GL064M BotB (8MB)" ,8,size8K, 127,size64K, 0,0, 0,0 },
{ 0x017E, 0x1001, size8MB, CMD_TYPE_AMD, "Spansion S29GL064M TopB (8MB)" ,127,size64K, 8,size8K, 0,0, 0,0 },
// patch from OpenWRT jal2 for ti-ar7 ip8100
{ 0x017E, 0x1301, size8MB, CMD_TYPE_AMD, "Spansion S29GL064M U (8MB)" ,128,size64K, 0,0, 0,0, 0,0 },
{ 0x017E, 0x2101, size16MB, CMD_TYPE_AMD, "Spansion S29GL128P U (16MB)" ,128,size128K, 0,0, 0,0, 0,0 },
{ 0x017E, 0x1200, size16MB, CMD_TYPE_AMD, "Spansion S29GL128M U (16MB)" ,128,size128K, 0,0, 0,0, 0,0 },
{ 0x017E, 0x2201, size32MB, CMD_TYPE_AMD, "Spansion S29GL256P U (32MB)" ,256,size128K, 0,0, 0,0, 0,0 },
{ 0x017E, 0x2301, size64MB, CMD_TYPE_AMD, "Spansion S29GL512P U (64MB)" ,512,size128K, 0,0, 0,0, 0,0 },
{ 0x017E, 0x2801, size128MB, CMD_TYPE_AMD, "Spansion S29GL01GP U (128MB)" ,1024,size128K, 0,0, 0,0, 0,0 },
{ 0x0001, 0x0214, size2MB, CMD_TYPE_SPI, "Spansion S25FL016A (2MB) Serial" ,32,size64K, 0,0, 0,0, 0,0 }, /* new */
{ 0x0001, 0x0215, size4MB, CMD_TYPE_SPI, "Spansion S25FL032A (4MB) Serial" ,64,size64K, 0,0, 0,0, 0,0 }, /* new */
{ 0x0001, 0x0216, size8MB, CMD_TYPE_SPI, "Spansion S25FL064A (8MB) Serial" ,128,size64K, 0,0, 0,0, 0,0 }, /* new */
// Winbond 3-stage ID chips
{ 0xDA7E, 0x0A00, size4MB, CMD_TYPE_AMD, "Winbond W19B320AB BotB (4MB)" ,8,size8K, 63,size64K, 0,0, 0,0 },
{ 0xDA7E, 0x0A01, size4MB, CMD_TYPE_AMD, "Winbond W19B320AT TopB (4MB)" ,63,size64K, 8,size8K, 0,0, 0,0 },
{ 0x00EF, 0x3016, size4MB, CMD_TYPE_SPI, "Winbond W25X32 (4MB) Serial" ,64,size64K, 0,0, 0,0, 0,0 }, /* new */
{ 0x00EF, 0x3017, size8MB, CMD_TYPE_SPI, "Winbond W25X64 (8MB) Serial" ,128,size64K, 0,0, 0,0, 0,0 }, /* new */
// EON
{ 0x007f, 0x22F9, size4MB, CMD_TYPE_AMD, "EON EN29LV320 2Mx16 BotB (4MB)" ,8,size8K, 63,size64K, 0,0, 0,0 }, /* wrt54gl v1.1 */
{ 0x007f, 0x22F6, size4MB, CMD_TYPE_AMD, "EON EN29LV320 2Mx16 TopB (4MB)" ,63,size64K, 8,size8K, 0,0, 0,0 }, /* bypass */
{ 0x007F, 0x22C9, size8MB, CMD_TYPE_AMD, "EON EN29LV640 4Mx16 TopB (8MB)" ,127,size64K, 8,size8K, 0,0, 0,0 }, /* bypass */
{ 0x007F, 0x22Cb, size8MB, CMD_TYPE_AMD, "EON EN29LV640 4Mx16 BotB (8MB)" ,8,size8K, 127,size64K, 0,0, 0,0 }, /* bypass */
// Atmel
{ 0x001F, 0x00C8, size4MB, CMD_TYPE_AMD, "AT49BV322A 2Mx16 BotB (4MB)" ,8,size8K, 63,size64K, 0,0, 0,0 },
{ 0x001F, 0x00C9, size4MB, CMD_TYPE_AMD, "AT49BV322A(T) 2Mx16 TopB (4MB)" ,63,size64K, 8,size8K, 0,0, 0,0 },
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
};
// -----------------------------------------
// ---- Start of Compiler Specific Code ----
// -----------------------------------------
void lpt_openport(void)
{
#ifdef WINDOWS_VERSION // ---- Compiler Specific Code ----
HANDLE h;
h = CreateFile("\\\\.\\giveio", GENERIC_READ, 0, NULL, OPEN_EXISTING, FILE_ATTRIBUTE_NORMAL, NULL);
if (h == INVALID_HANDLE_VALUE)
{
printf("Couldn't access giveio device\n");
CloseHandle(h);
exit(0);
}
CloseHandle(h);
#else // ---- Compiler Specific Code ----
#ifdef RASPPI // ---- Compiler Specific Code ----
int mem_fd;
char *gpio_mem, *gpio_map;
/* open /dev/mem */
if ((mem_fd = open("/dev/mem", O_RDWR|O_SYNC) ) < 0) {
printf("can't open /dev/mem \n");
exit(-1);
}
// Allocate MAP block
if ((gpio_mem = malloc(BLOCK_SIZE + (PAGE_SIZE - 1))) == NULL) {
printf("allocation error\n");
exit(-1);
}
// Make sure pointer is on 4K boundary
if ((unsigned long) gpio_mem % PAGE_SIZE)
gpio_mem += PAGE_SIZE - ((unsigned long) gpio_mem % PAGE_SIZE);
/* mmap GPIO */
gpio_map = mmap(
(caddr_t) gpio_mem,
BLOCK_SIZE,
PROT_READ|PROT_WRITE,
MAP_SHARED|MAP_FIXED,
mem_fd,
GPIO_BASE
);
if ((long) gpio_map < 0) {
printf("mmap error %ld\n", (long) gpio_map);
exit(-1);
}
close(mem_fd);
// Always use volatile pointer!
gpio = (volatile unsigned *) gpio_map;
// Set TDO as input and TMS,TCK and TDI as output
INP_GPIO(TDO);
INP_GPIO(TMS);
INP_GPIO(TCK);
INP_GPIO(TDI);
OUT_GPIO(TMS);
OUT_GPIO(TCK);
OUT_GPIO(TDI);
#else
#ifdef __FreeBSD__ // ---- Compiler Specific Code ----
pfd = open("/dev/ppi0", O_RDWR);
if (pfd < 0)
{
perror("Failed to open /dev/ppi0");
exit(0);
}
if ((ioctl(pfd, PPEXCL) < 0) || (ioctl(pfd, PPCLAIM) < 0))
{
perror("Failed to lock /dev/ppi0");
close(pfd);
exit(0);
}
#else // ---- Compiler Specific Code ----
pfd = open("/dev/parport0", O_RDWR);
if (pfd < 0)
{
perror("Failed to open /dev/parport0");
exit(0);
}
if ((ioctl(pfd, PPEXCL) < 0) || (ioctl(pfd, PPCLAIM) < 0))
{
perror("Failed to lock /dev/parport0");
close(pfd);
exit(0);
}
#endif
#endif
#endif
}
void lpt_closeport(void)
{
#ifndef WINDOWS_VERSION // ---- Compiler Specific Code ----
#ifdef RASPPI
#else
#ifndef __FreeBSD__ // ---- Compiler Specific Code ----
if (ioctl(pfd, PPRELEASE) < 0)
{
perror("Failed to release /dev/parport0");
close(pfd);
exit(0);
}
#endif
close(pfd);
#endif
#endif
}
// Yoon's extensions for exiting debug mode
static void return_from_debug_mode(void)
{
ExecuteDebugModule(pracc_return_from_debug);
}
static unsigned char clockin(int tms, int tdi)
{
#ifdef RASPPI
unsigned int data;
#else
unsigned char data;
#endif
tms = tms ? 1 : 0;
tdi = tdi ? 1 : 0;
#ifdef RASPPI
data = (tms << TMS) | (tdi << TDI);
GPIO_CLR = (1 << TCK) | (1 << TMS) | (1 << TDI);
GPIO_SET = data;
cable_wait();
GPIO_SET = 1 << TCK;
cable_wait();
data = GPIO_GET;
data = (data >> TDO) & 1;
#else
// yoon's remark we set wtrst_n to be d4 so we are going to drive it low
if (wiggler) data = (1 << WTDO) | (0 << WTCK) | (tms << WTMS) | (tdi << WTDI)| (1 << WTRST_N);
else data = (1 << TDO) | (0 << TCK) | (tms << TMS) | (tdi << TDI);
cable_wait();
#ifdef WINDOWS_VERSION // ---- Compiler Specific Code ----
_outp(0x378, data);
#else
ioctl(pfd, PPWDATA, &data);
#endif
if (wiggler) data = (1 << WTDO) | (1 << WTCK) | (tms << WTMS) | (tdi << WTDI) | (1 << WTRST_N);
else data = (1 << TDO) | (1 << TCK) | (tms << TMS) | (tdi << TDI);
cable_wait();
#ifdef WINDOWS_VERSION // ---- Compiler Specific Code ----
_outp(0x378, data);
#else
ioctl(pfd, PPWDATA, &data);
#endif
#ifdef WINDOWS_VERSION // ---- Compiler Specific Code ----
data = (unsigned char)_inp(0x379);
#else
ioctl(pfd, PPRSTATUS, &data);
#endif
data ^= 0x80;
data >>= wiggler?WTDO:TDO;
data &= 1;
#endif
return data;
}
// ---------------------------------------
// ---- End of Compiler Specific Code ----
// ---------------------------------------
void test_reset(void)
{
clockin(1, 0); // Run through a handful of clock cycles with TMS high to make sure
clockin(1, 0); // we are in the TEST-LOGIC-RESET state.
clockin(1, 0);
clockin(1, 0);
clockin(1, 0);
clockin(0, 0); // enter runtest-idle
}
static int curinstr = 0xFFFFFFFF;
void set_instr(int instr)
{
int i;
if (instr == curinstr)
return;
clockin(1, 0); // enter select-dr-scan
clockin(1, 0); // enter select-ir-scan
clockin(0, 0); // enter capture-ir
clockin(0, 0); // enter shift-ir (dummy)
for (i=0; i < instruction_length; i++)
{
clockin(i==(instruction_length - 1), (instr>>i)&1);
}
clockin(1, 0); // enter update-ir
clockin(0, 0); // enter runtest-idle
curinstr = instr;
}
static unsigned int ReadWriteData(unsigned int in_data)
{
int i;
unsigned int out_data = 0;
unsigned char out_bit;
if (DEBUG) printf("INSTR: 0x%04x ", curinstr);
if (DEBUG) printf("W: 0x%08x ", in_data);
clockin(1, 0); // enter select-dr-scan
clockin(0, 0); // enter capture-dr
clockin(0, 0); // enter shift-dr
for (i = 0 ; i < 32 ; i++)
{
out_bit = clockin((i == 31), ((in_data >> i) & 1));
out_data = out_data | (out_bit << i);
}
clockin(1,0); // enter update-dr
clockin(0,0); // enter runtest-idle
if (DEBUG) printf("R: 0x%08x\n", out_data);
return out_data;
}
static unsigned int ReadData(void)
{
return ReadWriteData(0x00);
}
void WriteData(unsigned int in_data)
{
ReadWriteData(in_data);
}
void ShowData(unsigned int value)
{
unsigned int i;
for (i=0; i<32; i++)
printf("%d", (value >> (31-i)) & 1);
printf(" (%08X)\n", value);
}
unsigned int swap_bytes(unsigned int data, int num_bytes)
{
unsigned int datab[4], i;
for (i = 0; i < num_bytes; i++)
{
datab[i] = (data >>((num_bytes - i - 1) * 8) & 0xFF);
}
data = 0x0;
for (i = 0; i < num_bytes; i++)
{
data = (data | (datab[i] <<(8 * i)));
}
return data;
}
unsigned short byteSwap(unsigned short data)
{
//convert from little to big endian
unsigned short tmp;
tmp=(data<<8)|(data>>8);
return tmp;
}
static unsigned int ejtag_read(unsigned int addr)
{
if (USE_DMA) return(ejtag_dma_read(addr));
else return(ejtag_pracc_read(addr));
}
static unsigned int ejtag_read_h(unsigned int addr)
{
if (USE_DMA) return(ejtag_dma_read_h(addr));
else return(ejtag_pracc_read_h(addr));
}
void ejtag_write(unsigned int addr, unsigned int data)
{
if (USE_DMA) ejtag_dma_write(addr, data);
else ejtag_pracc_write(addr, data);
}
void ejtag_write_h(unsigned int addr, unsigned int data)
{
if (USE_DMA) ejtag_dma_write_h(addr, data);
else ejtag_pracc_write_h(addr, data);
}
static unsigned int ejtag_dma_read(unsigned int addr)
{
unsigned int data;
int retries = RETRY_ATTEMPTS;
begin_ejtag_dma_read:
// Setup Address
set_instr(INSTR_ADDRESS);
WriteData(addr);
// Initiate DMA Read & set DSTRT
set_instr(INSTR_CONTROL);
ctrl_reg = ReadWriteData(DMAACC | DRWN | DMA_WORD | DSTRT | PROBEN | PRACC);
// Wait for DSTRT to Clear - Problem Gv8 tornado
if (!((proc_id & 0xfffffff) == 0x535417f))
{
while (ReadWriteData(DMAACC | PROBEN | PRACC) & DSTRT);
}
// Read Data
set_instr(INSTR_DATA);
data = ReadData();
// Clear DMA & Check DERR
set_instr(INSTR_CONTROL);
if (ReadWriteData(PROBEN | PRACC) & DERR)
{
if (retries--) goto begin_ejtag_dma_read;
else printf("DMA Read Addr = %08x Data = (%08x)ERROR ON READ\n", addr, data);
}
return(data);
}
static unsigned int ejtag_dma_read_h(unsigned int addr)
{
unsigned int data;
int retries = RETRY_ATTEMPTS;
begin_ejtag_dma_read_h:
// Setup Address
set_instr(INSTR_ADDRESS);
WriteData(addr);
// Initiate DMA Read & set DSTRT
set_instr(INSTR_CONTROL);
ctrl_reg = ReadWriteData(DMAACC | DRWN | DMA_HALFWORD | DSTRT | PROBEN | PRACC);
// Wait for DSTRT to Clear
while (ReadWriteData(DMAACC | PROBEN | PRACC) & DSTRT);
// Read Data
set_instr(INSTR_DATA);
data = ReadData();
// Clear DMA & Check DERR
set_instr(INSTR_CONTROL);
if (ReadWriteData(PROBEN | PRACC) & DERR)
{
if (retries--) goto begin_ejtag_dma_read_h;
else printf("DMA Read Addr = %08x Data = (%08x)ERROR ON READ\n", addr, data);
}
// Handle the bigendian / littleendian
if ( addr & 0x2 )
data = (data>>16)&0xffff;
else
data = (data&0x0000ffff);
return(data);
}
void ejtag_dma_write(unsigned int addr, unsigned int data)
{
int retries = RETRY_ATTEMPTS;
begin_ejtag_dma_write:
// Setup Address
set_instr(INSTR_ADDRESS);
WriteData(addr);
// Setup Data
set_instr(INSTR_DATA);
WriteData(data);
// Initiate DMA Write & set DSTRT
set_instr(INSTR_CONTROL);
ctrl_reg = ReadWriteData(DMAACC | DMA_WORD | DSTRT | PROBEN | PRACC);
// Wait for DSTRT to Clear
while (ReadWriteData(DMAACC | PROBEN | PRACC) & DSTRT);
// Clear DMA & Check DERR
set_instr(INSTR_CONTROL);
if (ReadWriteData(PROBEN | PRACC) & DERR)
{
if (retries--) goto begin_ejtag_dma_write;
else printf("DMA Write Addr = %08x Data = ERROR ON WRITE\n", addr);
}
}
void ejtag_dma_write_h(unsigned int addr, unsigned int data)
{
int retries = RETRY_ATTEMPTS;
begin_ejtag_dma_write_h:
// Setup Address
set_instr(INSTR_ADDRESS);
WriteData(addr);
// Setup Data
set_instr(INSTR_DATA);
WriteData(data);
// Initiate DMA Write & set DSTRT
set_instr(INSTR_CONTROL);
ctrl_reg = ReadWriteData(DMAACC | DMA_HALFWORD | DSTRT | PROBEN | PRACC);
// Wait for DSTRT to Clear
while (ReadWriteData(DMAACC | PROBEN | PRACC) & DSTRT);
// Clear DMA & Check DERR
set_instr(INSTR_CONTROL);
if (ReadWriteData(PROBEN | PRACC) & DERR)
{
if (retries--) goto begin_ejtag_dma_write_h;
else printf("DMA Write Addr = %08x Data = ERROR ON WRITE\n", addr);
}
}
static unsigned int ejtag_pracc_read(unsigned int addr)
{
address_register = addr | 0xA0000000; // Force to use uncached segment
data_register = 0x0;
ExecuteDebugModule(pracc_readword_code_module);
return(data_register);
}
void ejtag_pracc_write(unsigned int addr, unsigned int data)
{
address_register = addr | 0xA0000000; // Force to use uncached segment
data_register = data;
ExecuteDebugModule(pracc_writeword_code_module);
}
static unsigned int ejtag_pracc_read_h(unsigned int addr)
{
address_register = addr | 0xA0000000; // Force to use uncached segment
data_register = 0x0;
ExecuteDebugModule(pracc_readhalf_code_module);
return(data_register);
}
void ejtag_pracc_write_h(unsigned int addr, unsigned int data)
{
address_register = addr | 0xA0000000; // Force to use uncached segment
data_register = data;
ExecuteDebugModule(pracc_writehalf_code_module);
}
void setup_memory_4712(void)
{
printf("Configuring SDRAM... ");
ejtag_dma_write(0x18006f98,0x00030001); // #define SBTMSTATELOW offset 0xf00 + 0x98
ejtag_dma_write(0x18006f98,0x00030000);
ejtag_dma_write(0x18006f98,0x00010000);
ejtag_dma_write(0x18006004,0x00048000); // #define MEMC_SD_CONFIG_INIT 0x00048000
ejtag_dma_write(0x1800601c,0x000754da); // #define MEMC_SD_DRAMTIM3_INIT 0x000754da sbmemc.h
ejtag_dma_write(0x18006034,0x23232323);
ejtag_dma_write(0x18006038,0x14500200); // #define MEMC_SD1_WRNCDLCOR_INIT 0x14500200 For corerev 1 (4712)
ejtag_dma_write(0x1800603c,0x22021416); // #define MEMC_SD1_MISCDLYCTL_INIT 0x00021416 For corerev 1 (4712)
ejtag_dma_write(0x18006000,0x00000002); // #define MEMC_SD_CONTROL_INIT0 0x00000002
ejtag_dma_write(0x18006000,0x00000008); // #define MEMC_SD_CONTROL_INIT1 0x00000008
ejtag_dma_write(0x18006000,0x00000004);
ejtag_dma_write(0x18006000,0x00000004);
ejtag_dma_write(0x18006000,0x00000004);
ejtag_dma_write(0x18006000,0x00000004);
ejtag_dma_write(0x18006000,0x00000004);