Opening as draft as this is still incomplete, but will eventually close #297.

For the ESP32-C2 and ESP32-C3, I believe this should be relatively (or fully) complete, however it will require some review. Priority levels were stated in the TRM (though I'm not entirely sure if these should be 0- or 1-indexed). Core interrupts were taken from esp-riscv-rt, and I believe these should be correct.

The above also applies for the ESP32-C6 and ESP32-H2, though they are notably missing both the CLINT and PLIC sections in their respective settings.yaml files.

Copying blindly from greenlsi/e310x#1, I believe CLINT should be as simple as:

clint:
  name: "CLINT"
  freq: 32768
  async_delay: false

However, I'm unsure where this frequency comes from exactly; will required some investigation.

I tried adding the following for PLIC, but encountered some issues; it's been awhile, forget what exactly, but IIRC it was due to there being no PLIC peripheral in the PAC. Again, needs investigation.

plic:
  name: "PLIC"
  core_interrupt: "MachineExternal" 
  hart_id: "H0"

This changes the src/interrupts.rs file quite a bit, so I suppose additional changes will be required in esp-hal and/or esp-riscv-rt to reflect these.