LiteSATA bench not initializing on SQRL Acorn CLE-215 and Alientek Davinci Pro A35T

[hansfbaier]

I built the acorn.py for both the CLE-215 and the Alientek board,
and I get in both cases the same symptoms:

$ litex_server --jtag --jtag-config ft232.cfg 
Open On-Chip Debugger 0.12.0
Licensed under GNU GPL v2
For bug reports, read
	http://openocd.org/doc/doxygen/bugs.html
DEPRECATED! use 'adapter driver' not 'interface'
Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'.
DEPRECATED! use 'adapter speed' not 'adapter_khz'
fpga_program
jtagstream_serve
Info : clock speed 3000 kHz
Info : JTAG tap: xc7.tap tap/device found: 0x13636093 (mfg: 0x049 (Xilinx), part: 0x3636, ver: 0x1)
--------------
 [19:24:13] (venv) /devel/riscv/litex-root/litesata/bench master|+2…4$ litex_cli --ident
LiteSATA bench on Acorn CLE 215+.
[19:24:16] (venv) /devel/riscv/litex-root/litesata/bench master|+2…4$ litex_cli --regs
0x00000000 : 0x00000000 ctrl_reset
0x00000004 : 0x12345678 ctrl_scratch
0x00000008 : 0x00000000 ctrl_bus_errors
0x00001000 : 0x00000000 sata_bist_generator_start
0x00001004 : 0x00000000 sata_bist_generator_sector
0x0000100c : 0x00000000 sata_bist_generator_count
0x00001010 : 0x00000000 sata_bist_generator_loops
0x00001014 : 0x00000000 sata_bist_generator_random
0x00001018 : 0x00000001 sata_bist_generator_done
0x0000101c : 0x00000000 sata_bist_generator_aborted
0x00001020 : 0x00000000 sata_bist_generator_errors
0x00001024 : 0x00000000 sata_bist_generator_cycles
0x00001028 : 0x00000000 sata_bist_checker_start
0x0000102c : 0x00000000 sata_bist_checker_sector
0x00001034 : 0x00000000 sata_bist_checker_count
0x00001038 : 0x00000000 sata_bist_checker_loops
0x0000103c : 0x00000000 sata_bist_checker_random
0x00001040 : 0x00000001 sata_bist_checker_done
0x00001044 : 0x00000000 sata_bist_checker_aborted
0x00001048 : 0x00000000 sata_bist_checker_errors
0x0000104c : 0x00000000 sata_bist_checker_cycles
0x00001050 : 0x00000000 sata_bist_identify_start
0x00001054 : 0x00000001 sata_bist_identify_done
0x00001058 : 0x00000020 sata_bist_identify_data_width
0x0000105c : 0x00000000 sata_bist_identify_source_valid
0x00001060 : 0x00000000 sata_bist_identify_source_ready
0x00001064 : 0x00000000 sata_bist_identify_source_data
0x00001800 : 0x00000001 sata_phy_enable
0x00001804 : 0x00000002 sata_phy_status
[19:24:29] (venv) /devel/riscv/litex-root/litesata/bench master|+2…4$ litex_cli --write 0x4 0xffffffff
[19:24:42] (venv) /devel/riscv/litex-root/litesata/bench master|+2…4$ litex_cli --read 0x4
0x00000004 : 0xc3bfc3bf
[19:24:45] (venv) /devel/riscv/litex-root/litesata/bench master|+2…4$ litex_cli --write 0x4 0x0
[19:24:51] (venv) /devel/riscv/litex-root/litesata/bench master|+2…4$ litex_cli --read 0x4
0x00000004 : 0x00000000
[19:24:52] (venv) /devel/riscv/litex-root/litesata/bench master|+2…4$ litex_cli --write 0x4 0xaaaa5555
[19:25:03] (venv) /devel/riscv/litex-root/litesata/bench master|+2…4$ litex_cli --read 0x4
0x00000004 : 0xc2aac2aa
[19:25:06] (venv) /devel/riscv/litex-root/litesata/bench master|+2…4$ litex_cli --write 0x4 0x5555aaaa
[19:25:16] (venv) /devel/riscv/litex-root/litesata/bench master|+2…4$ litex_cli --read 0x4
0x00000004 : 0x5555c2aa
[19:25:17] (venv) /devel/riscv/litex-root/litesata/bench master|+2…4$ litex_cli --write 0x4 0x0
[19:25:27] (venv) /devel/riscv/litex-root/litesata/bench master|+2…4$ litex_cli --read 0x4
0x00000004 : 0x00000000
[19:25:28] (venv) /devel/riscv/litex-root/litesata/bench master|+2…4$ litex_cli --write 0x4 0x5555aaaa
[19:25:34] (venv) /devel/riscv/litex-root/litesata/bench master|+2…4$ litex_cli --read 0x4
0x00000004 : 0x5555c2aa
[19:25:35] (venv) /devel/riscv/litex-root/litesata/bench master|+2…4$ litex_cli --read 0x1804
0x00001804 : 0x00000002
[19:25:49] (venv) /devel/riscv/litex-root/litesata/bench master|+2…4$ litex_cli --read 0x1804
^[[A0x00001804 : 0x00000006
[19:25:50] (venv) /devel/riscv/litex-root/litesata/bench master|+2…4$
[19:25:50] (venv) /devel/riscv/litex-root/litesata/bench master|+2…4$ litex_cli --read 0x1804
^[[A0x00001804 : 0x00000002
[19:25:50] (venv) /devel/riscv/litex-root/litesata/bench master|+2…4$
[19:25:50] (venv) /devel/riscv/litex-root/litesata/bench master|+2…4$ litex_cli --read 0x1804
^[[A0x00001804 : 0x00000006
[19:25:51] (venv) /devel/riscv/litex-root/litesata/bench master|+2…4$
[19:25:51] (venv) /devel/riscv/litex-root/litesata/bench master|+2…4$ litex_cli --read 0x1804
^[[A0x00001804 : 0x00000006
[19:25:51] (venv) /devel/riscv/litex-root/litesata/bench master|+2…4$
[19:25:51] (venv) /devel/riscv/litex-root/litesata/bench master|+2…4$ litex_cli --read 0x1804
^[[A0x00001804 : 0x00000002
[19:25:52] (venv) /devel/riscv/litex-root/litesata/bench master|+2…4$
[19:25:52] (venv) /devel/riscv/litex-root/litesata/bench master|+2…4$ litex_cli --read 0x1804
^[[A0x00001804 : 0x00000006

[19:25:52] (venv) /devel/riscv/litex-root/litesata/bench master|+2…4$
[19:25:52] (venv) /devel/riscv/litex-root/litesata/bench master|+2…4$ litex_cli --read 0x1804
^[[A0x00001804 : 0x00000006
[19:25:53] (venv) /devel/riscv/litex-root/litesata/bench master|+2…4$
[19:25:53] (venv) /devel/riscv/litex-root/litesata/bench master|+2…4$ python test_init.py
................................................................................
Failed

The results are identical to the Alientek board, only that in the latter case sometimes LEDs 1 and 2 start blinking
after test_init.py is finished, but SATA status still oscillates between 0x2 and 0x6.
In both cases, Vivado is used as a toolchain.

[hansfbaier]

This issue is very likely related to #28

[hansfbaier]

Plugging in a different drive, Switching from a crossed SATA adapter to a non-crossed and switching SATA generations do not seem to make a difference in the symptoms.

[hansfbaier]

Vivado version:
****** Vivado v2022.2 (64-bit)
**** SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022
**** IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022