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Register specifiers rs and rd must not be equal, because such an instruction does not have the same effect when reexecuted. The result of executing such an instruction is UNPREDICTABLE.
This restriction permits an exception handler to resume execution by re-executing the branch when an exception occurs in the branch delay slot. ))
However, now $ra can be used like other general purpose registers, which means that it is possible to generate legal instructions like jalr $ra (equivalent to jalr $ra, $ra).
Currently, the SPIM simulator covers up the problem, because it can execute jalr $ra in the way we expect instead of rejecting it.
The text was updated successfully, but these errors were encountered:
MIPS standard says:
However, now $ra can be used like other general purpose registers, which means that it is possible to generate legal instructions like
jalr $ra
(equivalent tojalr $ra, $ra
).Currently, the SPIM simulator covers up the problem, because it can execute
jalr $ra
in the way we expect instead of rejecting it.The text was updated successfully, but these errors were encountered: