diff --git a/.github/dependabot.yml b/.github/dependabot.yml new file mode 100644 index 0000000..0d08e26 --- /dev/null +++ b/.github/dependabot.yml @@ -0,0 +1,11 @@ +# To get started with Dependabot version updates, you'll need to specify which +# package ecosystems to update and where the package manifests are located. +# Please see the documentation for all configuration options: +# https://docs.github.com/code-security/dependabot/dependabot-version-updates/configuration-options-for-the-dependabot.yml-file + +version: 2 +updates: + - package-ecosystem: "github-actions" # See documentation for possible values + directory: "/" # Location of package manifests + schedule: + interval: "weekly" diff --git a/.github/workflows/haskell.yml b/.github/workflows/haskell.yml index ef27f71..6e98567 100644 --- a/.github/workflows/haskell.yml +++ b/.github/workflows/haskell.yml @@ -23,7 +23,7 @@ jobs: os: [ubuntu-20.04] steps: - - uses: actions/checkout@v3 + - uses: actions/checkout@v4 with: submodules: true @@ -66,7 +66,7 @@ jobs: cabal build --dry-run - name: Restore Haskell cached dependencies - uses: actions/cache/restore@v3 + uses: actions/cache/restore@v4 id: cache env: key: ${{ runner.os }}-ghc-${{ steps.setup.outputs.ghc-version }}-cabal-${{ steps.setup.outputs.cabal-version }} @@ -91,7 +91,7 @@ jobs: run: cabal build all --only-dependencies - name: Save cached dependencies - uses: actions/cache/save@v3 + uses: actions/cache/save@v4 if: ${{ steps.cache.outputs.cache-primary-key != steps.cache.outputs.cache-matched-key }} with: path: ${{ steps.setup.outputs.cabal-store }} @@ -115,7 +115,7 @@ jobs: sudo apt-get install build-essential clang bison flex libreadline-dev gawk tcl-dev libffi-dev git graphviz xdot pkg-config python python3 libftdi-dev qt5-default python3-dev libboost-all-dev cmake libeigen3-dev - name: Checkout icestorm - uses: actions/checkout@v3 + uses: actions/checkout@v4 with: repository: YosysHQ/icestorm path: icestorm @@ -127,7 +127,7 @@ jobs: sudo make install - name: Checkout nextpnr - uses: actions/checkout@v3 + uses: actions/checkout@v4 with: repository: YosysHQ/nextpnr ref: master @@ -142,11 +142,12 @@ jobs: sudo make install - name: Checkout yosys - uses: actions/checkout@v3 + uses: actions/checkout@v4 with: repository: YosysHQ/yosys - ref: master + ref: main path: yosys + submodules: true - name: Install yosys working-directory: yosys @@ -154,21 +155,21 @@ jobs: make -j$(nproc) sudo make install - - name: Checkout SymbiYosys - uses: actions/checkout@v3 + - name: Checkout SymbiYosys (sby) + uses: actions/checkout@v4 with: - repository: YosysHQ/SymbiYosys - ref: master - path: SymbiYosys + repository: YosysHQ/sby + ref: main + path: sby - name: Install SymbiYosys - working-directory: SymbiYosys + working-directory: sby run: | sudo apt-get install libboost-program-options-dev autoconf libgmp-dev cmake sudo make install - name: Checkout Boolector - uses: actions/checkout@v3 + uses: actions/checkout@v4 with: repository: boolector/boolector ref: master @@ -185,7 +186,7 @@ jobs: sudo cp deps/btor2tools/build/bin/btorsim /usr/local/bin - name: Checkout riscv-gnu-toolchain - uses: actions/checkout@v3 + uses: actions/checkout@v4 with: repository: riscv/riscv-gnu-toolchain ref: master diff --git a/CHANGELOG.md b/CHANGELOG.md index 4249155..e4a8e45 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,6 +1,11 @@ # Revision history for lion +## 0.4.0.1 + +* GHC and library updates #21 + ## 0.4.0.0 + * Update clash-prelude dependency bounds #4 * Type-level -> data-level configuration #6 diff --git a/README.md b/README.md index 47b0554..fbee2ed 100644 --- a/README.md +++ b/README.md @@ -8,9 +8,9 @@ Lion is a formally verified, 5-stage pipeline [RISC-V](https://riscv.org) core. This repository contains four parts: 1. The Lion library: a pipelined RISC-V core. - 2. [lion-formal](https://github.com/standardsemiconductor/lion/tree/main/lion-formal): formally verify the core using [riscv-formal](https://github.com/standardsemiconductor/riscv-formal/tree/lion). - 3. [lion-soc](https://github.com/standardsemiconductor/lion/tree/main/lion-soc): a System-on-Chip demonstrating usage of the Lion core on the VELDT. - 4. [lion-metric](https://github.com/standardsemiconductor/lion/tree/main/lion-metric): Observe Yosys synthesis metrics on the Lion Core. + 2. [lion-formal](lion-formal): formally verify the core using [riscv-formal](https://github.com/standardsemiconductor/riscv-formal/tree/lion). + 3. [lion-soc](lion-soc): a System-on-Chip demonstrating usage of the Lion core on the VELDT. + 4. [lion-metric](lion-metric): Observe Yosys synthesis metrics on the Lion Core. ## Lion library ### Usage: diff --git a/src/Lion/Alu.hs b/lib/Lion/Alu.hs similarity index 95% rename from src/Lion/Alu.hs rename to lib/Lion/Alu.hs index e07cbe4..8b49bdf 100644 --- a/src/Lion/Alu.hs +++ b/lib/Lion/Alu.hs @@ -1,4 +1,6 @@ -{-| +{-# LANGUAGE CPP #-} + +{-| Module : Lion.Alu Description : Lion arithmetic logic unit Copyright : (c) David Cox, 2021-2024 @@ -10,7 +12,11 @@ Configurable alu, choose between soft and hard adders/subtractors module Lion.Alu where +#if __GLASGOW_HASKELL__ > 902 +import Clash.Prelude hiding (And(..), Xor(..)) +#else import Clash.Prelude +#endif import Data.Function ( on ) import Ice40.Mac ( Input(..), @@ -45,7 +51,7 @@ softAlu -> Signal dom (BitVector 32) softAlu op in1 = register 0 . liftA3 aluFunc op in1 where - aluFunc = \case + aluFunc = \case Add -> (+) Sub -> (-) Sll -> \x y -> x `shiftL` shamt y @@ -73,13 +79,13 @@ hardAlu op in1 in2 = mux isAddSub adderSubtractor $ register 0 $ baseAlu op in1 isSub = (Sub == ) <$> op isAddSub = delay False $ isAdd .||. isSub adderSubtractor = hardAddSub (boolToBit <$> isSub) in1 in2 - + baseAlu :: Signal dom Op -> Signal dom (BitVector 32) -> Signal dom (BitVector 32) -> Signal dom (BitVector 32) -baseAlu = liftA3 $ \case +baseAlu = liftA3 $ \case Add -> \_ _ -> 0 Sub -> \_ _ -> 0 Sll -> \x y -> x `shiftL` shamt y diff --git a/src/Lion/Core.hs b/lib/Lion/Core.hs similarity index 100% rename from src/Lion/Core.hs rename to lib/Lion/Core.hs diff --git a/src/Lion/Instruction.hs b/lib/Lion/Instruction.hs similarity index 98% rename from src/Lion/Instruction.hs rename to lib/Lion/Instruction.hs index 3c89d18..9393c32 100644 --- a/src/Lion/Instruction.hs +++ b/lib/Lion/Instruction.hs @@ -1,3 +1,5 @@ +{-# LANGUAGE CPP #-} + {-| Module : Lion.Instruction Description : RISC-V ISA @@ -8,7 +10,11 @@ Maintainer : standardsemiconductor@gmail.com module Lion.Instruction where +#if __GLASGOW_HASKELL__ > 902 +import Clash.Prelude hiding (Xor(Xor), And(And)) +#else import Clash.Prelude +#endif import Data.Function ( on ) data Exception = IllegalInstruction @@ -26,7 +32,7 @@ data WbInstr = WbRegWr (Unsigned 5) (BitVector 32) -- | Memory pipeline instruction data MeInstr = MeRegWr (Unsigned 5) | MeJump (Unsigned 5) (BitVector 32) - | MeBranch + | MeBranch | MeStore (BitVector 32) (BitVector 4) (BitVector 32) | MeLoad Load (Unsigned 5) (BitVector 32) (BitVector 4) | MeNop @@ -155,7 +161,7 @@ parseInstr i = case i of immI :: BitVector 32 immI = signExtend $ slice d31 d20 i - + immS :: BitVector 32 immS = signExtend $ slice d31 d25 i ++# slice d11 d7 i @@ -164,7 +170,7 @@ parseInstr i = case i of immU :: BitVector 32 immU = slice d31 d12 i ++# 0 - + immJ :: BitVector 32 immJ = signExtend (slice d31 d31 i ++# slice d19 d12 i ++# slice d20 d20 i ++# slice d30 d25 i ++# slice d24 d21 i) `shiftL` 1 diff --git a/src/Lion/Pipe.hs b/lib/Lion/Pipe.hs similarity index 96% rename from src/Lion/Pipe.hs rename to lib/Lion/Pipe.hs index f521cf6..cea32eb 100644 --- a/src/Lion/Pipe.hs +++ b/lib/Lion/Pipe.hs @@ -1,3 +1,5 @@ +{-# LANGUAGE CPP #-} + {-| Module : Lion.Pipe Description : RISC-V 5-stage pipeline @@ -16,13 +18,18 @@ import Data.Monoid.Generic import Lion.Instruction import Lion.Rvfi +#if __GLASGOW_HASKELL__ > 902 +import Data.Monoid (First(..)) +import Control.Monad (unless) +#endif + -- | Pipeline configuration newtype PipeConfig = PipeConfig { startPC :: BitVector 32 -- ^ start program counter } deriving stock (Generic, Show, Eq) -- | Default pipeline configuration --- +-- -- `startPC` = 0 defaultPipeConfig :: PipeConfig defaultPipeConfig = PipeConfig 0 @@ -55,7 +62,7 @@ data ToMem = ToMem deriving anyclass NFDataX -- | Construct instruction memory access -instrMem +instrMem :: BitVector 32 -- ^ instruction address -> ToMem instrMem addr = ToMem @@ -66,7 +73,7 @@ instrMem addr = ToMem } -- | Construct data memory access -dataMem +dataMem :: BitVector 32 -- ^ memory address -> BitVector 4 -- ^ byte mask -> Maybe (BitVector 32) -- ^ write @@ -111,8 +118,8 @@ data Control = Control makeLenses ''Control mkControl :: Control -mkControl = Control - { _firstCycle = True +mkControl = Control + { _firstCycle = True , _exBranching = Nothing , _meBranching = False , _deLoad = False @@ -156,9 +163,9 @@ mkPipe :: PipeConfig -> Pipe mkPipe pipeConfig = Pipe { _fetchPC = startPC pipeConfig - -- decode stage + -- decode stage , _dePC = 0 - + -- execute stage , _exIR = Nothing , _exPC = 0 @@ -169,18 +176,18 @@ mkPipe pipeConfig = Pipe -- memory stage , _meIR = Nothing , _meRvfi = mkRvfi - + -- writeback stage , _wbIR = Nothing , _wbNRet = 0 , _wbRvfi = mkRvfi - + -- pipeline control , _control = mkControl } -- | 5-Stage RISC-V pipeline -pipe +pipe :: HiddenClockResetEnable dom => PipeConfig -> Signal dom ToPipe @@ -188,7 +195,7 @@ pipe pipe config = mealy pipeMealy (mkPipe config) where pipeMealy s i = let ((), s', o) = runRWS pipeM i s - in (s', o) + in (s', o) -- | Monadic pipeline pipeM :: RWS ToPipe FromPipe Pipe () @@ -329,21 +336,21 @@ execute = do scribe toAluInput1 $ First $ Just in1 scribe toAluInput2 $ First $ Just in2 - regFwd - :: MonadState s m + regFwd + :: MonadState s m => MonadReader r m - => Lens' s (Unsigned 5) + => Lens' s (Unsigned 5) -> Lens' r (BitVector 32) -> Lens' s (Maybe (Unsigned 5, BitVector 32)) -> Lens' s (Maybe (Unsigned 5, BitVector 32)) -> m (BitVector 32) - regFwd rsAddr rsData meFwd wbFwd = + regFwd rsAddr rsData meFwd wbFwd = guardZero rsAddr =<< fwd <$> use rsAddr <*> view rsData <*> use meFwd <*> use wbFwd where guardZero -- register x0 always has value 0. - :: MonadState s m - => Lens' s (Unsigned 5) - -> BitVector 32 + :: MonadState s m + => Lens' s (Unsigned 5) + -> BitVector 32 -> m (BitVector 32) guardZero addr value = do isZero <- uses addr (== 0) @@ -375,7 +382,7 @@ decode = do Left IllegalInstruction -> do -- trap and instr=Nop (addi x0 x0 0) unless bubble $ exIR ?= ExAlu Add 0 exRvfi.rvfiTrap .= True - + -- | fetch instruction fetch :: RWS ToPipe FromPipe Pipe () fetch = do @@ -391,9 +398,9 @@ fetch = do ------------- -- | forward register writes -fwd - :: Unsigned 5 - -> BitVector 32 +fwd + :: Unsigned 5 + -> BitVector 32 -> Maybe (Unsigned 5, BitVector 32) -- ^ meRegFwd -> Maybe (Unsigned 5, BitVector 32) -- ^ wbRegFwd -> BitVector 32 diff --git a/src/Lion/Rvfi.hs b/lib/Lion/Rvfi.hs similarity index 100% rename from src/Lion/Rvfi.hs rename to lib/Lion/Rvfi.hs diff --git a/lion-formal/lion-formal.cabal b/lion-formal/lion-formal.cabal index 22b5964..2321a97 100644 --- a/lion-formal/lion-formal.cabal +++ b/lion-formal/lion-formal.cabal @@ -16,8 +16,8 @@ library hs-source-dirs: src default-language: Haskell2010 build-depends: - base >= 4.13 && < 4.17, - clash-prelude >= 1.4 && < 1.7, + base >= 4.13 && < 4.21, + clash-prelude >= 1.4 && < 1.9, lion >= 0.4 && < 0.5, ghc-typelits-natnormalise, ghc-typelits-extra, diff --git a/lion-metric/cabal.project b/lion-metric/cabal.project index 033b894..86911bf 100644 --- a/lion-metric/cabal.project +++ b/lion-metric/cabal.project @@ -1,5 +1,6 @@ packages: lion-metric.cabal , ../lion.cabal + , https://hackage.haskell.org/package/ice40-prim-0.3.1.3/ice40-prim-0.3.1.3.tar.gz write-ghc-environment-files: always diff --git a/lion-metric/lion-metric.cabal b/lion-metric/lion-metric.cabal index a4eae86..d5b021d 100644 --- a/lion-metric/lion-metric.cabal +++ b/lion-metric/lion-metric.cabal @@ -7,7 +7,7 @@ bug-reports: https://github.com/standardsemiconductor/lion/issues license: BSD-3-Clause author: dopamane maintainer: dopamane -copyright: (c) 2021-2023 David Cox +copyright: (c) 2021-2024 David Cox category: Hardware library @@ -15,7 +15,7 @@ library hs-source-dirs: src default-language: Haskell2010 build-depends: - base >= 4.13 && < 4.17, + base >= 4.13 && < 4.21, clash-prelude >= 1.4 && < 1.7, lion >= 0.4 && < 0.5, ghc-typelits-natnormalise, @@ -40,7 +40,7 @@ library executable metric main-is: Main.hs - build-depends: base >= 4.13 && < 4.16 + build-depends: base >= 4.13 && < 4.21 , clash-ghc , shake hs-source-dirs: app diff --git a/lion-soc/README.md b/lion-soc/README.md index 7df3404..492d5b3 100644 --- a/lion-soc/README.md +++ b/lion-soc/README.md @@ -71,7 +71,7 @@ Max frequency for clock: 14.93 MHz (PASS @ 12MHz) |----------|----------|------------------|---------------| | Reserved | Reserved | Register Address | Register Data | -See [Appendix D of the iCE40 LED Driver Usage Guide](https://github.com/standardsemiconductor/VELDT-info/blob/master/ICE40LEDDriverUsageGuide.pdf) for information on LED control bus addressable registers and register field descriptions. +See [Appendix D of the iCE40 LED Driver Usage Guide](https://github.com/standardsemiconductor/VELDT-info/blob/main/ICE40LEDDriverUsageGuide.pdf) for information on LED control bus addressable registers and register field descriptions. ### UART | Byte 3 | Byte 2 | Byte 1 | Byte 0 | @@ -107,7 +107,7 @@ Status Byte: ``` ### SPI Flash -See [VELDT-info](https://github.com/standardsemiconductor/VELDT-info#veldt-info) for more information about the on-board [SPI flash chip](https://github.com/standardsemiconductor/VELDT-info/blob/master/AT25SF081.pdf) and the [Lattice SPI and SysBus interface](https://github.com/standardsemiconductor/VELDT-info/blob/master/AdvancediCE40SPII2CHardenedIPUsageGuide.pdf). +See [VELDT-info](https://github.com/standardsemiconductor/VELDT-info#veldt-info) for more information about the on-board [SPI flash chip](https://github.com/standardsemiconductor/VELDT-info/AT25SF081.pdf) and the [Lattice SPI and SysBus interface](https://github.com/standardsemiconductor/VELDT-info/AdvancediCE40SPII2CHardenedIPUsageGuide.pdf). #### Peripheral Register | Byte 3 | Byte 2 | Byte 1 | Byte 0 | diff --git a/lion-soc/lion-soc.cabal b/lion-soc/lion-soc.cabal index ec59af2..d4101a3 100644 --- a/lion-soc/lion-soc.cabal +++ b/lion-soc/lion-soc.cabal @@ -20,13 +20,13 @@ library hs-source-dirs: src default-language: Haskell2010 build-depends: - base >= 4.13 && < 4.17, + base >= 4.13 && < 4.21, clash-prelude >= 1.4 && < 1.7, generic-monoid >= 0.1 && < 0.2, - ice40-prim >= 0.3 && < 0.4, + ice40-prim >= 0.3 && < 0.3.1.4, lens, lion >= 0.4 && < 0.5, - mtl >= 2.2 && < 2.3, + mtl >= 2.2 && < 2.4, ghc-typelits-natnormalise, ghc-typelits-extra, ghc-typelits-knownnat diff --git a/lion-soc/src/Spi.hs b/lion-soc/src/Spi.hs index 52596a0..a826f8c 100644 --- a/lion-soc/src/Spi.hs +++ b/lion-soc/src/Spi.hs @@ -1,7 +1,9 @@ +{-# LANGUAGE CPP #-} + {-| Module : Spi Description : Lion SoC SPI peripheral -Copyright : (c) David Cox, 2021 +Copyright : (c) David Cox, 2024 License : BSD-3-Clause Maintainer : standardsemiconductor@gmail.com @@ -24,6 +26,10 @@ import Data.Monoid.Generic import qualified Ice40.Spi as S import Ice40.IO import Bus +#if __GLASGOW_HASKELL__ > 902 +import Control.Monad (when) +import Data.Monoid (First(..)) +#endif data SpiIO = SpiIO ("biwo" ::: Bit) ("bowi" ::: Bit) @@ -52,8 +58,8 @@ data FromSysBus = FromSysBus deriving Monoid via GenericMonoid FromSysBus makeLenses ''FromSysBus -data SysBus = SysBus - { _sbInstr :: Maybe (BitVector 8, Maybe (BitVector 8)) +data SysBus = SysBus + { _sbInstr :: Maybe (BitVector 8, Maybe (BitVector 8)) , _sbRecv :: BitVector 8 } deriving stock (Generic, Show, Eq) @@ -88,7 +94,7 @@ sysBusM = do Nothing -> -- idle, execute command let isWrite = bitToBool $ wr!(16 :: Index 32) adri = slice d15 d8 wr - dati = slice d7 d0 wr + dati = slice d7 d0 wr in sbInstr ?= if isWrite then (adri, Just dati) else (adri, Nothing) @@ -99,7 +105,7 @@ sysBusM = do then 0x01000000 else 0x00000000 -sysBus +sysBus :: HiddenClockResetEnable dom => Signal dom ToSysBus -> Signal dom FromSysBus @@ -120,7 +126,7 @@ spi toSpi = (spiIO, fromSpi) fromSysBus = sysBus $ ToSysBus <$> sbacko <*> sbdato <*> toSpi - + spiIO = SpiIO <$> biwo <*> bowi <*> wck <*> cs (biwo, bi) = biwoIO woe wo (bowi, wi) = bowiIO boe bo @@ -132,7 +138,7 @@ spi toSpi = (spiIO, fromSpi) adri = fromMaybe 0 . getFirst . _sbAdrI <$> fromSysBus dati = fromMaybe 0 . getFirst . _sbDatI <$> fromSysBus - (sbdato, sbacko, _, _, wo, woe, bo, boe, wcko, wckoe, bcsno, bcsnoe) + (sbdato, sbacko, _, _, wo, woe, bo, boe, wcko, wckoe, bcsno, bcsnoe) = S.spi "0b0000" rwi stbi @@ -144,8 +150,8 @@ spi toSpi = (spiIO, fromSpi) wcsni {-# NOINLINE biwoIO #-} -biwoIO - :: HiddenClock dom +biwoIO + :: HiddenClock dom => Signal dom Bit -> Signal dom Bit -> Unbundled dom (Bit, Bit) @@ -165,10 +171,10 @@ biwoIO woe wo = (biwo, bi) 0 {-# NOINLINE bowiIO #-} -bowiIO - :: HiddenClock dom - => Signal dom Bit - -> Signal dom Bit +bowiIO + :: HiddenClock dom + => Signal dom Bit + -> Signal dom Bit -> Unbundled dom (Bit, Bit) bowiIO boe bo = (bowi, wi) where @@ -186,10 +192,10 @@ bowiIO boe bo = (bowi, wi) 0 {-# NOINLINE wckIO #-} -wckIO - :: HiddenClock dom - => Signal dom Bit - -> Signal dom Bit +wckIO + :: HiddenClock dom + => Signal dom Bit + -> Signal dom Bit -> Unbundled dom (Bit, Bit) wckIO wckoe wcko = (wck, wcki) where @@ -207,10 +213,10 @@ wckIO wckoe wcko = (wck, wcki) 0 {-# NOINLINE csIO #-} -csIO - :: HiddenClock dom - => Signal dom (BitVector 4) - -> Signal dom (BitVector 4) +csIO + :: HiddenClock dom + => Signal dom (BitVector 4) + -> Signal dom (BitVector 4) -> Unbundled dom (Bit, Bit) csIO bcsnoe bcsno = (cs, wcsni) where @@ -226,5 +232,5 @@ csIO bcsnoe bcsno = (cs, wcsni) ((! (3 :: Index 4)) <$> bcsnoe) -- output enable ((! (3 :: Index 4)) <$> bcsno) -- dOut0 0 -- dOut1 - - + + diff --git a/lion-soc/src/Uart.hs b/lion-soc/src/Uart.hs index a45ac45..309c174 100644 --- a/lion-soc/src/Uart.hs +++ b/lion-soc/src/Uart.hs @@ -1,3 +1,5 @@ +{-# LANGUAGE CPP #-} + {-| Module : Uart Description : Lion Soc Uart Peripheral @@ -14,6 +16,10 @@ import Control.Lens hiding (Index, Empty) import Control.Monad.RWS import Data.Maybe ( isJust, fromMaybe ) import Data.Monoid.Generic +#if __GLASGOW_HASKELL__ > 902 +import Control.Monad (when, forM_) +import Data.Monoid (First(..)) +#endif -- | uart register -- 31 - 24 : 23 - 16 : 15 - 8 : 7 - 0 @@ -31,7 +37,7 @@ data ToUart = ToUart , _rx :: Bit } makeLenses ''ToUart - + -- | Receiver finite-state machine data RxFsm = RxIdle | RxStart @@ -55,7 +61,7 @@ data Uart = Uart } deriving stock (Generic, Show, Eq) deriving anyclass NFDataX -makeLenses ''Uart +makeLenses ''Uart -- | Construct a Uart mkUart :: Uart @@ -104,7 +110,7 @@ uartM = do txIdx .= 0 txBaud .= 0 txBuffer ?= frame wr - _ -> return () + _ -> return () -- read status rxS <- uses rxRecv $ boolToBV . isJust @@ -115,14 +121,14 @@ uartM = do -- receive rxIn <- view rx use rxFsm >>= \case - RxIdle -> + RxIdle -> when (rxIn == low) $ do rxBaud %= increment rxFsm %= increment RxStart -> do ctr <- rxBaud <<%= increment let baudHalf = maxBound `shiftR` 1 - when (ctr == baudHalf) $ do + when (ctr == baudHalf) $ do rxBaud .= 0 if rxIn == low then rxFsm %= increment @@ -132,7 +138,7 @@ uartM = do when (ctr == maxBound) $ do idx <- rxIdx <<%= increment rxBuffer %= (rxIn +>>) - when (idx == maxBound) $ + when (idx == maxBound) $ rxFsm %= increment RxStop -> do ctr <- rxBaud <<%= increment @@ -144,13 +150,13 @@ uartM = do uartMealy :: Uart -> ToUart -> (Uart, FromUart) uartMealy s i = (s', o) - where + where (_, s', o) = runRWS uartM i s uart - :: HiddenClockResetEnable dom + :: HiddenClockResetEnable dom => Signal dom Bit -- ^ uart rx - -> Signal dom (B.BusIn 'B.Uart) -- ^ soc bus + -> Signal dom (B.BusIn 'B.Uart) -- ^ soc bus -> Unbundled dom (Bit, B.BusOut 'B.Uart) -- ^ (uart tx, toCore) uart rxIn bus = (txOut, B.FromUart <$> uartOut) where diff --git a/lion.cabal b/lion.cabal index 6e9026b..5209b66 100644 --- a/lion.cabal +++ b/lion.cabal @@ -1,6 +1,6 @@ cabal-version: 2.4 name: lion -version: 0.4.0.0 +version: 0.4.0.1 synopsis: RISC-V Core description: Lion is a formally verified, 5-stage pipeline [RISC-V](https://riscv.org) core. Lion targets the [VELDT FPGA development board](https://standardsemiconductor.com) and is written in Haskell using [Clash](https://clash-lang.org). bug-reports: https://github.com/standardsemiconductor/lion/issues @@ -19,20 +19,20 @@ source-repository head location: https://github.com/standardsemiconductor/lion library - exposed-modules: Lion.Core - , Lion.Rvfi - other-modules: Lion.Alu - , Lion.Instruction - , Lion.Pipe - hs-source-dirs: src + exposed-modules: Lion.Core + , Lion.Rvfi + other-modules: Lion.Alu + , Lion.Instruction + , Lion.Pipe + hs-source-dirs: lib default-language: Haskell2010 - build-depends: - base >= 4.13 && < 4.17, + build-depends: + base >= 4.13 && < 4.21, generic-monoid >= 0.1 && < 0.2, - mtl >= 2.2 && < 2.3, - lens >= 4.19 && < 5.2, - ice40-prim >= 0.3 && < 0.3.1.4, - clash-prelude >= 1.2.5 && < 1.7, + mtl >= 2.2 && < 2.4, + lens >= 4.19 && < 5.4, + ice40-prim >= 0.3 && < 0.3.1.5, + clash-prelude >= 1.2.5 && < 1.9, ghc-typelits-natnormalise, ghc-typelits-extra, ghc-typelits-knownnat