cmblock.vcd

$date
	Mon Oct  7 08:50:13 2024
$end
$version
	Icarus Verilog
$end
$timescale
	1ps
$end
$scope module combinational_lock_tb $end
$var wire 1 ! unlock_led $end
$var wire 1 " q2 $end
$var wire 1 # q1 $end
$var wire 1 $ q0 $end
$var wire 1 % lock_led $end
$var reg 1 & clk $end
$var reg 1 ' clr_n $end
$var reg 1 ( data_in $end
$scope module UUT $end
$var wire 1 & clk $end
$var wire 1 ' clr_n $end
$var wire 1 ( data_in $end
$var wire 1 % lock_led $end
$var wire 1 ) r0 $end
$var wire 1 * r1 $end
$var wire 1 + r2 $end
$var wire 1 ! unlock_led $end
$var wire 1 " q2 $end
$var wire 1 # q1 $end
$var wire 1 $ q0 $end
$scope module sr $end
$var wire 1 & clk $end
$var wire 1 ' clr_n $end
$var wire 1 ( data_in $end
$var wire 1 , q2_n $end
$var wire 1 " q2 $end
$var wire 1 - q1_n $end
$var wire 1 # q1 $end
$var wire 1 . q0_n $end
$var wire 1 $ q0 $end
$scope module ff0 $end
$var wire 1 & clk $end
$var wire 1 ' clr_n $end
$var wire 1 ( d $end
$var wire 1 / pre_n $end
$var wire 1 . q_n $end
$var reg 1 $ q $end
$upscope $end
$scope module ff1 $end
$var wire 1 & clk $end
$var wire 1 ' clr_n $end
$var wire 1 $ d $end
$var wire 1 0 pre_n $end
$var wire 1 - q_n $end
$var reg 1 # q $end
$upscope $end
$scope module ff2 $end
$var wire 1 & clk $end
$var wire 1 ' clr_n $end
$var wire 1 # d $end
$var wire 1 1 pre_n $end
$var wire 1 , q_n $end
$var reg 1 " q $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
$comment Show the parameter values. $end
$dumpall
$end
#0
$dumpvars
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$end
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#35000
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#100000
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