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vc5: register spilling vs uniform loads #98

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anholt opened this issue Mar 28, 2018 · 0 comments
Open

vc5: register spilling vs uniform loads #98

anholt opened this issue Mar 28, 2018 · 0 comments

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@anholt
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anholt commented Mar 28, 2018

If we introduce register spilling in between a ldunif and its usage, we'll leave our address in r5 instead of what the previous code wanted. Need to fix this somehow (can we delay ldunif generation until after regalloc?)
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