From 72a525aa3dffd0573549b21c6d7a02ae4096887a Mon Sep 17 00:00:00 2001
From: "Travis F. Collins" <travis.collins@analog.com>
Date: Wed, 25 Sep 2024 15:05:13 -0600
Subject: [PATCH] Update HDL core version for Xilinx

Signed-off-by: Travis F. Collins <travis.collins@analog.com>
---
 adijif/fpgas/xilinx.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/adijif/fpgas/xilinx.py b/adijif/fpgas/xilinx.py
index 0808d90..652926c 100644
--- a/adijif/fpgas/xilinx.py
+++ b/adijif/fpgas/xilinx.py
@@ -26,7 +26,7 @@ class xilinx(xilinx_bf):
 
     max_serdes_lanes = 24
 
-    hdl_core_version = 1.0
+    hdl_core_version = 2.1
 
     available_speed_grades = [-1, -2, -3]
     speed_grade = -2