diff --git a/examples/draw/ad9680_draw.py b/examples/draw/ad9680_draw.py
new file mode 100644
index 0000000..369b409
--- /dev/null
+++ b/examples/draw/ad9680_draw.py
@@ -0,0 +1,34 @@
+import adijif as jif
+
+
+adc = jif.ad9680()
+
+# Check static
+adc.validate_config()
+
+required_clocks = adc.get_required_clocks()
+required_clock_names = adc.get_required_clock_names()
+
+# Add generic clock sources for solver
+clks = []
+for clock, name in zip(required_clocks, required_clock_names):
+    clk = jif.types.arb_source(name)
+    adc._add_equation(clk(adc.model) == clock)
+    clks.append(clk)
+
+# Solve
+solution = adc.model.solve(LogVerbosity="Quiet")
+settings = adc.get_config(solution)
+
+# Get clock values
+clock_values = {}
+for clk in clks:
+    clock_values.update(clk.get_config(solution))
+settings["clocks"] = clock_values
+
+print(settings)
+print(dir(adc))
+image_data = adc.draw(settings["clocks"])
+
+with open("ad9680_example.svg", "w") as f:
+    f.write(image_data)
\ No newline at end of file
diff --git a/examples/draw/xilinx_draw.py b/examples/draw/xilinx_draw.py
new file mode 100644
index 0000000..9922e6f
--- /dev/null
+++ b/examples/draw/xilinx_draw.py
@@ -0,0 +1,38 @@
+import adijif as jif
+from adijif.converters.converter import converter
+
+fpga = jif.xilinx()
+fpga.setup_by_dev_kit_name("vcu118")
+
+# class dummy_converter(converter):
+#     name = "dummy"
+
+# dc = dummy_converter()
+dc = jif.ad9680()
+
+
+fpga_ref = jif.types.arb_source("FPGA_REF")
+link_out_ref = jif.types.arb_source("LINK_OUT_REF")
+
+clocks = fpga.get_required_clocks(dc, fpga_ref(fpga.model), link_out_ref(fpga.model))
+print(clocks)
+
+solution = fpga.model.solve(LogVerbosity="Quiet")
+solution.write()
+
+settings = {}
+# Get clock values
+clock_values = {}
+for clk in [fpga_ref, link_out_ref]:
+    clock_values.update(clk.get_config(solution))
+settings["clocks"] = clock_values
+
+
+settings['fpga'] = fpga.get_config(dc, settings['clocks']['FPGA_REF'], solution)
+print(settings)
+
+
+image_data = fpga.draw(settings)
+
+with open("xilinx_example.svg", "w") as f:
+    f.write(image_data)
\ No newline at end of file