- Add left operator functions (ex: "5 + mipp::Reg" should work then!)
- Fix and improve GitHub actions
- Create a docker image with "Intel Software Development Emulator" to enable AVX-512 instructions emulation on the runners that does not support native AVX-512
- Find a workaround for the 16-bit SSE
compress
that requires BMI2 extension (remove_pext_u32
dependency, available since Haswell) - Add SVE to the code coverage
- Compile the examples in the `CMakeFiles.txt
- Add
compress
for NEONv1 with emulation ofvqtbl1q
based on twovtbl2
- Improve NEONv2
shuff
operations withvqtbl1q
instruction