From ffb79dffa2969e4248f5396fd87256b5a05e25cb Mon Sep 17 00:00:00 2001 From: Kamyar Mohajerani Date: Fri, 4 Oct 2024 17:01:31 -0400 Subject: [PATCH] fix fpga parsing --- src/xeda/flow/flow.py | 2 ++ src/xeda/flow/fpga.py | 5 +++-- src/xeda/flows/yosys/templates/read_files.tcl | 2 +- 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/src/xeda/flow/flow.py b/src/xeda/flow/flow.py index 1885d1ea..60637db7 100644 --- a/src/xeda/flow/flow.py +++ b/src/xeda/flow/flow.py @@ -146,6 +146,8 @@ def __init__(self, **data: Any) -> None: log.debug("Settings.__init__(): data=%s", data) super().__init__(**data) except ValidationError as e: + if data.get("debug", None): + raise e raise FlowSettingsError(validation_errors(e.errors()), e.model, e.json()) from e class Results(Box): diff --git a/src/xeda/flow/fpga.py b/src/xeda/flow/fpga.py index b89018ed..245e5250 100644 --- a/src/xeda/flow/fpga.py +++ b/src/xeda/flow/fpga.py @@ -121,8 +121,9 @@ def set_xc_family(s: str, gen=None): ) set_if_not_exist("capacity", lc + "K") pins = match_xc6.group("pins") - set_if_not_exist("package", match_xc6.group("pkg") + pins) - set_if_not_exist("pins", try_convert(pins, int)) + if pins: + set_if_not_exist("package", match_xc6.group("pkg") + pins) + set_if_not_exist("pins", try_convert(pins, int)) set_if_not_exist("speed", match_xc6.group("speed_grade")) return values match_xc7 = re.match( diff --git a/src/xeda/flows/yosys/templates/read_files.tcl b/src/xeda/flows/yosys/templates/read_files.tcl index b252ba9f..4cac78e7 100644 --- a/src/xeda/flows/yosys/templates/read_files.tcl +++ b/src/xeda/flows/yosys/templates/read_files.tcl @@ -19,7 +19,7 @@ yosys read_systemverilog -defer {{settings.read_systemverilog_flags|join(" ")}} {%- endif %} {%- endfor %} -{% set vhdl_files = design.sources_of_type("Vhdl", rtl=true, tb=false) | map('quote') %} +{% set vhdl_files = design.sources_of_type("Vhdl", rtl=true, tb=false) | map('quote') | list %} {%- if vhdl_files %} yosys log -stdout "** Elaborating VHDL files **" yosys plugin -i ghdl